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stm32l4, stm32f7, stm32h7: fix qspi (unused) register addresses

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This commit is contained in:
Kian Karas 2024-05-28 22:29:02 +02:00 committed by Alan Carvalho de Assis
parent 46a8c665d7
commit b55ed92361
4 changed files with 4 additions and 4 deletions
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2
arch/arm/src/stm32f7/hardware/stm32_qspi.h
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@ -207,7 +207,7 @@
/* Low-Power Timeout Register */
#define QSPI_LPTR_TIMEOUT_SHIFT (0) /* Bits 0-15: Timeout period */
#define QSPI_LPTR_TIMEOUT_MASK (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
#define QSPI_LPTR_TIMEOUT_MASK (0xFFff << QSPI_LPTR_TIMEOUT_SHIFT)
/****************************************************************************
* Public Types

2
arch/arm/src/stm32h7/hardware/stm32_qspi.h
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@ -207,7 +207,7 @@
/* Low-Power Timeout Register */
#define QSPI_LPTR_TIMEOUT_SHIFT (0) /* Bits 0-15: Timeout period */
#define QSPI_LPTR_TIMEOUT_MASK (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
#define QSPI_LPTR_TIMEOUT_MASK (0xFFff << QSPI_LPTR_TIMEOUT_SHIFT)
/****************************************************************************
* Public Types

2
arch/arm/src/stm32h7/stm32_qspi.c
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@ -549,7 +549,7 @@ static void qspi_dumpregs(struct stm32h7_qspidev_s *priv, const char *msg)
(regval & QSPI_CCR_INSTRUCTION_MASK) >> QSPI_CCR_INSTRUCTION_SHIFT,
(regval & QSPI_CCR_IMODE_MASK) >> QSPI_CCR_IMODE_SHIFT,
(regval & QSPI_CCR_ADMODE_MASK) >> QSPI_CCR_ADMODE_SHIFT,
(regval & QSPI_CCR_ADSIZE_MASK) >> QSPI_CCR_ABSIZE_SHIFT,
(regval & QSPI_CCR_ADSIZE_MASK) >> QSPI_CCR_ADSIZE_SHIFT,
(regval & QSPI_CCR_ABMODE_MASK) >> QSPI_CCR_ABMODE_SHIFT,
(regval & QSPI_CCR_ABSIZE_MASK) >> QSPI_CCR_ABSIZE_SHIFT,
(regval & QSPI_CCR_DCYC_MASK) >> QSPI_CCR_DCYC_SHIFT,

2
arch/arm/src/stm32l4/hardware/stm32l4_qspi.h
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@ -205,7 +205,7 @@
/* Low-Power Timeout Register */
#define QSPI_LPTR_TIMEOUT_SHIFT (0) /* Bits 0-15: Timeout period */
#define QSPI_LPTR_TIMEOUT_MASK (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
#define QSPI_LPTR_TIMEOUT_MASK (0xFFff << QSPI_LPTR_TIMEOUT_SHIFT)
/****************************************************************************
* Public Types