STM32 DAC DMA fixes from John Wharington
This commit is contained in:
Gregory Nutt
parent
413aba0bf5
commit
b57f54fbd0
@ -5229,4 +5229,7 @@
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(2013-7-29).
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* arch/arm/src/armv7-a/arm_cache.S: Separate the bigger cache
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operations into separater files (2013-7-29).
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* arch/arm/src/stm32/stm32_dac.c: Fixed numerous DAC driver
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errors and added support for DAC DMA (contributed by John
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Wharington, 2013-7-30).
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@ -675,7 +675,7 @@ config STM32_SPI1
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config STM32_SPI2
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bool "SPI2"
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default n
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depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY) || (STM32_STM32F10XX && (STM32_HIGHDENSITY || STM32_MEDIUMDENSITY))
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depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY) || (STM32_STM32F10XX && (STM32_HIGHDENSITY || STM32_MEDIUMDENSITY)) || STM32_STM32F30XX
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select SPI
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select STM32_SPI
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@ -1121,7 +1121,7 @@ config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
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config STM32_CCMEXCLUDE
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bool "Exclude CCM SRAM from the heap"
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depends on STM32_STM32F20XX || STM32_STM32F40XX
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depends on STM32_STM32F20XX || STM32_STM32F40XX || STM32_STM32F30XX
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default y if ARCH_DMA || ELF
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---help---
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Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA
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@ -2202,6 +2202,61 @@ config STM32_TIM14_DAC2
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endchoice
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menu "DAC Configuration"
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depends on STM32_DAC1 || STM32_DAC2
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config STM32_DAC1_DMA
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bool "DAC1 DMA"
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depends on STM32_DAC1
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default n
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---help---
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If DMA is selected, then a timer and output frequency must also be
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provided to support the DMA transfer. The DMA transfer could be
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supported by and EXTI trigger, but this feature is not currently
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supported by the driver.
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if STM32_DAC1_DMA
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config STM32_DAC1_TIMER
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int "DAC1 timer"
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range 2 7
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config STM32_DAC1_TIMER_FREQUENCY
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int "DAC1 timer frequency"
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default 0
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range 0 14
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endif
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config STM32_DAC2_DMA
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bool "DAC2 DMA"
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depends on STM32_DAC2
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default n
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---help---
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If DMA is selected, then a timer and output frequency must also be
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provided to support the DMA transfer. The DMA transfer could be
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supported by and EXTI trigger, but this feature is not currently
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supported by the driver.
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if STM32_DAC2_DMA
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config STM32_DAC2_TIMER
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int "DAC2 timer"
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default 0
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range 2 7
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config STM32_DAC2_TIMER_FREQUENCY
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int "DAC2 timer frequency"
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default 0
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endif
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config STM32_DAC_DMA_BUFFER_SIZE
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int "DAC DMA buffer size"
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default 256
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endmenu
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config STM32_USART
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bool
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@ -103,7 +103,7 @@
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# define DAC_CR_TSEL_TIM4 (5 << DAC_CR_TSEL_SHIFT) /* Timer 4 TRGO event */
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# define DAC_CR_TSEL_EXT9 (6 << DAC_CR_TSEL_SHIFT) /* External line9 */
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# define DAC_CR_TSEL_SW (7 << DAC_CR_TSEL_SHIFT) /* Software trigger */
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#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation */enable
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#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation */
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#define DAC_CR_WAVE_MASK (3 << DAC_CR_WAVE_SHIFT)
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# define DAC_CR_WAVE_DISABLED (0 << DAC_CR_WAVE_SHIFT) /* Wave generation disabled */
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# define DAC_CR_WAVE_NOISE (1 << DAC_CR_WAVE_SHIFT) /* Noise wave generation enabled */
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@ -291,7 +291,7 @@
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#define STM32_DMA2_CHAN1 (7)
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#define STM32_DMA2_CHAN2 (8)
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#define STM32_DMA2_CHAN3 (1)
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#define STM32_DMA2_CHAN3 (9)
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#define STM32_DMA2_CHAN4 (10)
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#define STM32_DMA2_CHAN5 (11)
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@ -97,6 +97,15 @@
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#define GPIO_COMP6_OUT_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN10)
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#define GPIO_COMP7_OUT (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN2)
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/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
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* (PA4 or PA5) is automatically connected to the analog converter output
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* (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin
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* should first be configured to analog (AIN)".
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*/
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#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
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/* I2C */
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#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN15)
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/stm32_dac.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -43,6 +43,7 @@
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <math.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <debug.h>
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@ -57,6 +58,8 @@
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#include "chip.h"
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#include "stm32.h"
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#include "stm32_dac.h"
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#include "stm32_rcc.h"
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#include "stm32_dma.h"
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#ifdef CONFIG_DAC
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@ -85,9 +88,9 @@
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/* DMA configuration. */
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#if defined(CONFIG_STM32_DAC1_DMA) || defined(CONFIG_STM32_DAC2_DMA)
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# if defined(CONFIG_STM32_STM32F10XX)
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# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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# ifndef CONFIG_STM32_DMA2
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# warning "STM32 F1 DAC DMA support requires CONFIG_STM32_DMA2"
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# warning "STM32 F1/F3 DAC DMA support requires CONFIG_STM32_DMA2"
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# undef CONFIG_STM32_DAC1_DMA
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# undef CONFIG_STM32_DAC2_DMA
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# endif
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@ -139,7 +142,7 @@
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#undef HAVE_DMA
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#if defined(CONFIG_STM32_DAC1_DMA) || defined(CONFIG_STM32_DAC2_DMA)
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# if defined(CONFIG_STM32_STM32F10XX)
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# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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# define HAVE_DMA 1
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# define DAC_DMA 2
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# define DAC1_DMA_CHAN DMACHAN_DAC_CHAN1
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@ -149,7 +152,7 @@
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# define DAC_DMA 1
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# define DAC1_DMA_CHAN DMAMAP_DAC1
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# define DAC2_DMA_CHAN DMAMAP_DAC2
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# endif
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# endif
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#endif
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/* Timer configuration. The STM32 supports 8 different trigger for DAC
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@ -170,11 +173,20 @@
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* This driver does not support the EXTI trigger.
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*/
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#undef NEED_TIM6
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#undef NEED_TIM3
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#undef NEED_TIM8
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#undef NEED_TIM7
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#undef NEED_TIM5
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#undef NEED_TIM2
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#undef NEED_TIM4
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#ifdef CONFIG_STM32_DAC1_DMA
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# if CONFIG_STM32_DAC1_TIMER == 6
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# ifndef CONFIG_STM32_TIM6_DAC
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# error "CONFIG_STM32_TIM6_DAC required for DAC1"
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# endif
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# define NEED_TIM6
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6
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# define DAC1_TIMER_BASE STM32_TIM6_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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@ -182,6 +194,7 @@
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# ifndef CONFIG_STM32_TIM3_DAC
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# error "CONFIG_STM32_TIM3_DAC required for DAC1"
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# endif
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# define NEED_TIM3
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM3
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# define DAC1_TIMER_BASE STM32_TIM3_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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@ -189,6 +202,7 @@
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# ifndef CONFIG_STM32_TIM8_DAC
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# error "CONFIG_STM32_TIM8_DAC required for DAC1"
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# endif
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# define NEED_TIM8
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8
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# define DAC1_TIMER_BASE STM32_TIM8_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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@ -196,12 +210,14 @@
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# ifndef CONFIG_STM32_TIM7_DAC
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# error "CONFIG_STM32_TIM7_DAC required for DAC1"
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# endif
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# define NEED_TIM7
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7
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# define DAC1_TIMER_BASE STM32_TIM7_BASE
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# elif CONFIG_STM32_DAC1_TIMER == 5
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# ifndef CONFIG_STM32_TIM5_DAC
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# error "CONFIG_STM32_TIM5_DAC required for DAC1"
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# endif
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# define NEED_TIM5
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5
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# define DAC1_TIMER_BASE STM32_TIM5_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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@ -209,6 +225,7 @@
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# ifndef CONFIG_STM32_TIM2_DAC
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# error "CONFIG_STM32_TIM2_DAC required for DAC1"
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# endif
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# define NEED_TIM2
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2
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# define DAC1_TIMER_BASE STM32_TIM2_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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@ -216,6 +233,7 @@
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# ifndef CONFIG_STM32_TIM4_DAC
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# error "CONFIG_STM32_TIM4_DAC required for DAC1"
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# endif
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# define NEED_TIM4
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4
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# define DAC1_TIMER_BASE STM32_TIM4_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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@ -283,9 +301,14 @@
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_SW
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#endif
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#ifndef CONFIG_STM32_DAC_DMA_BUFFER_SIZE
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# define CONFIG_STM32_DAC_DMA_BUFFER_SIZE 256
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#endif
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/* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and
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* CONFIG_STM32_DACn_TIMER_FREQUENCY.
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*/
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#warning "Missing Logic"
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/****************************************************************************
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@ -306,13 +329,17 @@ struct stm32_chan_s
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uint8_t inuse : 1; /* True, the driver is in use and not available */
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#ifdef HAVE_DMA
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uint8_t hasdma : 1; /* True, this channel supports DMA */
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uint8_t timer; /* Timer number 2-8 */
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#endif
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uint8_t intf; /* DAC zero-based interface number (0 or 1) */
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uint32_t dro; /* Data output register */
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#ifdef HAVE_DMA
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uint16_t dmachan; /* DMA channel needed by this DAC */
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DMA_HANDLE dma; /* Allocated DMA channel */
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uint32_t tsel; /* CR trigger select value */
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uint32_t tbase; /* Timer base address */
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uint32_t tfrequency; /* Timer frequency */
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uint16_t dmabuffer[CONFIG_STM32_DAC_DMA_BUFFER_SIZE]; /* DMA transfer buffer */
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#endif
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};
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@ -340,7 +367,6 @@ static void dac_shutdown(FAR struct dac_dev_s *dev);
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static void dac_txint(FAR struct dac_dev_s *dev, bool enable);
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static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg);
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static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg);
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static int dac_interrupt(int irq, void *context);
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/* Initialization */
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@ -367,14 +393,17 @@ static const struct dac_ops_s g_dacops =
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#ifdef CONFIG_STM32_DAC1
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static struct stm32_chan_s g_dac1priv =
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{
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.intf = 0;
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.intf = 0,
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.dro = STM32_DAC_DHR12R1,
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#ifdef CONFIG_STM32_DAC1_DMA
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.hasdma = 1;
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.hasdma = 1,
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.dmachan = DAC1_DMA_CHAN,
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.timer = CONFIG_STM32_DAC1_TIMER,
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.tsel = DAC1_TSEL_VALUE,
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.tbase = DAC1_TIMER_BASE
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.tbase = DAC1_TIMER_BASE,
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.tfrequency = CONFIG_STM32_DAC1_TIMER_FREQUENCY,
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#endif
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}
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};
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static struct dac_dev_s g_dac1dev =
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{
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@ -386,14 +415,17 @@ static struct dac_dev_s g_dac1dev =
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#ifdef CONFIG_STM32_DAC2
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static struct stm32_chan_s g_dac2priv =
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{
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.intf = 1;
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.intf = 1,
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.dro = STM32_DAC_DHR12R2,
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#ifdef CONFIG_STM32_DAC2_DMA
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.hasdma = 1;
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.hasdma = 1,
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.dmachan = DAC2_DMA_CHAN,
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.tsel = DAC2_TSEL_VALUE.
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.timer = CONFIG_STM32_DAC2_TIMER,
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.tsel = DAC2_TSEL_VALUE,
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.tbase = DAC2_TIMER_BASE
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.tfrequency = CONFIG_STM32_DAC2_TIMER_FREQUENCY,
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#endif
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}
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};
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static struct dac_dev_s g_dac2dev =
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{
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@ -408,6 +440,30 @@ static struct stm32_dac_s g_dacblock;
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_dac_modify_cr
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*
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* Description:
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* Modify the contents of the DAC control register.
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*
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* Input Parameters:
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* priv - Driver state instance
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* clearbits - Bits in the control register to be cleared
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* setbits - Bits in the control register to be set
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void stm32_dac_modify_cr(FAR struct stm32_chan_s *priv,
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uint32_t clearbits, uint32_t setbits)
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{
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uint32_t cr = getreg32(STM32_DAC_CR);
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modifyreg32(STM32_DAC_CR, clearbits << (priv->intf*16), setbits << (priv->intf*16));
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uint32_t cr1 = getreg32(STM32_DAC_CR);
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}
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/****************************************************************************
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* Name: tim_getreg
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*
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@ -445,12 +501,38 @@ static uint32_t tim_getreg(struct stm32_chan_s *chan, int offset)
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*
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****************************************************************************/
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#ifdef HAVE_DMA
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static void tim_putreg(struct stm32_chan_s *chan, int offset, uint32_t value)
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{
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putreg32(value, chan->tbase + offset);
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}
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#endif
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/****************************************************************************
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* Name: tim_modifyreg
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*
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* Description:
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* Modify the value of an DMA timer register.
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*
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* Input Parameters:
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* priv - Driver state instance
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* offset - The timer register offset
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* clear_bits - Bits in the control register to be cleared
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* set_bits - Bits in the control register to be set
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef HAVE_DMA
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static void tim_modifyreg(struct stm32_chan_s *chan, int offset,
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uint32_t clear_bits, uint32_t set_bits)
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{
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modifyreg32(chan->tbase + offset, clear_bits, set_bits);
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}
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#endif
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/****************************************************************************
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* Name: dac_interrupt
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*
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@ -564,6 +646,23 @@ static void dac_txint(FAR struct dac_dev_s *dev, bool enable)
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# warning "Missing logic"
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}
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/****************************************************************************
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* Name: dac_dmatxcallback
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*
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* Description:
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* DMA callback function.
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*
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* Input Parameters:
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void dac_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
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{
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}
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/****************************************************************************
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* Name: dac_send
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*
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@ -579,8 +678,14 @@ static void dac_txint(FAR struct dac_dev_s *dev, bool enable)
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static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
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{
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struct stm32_chan_s * chan = dev->ad_priv;
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/* Enable DAC Channel */
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stm32_dac_modify_cr(chan, 0, DAC_CR_EN);
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#ifdef HAVE_DMA
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if (priv->hasdma)
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if (chan->hasdma)
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{
|
||||
/* Configure the DMA stream/channel.
|
||||
*
|
||||
@ -597,23 +702,47 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
|
||||
* - Memory Burst: single
|
||||
* - Peripheral Burst: single
|
||||
*/
|
||||
#warning "Missing logic"
|
||||
|
||||
uint32_t ccr =
|
||||
DMA_CCR_MSIZE_16BITS | /* Memory size */
|
||||
DMA_CCR_PSIZE_16BITS | /* Peripheral size */
|
||||
DMA_CCR_MINC | /* Memory increment mode */
|
||||
DMA_CCR_CIRC | /* Circular buffer */
|
||||
DMA_CCR_DIR; /* Read from memory */
|
||||
|
||||
stm32_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer,
|
||||
CONFIG_STM32_DAC_DMA_BUFFER_SIZE, ccr);
|
||||
|
||||
/* Enable DMA */
|
||||
#warning "Missing logic"
|
||||
|
||||
/* Enable DAC Channel */
|
||||
#warning "Missing logic"
|
||||
stm32_dmastart(chan->dma, dac_dmatxcallback, chan, false);
|
||||
|
||||
/* Enable DMA for DAC Channel */
|
||||
#warning "Missing logic"
|
||||
|
||||
stm32_dac_modify_cr(chan, 0, DAC_CR_DMAEN);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* Non-DMA transfer */
|
||||
#warning "Missing logic"
|
||||
|
||||
putreg16(msg->am_data, chan->dro);
|
||||
#ifdef CONFIG_STM32_DAC2
|
||||
if (chan->intf)
|
||||
{
|
||||
dac_txdone(&g_dac2dev);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
dac_txdone(&g_dac1dev);
|
||||
}
|
||||
}
|
||||
return -ENOSYS;
|
||||
|
||||
/* Reset counters (generate an update) */
|
||||
|
||||
tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -652,16 +781,114 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
|
||||
#ifdef HAVE_DMA
|
||||
static int dac_timinit(struct stm32_chan_s *chan)
|
||||
{
|
||||
uint32_t prescaler;
|
||||
uint32_t numerator;
|
||||
uint32_t regaddr;
|
||||
uint32_t setbits;
|
||||
|
||||
/* Configure the time base: Timer period, prescaler, clock division,
|
||||
* counter mode (up).
|
||||
*/
|
||||
#warning "Missing Logic"
|
||||
|
||||
/* Enable the timer. At most, two of the following cases (pluse the
|
||||
* default) will be enabled
|
||||
*/
|
||||
|
||||
numerator = 2 * STM32_TIM27_FREQUENCY;
|
||||
regaddr = STM32_RCC_APB1ENR;
|
||||
|
||||
switch (chan->timer)
|
||||
{
|
||||
#ifdef NEED_TIM2
|
||||
case 2:
|
||||
setbits = RCC_APB1ENR_TIM2EN;
|
||||
break;
|
||||
#endif
|
||||
#ifdef NEED_TIM3
|
||||
case 3:
|
||||
setbits = RCC_APB1ENR_TIM3EN;
|
||||
break;
|
||||
#endif
|
||||
#ifdef NEED_TIM4
|
||||
case 4:
|
||||
setbits = RCC_APB1ENR_TIM4EN;
|
||||
break;
|
||||
#endif
|
||||
#ifdef NEED_TIM5
|
||||
case 5:
|
||||
setbits = RCC_APB1ENR_TIM5EN;
|
||||
break;
|
||||
#endif
|
||||
#ifdef NEED_TIM6
|
||||
case 6:
|
||||
setbits = RCC_APB1ENR_TIM6EN;
|
||||
break;
|
||||
#endif
|
||||
#ifdef NEED_TIM8
|
||||
case 8:
|
||||
regaddr = STM32_RCC_APB2ENR;
|
||||
setbits = RCC_APB2ENR_TIM8EN;
|
||||
numerator = 2 * STM32_TIM18_FREQUENCY
|
||||
break;
|
||||
#endif
|
||||
#ifdef NEED_TIM7
|
||||
case 7:
|
||||
setbits = RCC_APB1ENR_TIM7EN;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
adbg("Could not enable timer\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the timer. */
|
||||
|
||||
modifyreg32(regaddr, 0, setbits);
|
||||
|
||||
/* Calculate the pre-scaler value */
|
||||
|
||||
prescaler = numerator / chan->tfrequency;
|
||||
|
||||
/* We need to decrement value for '1', but only, if we are allowed to
|
||||
* not to cause underflow. Check for overflow.
|
||||
*/
|
||||
|
||||
if (prescaler > 0)
|
||||
{
|
||||
prescaler--;
|
||||
}
|
||||
|
||||
if (prescaler > 0xffff)
|
||||
{
|
||||
prescaler = 0xffff;
|
||||
}
|
||||
|
||||
/* Set prescaler */
|
||||
|
||||
tim_putreg(chan, STM32_BTIM_PSC_OFFSET, 0);
|
||||
|
||||
/* Set period */
|
||||
|
||||
tim_putreg(chan, STM32_BTIM_ARR_OFFSET, prescaler);
|
||||
|
||||
/* Count mode up, auto reload */
|
||||
|
||||
tim_modifyreg(chan, STM32_BTIM_CR1_OFFSET, 0, ATIM_CR1_ARPE);
|
||||
|
||||
/* Selection TRGO selection: update */
|
||||
#warning "Missing Logic"
|
||||
|
||||
tim_modifyreg(chan, STM32_BTIM_CR2_OFFSET, ATIM_CR2_MMS_MASK,
|
||||
ATIM_CR2_MMS_UPDATE);
|
||||
|
||||
/* Update DMA request enable ???? */
|
||||
#if 0
|
||||
tim_modifyreg(chan, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UDE);
|
||||
#endif
|
||||
|
||||
/* Enable the counter */
|
||||
#warning "Missing Logic"
|
||||
|
||||
tim_modifyreg(chan, STM32_BTIM_CR1_OFFSET, 0, ATIM_CR1_CEN);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -681,6 +908,8 @@ static int dac_timinit(struct stm32_chan_s *chan)
|
||||
|
||||
static int dac_chaninit(struct stm32_chan_s *chan)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Is the selected channel already in-use? */
|
||||
|
||||
if (chan->inuse)
|
||||
@ -706,17 +935,33 @@ static int dac_chaninit(struct stm32_chan_s *chan)
|
||||
* - Set wave generation == None.
|
||||
* - Enable the output buffer.
|
||||
*/
|
||||
#warning "Missing logic"
|
||||
|
||||
/* Determine if DMA is supported by this channel */
|
||||
/* Disable before change */
|
||||
|
||||
stm32_dac_modify_cr(chan, DAC_CR_EN, 0);
|
||||
|
||||
uint16_t clear =
|
||||
DAC_CR_TSEL_MASK | DAC_CR_MAMP_MASK | DAC_CR_WAVE_MASK | DAC_CR_BOFF;
|
||||
uint16_t set =
|
||||
chan->tsel | /* Set trigger source (SW or timer TRGO event) */
|
||||
DAC_CR_MAMP_AMP1 | /* Set waveform characteristics */
|
||||
DAC_CR_WAVE_DISABLED | /* Set no noise */
|
||||
DAC_CR_BOFF; /* Enable output buffer */
|
||||
stm32_dac_modify_cr(chan, clear, set);
|
||||
|
||||
#ifdef HAVE_DMA
|
||||
if (priv->hasdma)
|
||||
{
|
||||
/* Yes.. allocate a DMA channel */
|
||||
/* Determine if DMA is supported by this channel */
|
||||
|
||||
priv->dma = stm32_dmachannel(priv->dmachan);
|
||||
if (!priv->dma)
|
||||
if (chan->hasdma)
|
||||
{
|
||||
/* Yes.. DAC trigger enable */
|
||||
|
||||
stm32_dac_modify_cr(chan, 0, DAC_CR_TEN);
|
||||
|
||||
/* Allocate a DMA channel */
|
||||
|
||||
chan->dma = stm32_dmachannel(chan->dmachan);
|
||||
if (!chan->dma)
|
||||
{
|
||||
adbg("Failed to allocate a DMA channel\n");
|
||||
return -EBUSY;
|
||||
@ -730,6 +975,7 @@ static int dac_chaninit(struct stm32_chan_s *chan)
|
||||
adbg("Failed to initialize the DMA timer: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -770,12 +1016,12 @@ static int dac_blockinit(void)
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(STM32_RCC_APB1RSTR);
|
||||
regval |= RCC_APB1RSTR_DACRST
|
||||
regval |= RCC_APB1RSTR_DACRST;
|
||||
putreg32(regval, STM32_RCC_APB1RSTR);
|
||||
|
||||
/* Take the DAC out of reset state */
|
||||
|
||||
regval &= ~RCC_APB1RSTR_DACRST
|
||||
regval &= ~RCC_APB1RSTR_DACRST;
|
||||
putreg32(regval, STM32_RCC_APB1RSTR);
|
||||
irqrestore(flags);
|
||||
|
||||
@ -817,7 +1063,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
|
||||
if (intf == 1)
|
||||
{
|
||||
avdbg("DAC1 Selected\n");
|
||||
dev = &g_dacdev1;
|
||||
dev = &g_dac1dev;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
@ -831,6 +1077,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
|
||||
#endif
|
||||
{
|
||||
adbg("No such DAC interface: %d\n", intf);
|
||||
errno = ENODEV;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -840,7 +1087,8 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
|
||||
if (ret < 0)
|
||||
{
|
||||
adbg("Failed to initialize the DAC block: %d\n", ret);
|
||||
return ret;
|
||||
errno = ret;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Configure the selected DAC channel */
|
||||
@ -850,7 +1098,8 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
|
||||
if (ret < 0)
|
||||
{
|
||||
adbg("Failed to initialize DAC channel %d: %d\n", intf, ret);
|
||||
return ret;
|
||||
errno = ret;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return dev;
|
||||
|
||||
@ -58,7 +58,7 @@
|
||||
|
||||
/* Only for the STM32F10xx family for now */
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F10XX
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -157,7 +157,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
|
||||
},
|
||||
{
|
||||
.chan = 3,
|
||||
#ifdef CONFIG_STM32_CONNECTIVITYLINE
|
||||
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
|
||||
.irq = STM32_IRQ_DMA2CH4,
|
||||
#else
|
||||
.irq = STM32_IRQ_DMA2CH45,
|
||||
@ -166,7 +166,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
|
||||
},
|
||||
{
|
||||
.chan = 4,
|
||||
#ifdef CONFIG_STM32_CONNECTIVITYLINE
|
||||
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
|
||||
.irq = STM32_IRQ_DMA2CH5,
|
||||
#else
|
||||
.irq = STM32_IRQ_DMA2CH45,
|
||||
@ -288,7 +288,7 @@ static int stm32_dmainterrupt(int irq, void *context)
|
||||
}
|
||||
else
|
||||
#if STM32_NDMA > 1
|
||||
#ifdef CONFIG_STM32_CONNECTIVITYLINE
|
||||
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
|
||||
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
|
||||
#else
|
||||
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
|
||||
@ -615,10 +615,12 @@ bool stm32_dmacapable(uint32_t maddr)
|
||||
{
|
||||
switch (maddr & STM32_REGION_MASK)
|
||||
{
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
case STM32_FSMC_BANK1:
|
||||
case STM32_FSMC_BANK2:
|
||||
case STM32_FSMC_BANK3:
|
||||
case STM32_FSMC_BANK4:
|
||||
#endif
|
||||
case STM32_SRAM_BASE:
|
||||
case STM32_CODE_BASE:
|
||||
/* All RAM and flash is supported */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user