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Merge branch 'xmc4'

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This commit is contained in:
Gregory Nutt 2017-03-18 06:48:59 -06:00
commit b582d0b5df
54 changed files with 11040 additions and 9 deletions
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35
arch/arm/Kconfig
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@ -151,6 +151,14 @@ config ARCH_CHIP_LPC43XX
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
config ARCH_CHIP_MOXART
bool "MoxART"
select ARCH_ARM7TDMI
select ARCH_HAVE_RESET
select ARCH_HAVE_SERIAL_TERMIOS
---help---
MoxART family
config ARCH_CHIP_NUC1XX
bool "Nuvoton NUC100/120"
select ARCH_CORTEXM0
@ -270,13 +278,18 @@ config ARCH_CHIP_TMS570
---help---
TI TMS570 family
config ARCH_CHIP_MOXART
bool "MoxART"
select ARCH_ARM7TDMI
select ARCH_HAVE_RESET
select ARCH_HAVE_SERIAL_TERMIOS
config ARCH_CHIP_XMC4
bool "Infineon XMC4xxx"
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_I2CRESET
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
MoxART family
Infineon XMC4xxx(ARM Cortex-M4) architectures
endchoice
@ -421,6 +434,7 @@ config ARCH_CHIP
default "lpc2378" if ARCH_CHIP_LPC2378
default "lpc31xx" if ARCH_CHIP_LPC31XX
default "lpc43xx" if ARCH_CHIP_LPC43XX
default "moxart" if ARCH_CHIP_MOXART
default "nuc1xx" if ARCH_CHIP_NUC1XX
default "sama5" if ARCH_CHIP_SAMA5
default "samdl" if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
@ -431,7 +445,7 @@ config ARCH_CHIP
default "stm32l4" if ARCH_CHIP_STM32L4
default "str71x" if ARCH_CHIP_STR71X
default "tms570" if ARCH_CHIP_TMS570
default "moxart" if ARCH_CHIP_MOXART
default "xmc4" if ARCH_CHIP_XMC4
config ARM_TOOLCHAIN_IAR
bool
@ -662,6 +676,9 @@ endif
if ARCH_CHIP_LPC43XX
source arch/arm/src/lpc43xx/Kconfig
endif
if ARCH_CHIP_MOXART
source arch/arm/src/moxart/Kconfig
endif
if ARCH_CHIP_NUC1XX
source arch/arm/src/nuc1xx/Kconfig
endif
@ -692,8 +709,8 @@ endif
if ARCH_CHIP_TMS570
source arch/arm/src/tms570/Kconfig
endif
if ARCH_CHIP_MOXART
source arch/arm/src/moxart/Kconfig
if ARCH_CHIP_XMC4
source arch/arm/src/xmc4/Kconfig
endif
endif # ARCH_ARM

130
arch/arm/include/xmc4/chip.h Normal file
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@ -0,0 +1,130 @@
/************************************************************************************
* arch/arm/include/xmc4/chip.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_XM4_CHIP_H
#define __ARCH_ARM_INCLUDE_XM4_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_XMC4500)
# define XM4_NUSIC 3 /* Three USIC modules: USCI0-2 */
#else
# error "Unsupported XMC4xxx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
* the priority of the corresponding interrupt. The XMC4500 implements only
* bits[7:2] of this field, bits[1:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xfc /* All bits[7:2] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x04 /* Steps between supported priority values */
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the up_irq_save() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_XM4_CHIP_H */

120
arch/arm/include/xmc4/irq.h Normal file
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@ -0,0 +1,120 @@
/****************************************************************************
* arch/arm/include/xmc4/irq.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_XMC4_IRQ_H
#define __ARCH_ARM_INCLUDE_XMC4_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define XMC4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define XMC4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define XMC4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define XMC4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define XMC4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define XMC4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define XMC4_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define XMC4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define XMC4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define XMC4_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are chip-specific */
#define XMC4_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_XMC4500)
# include <arch/xmc4/xmc4500_irq.h>
#else
/* The interrupt vectors for other parts are defined in other documents and may or
* may not be the same as above (the family members are all very similar) This
* error just means that you have to look at the document and determine for yourself
* if the vectors are the same.
*/
# error "No IRQ numbers for this XMC4xxx part"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_XMC4_IRQ_H */

225
arch/arm/include/xmc4/xmc4500_irq.h Normal file
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@ -0,0 +1,225 @@
/*****************************************************************************
* arch/arm/include/xmc4/xmc4500_.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H
#define xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H
/*****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
*
* External interrupts (vectors >= 16)
*
* Acronyms:
* ADC - Analog to Digital Converter
* CCU - Capture Compare Unit
* DAC - Digital to Analog Converter
* DSD - Delta Sigmoid Demodulator
* ERU - External Request Unit
* FCE - Flexible CRC Engine
* GPDMA - General Purpose DMA
* LEDTS - LED and Touch Sense Control Unit
* PMU - Program Management Unit
* POSIF - Position Interface
* SDMMC - Multi Media Card Interface
* USB - Universal Serial Bus
* USCI - Universal Serial Interface
*/
#define XMC4_IRQ_SCU (XMC4_IRQ_FIRST+0) /* 0: System Control */
#define XMC4_IRQ_ERU0_SR0 (XMC4_IRQ_FIRST+1) /* 1: ERU0, SR0 */
#define XMC4_IRQ_ERU0_SR1 (XMC4_IRQ_FIRST+2) /* 2: ERU0, SR1 */
#define XMC4_IRQ_ERU0_SR2 (XMC4_IRQ_FIRST+3) /* 3: ERU0, SR2 */
#define XMC4_IRQ_ERU0_SR3 (XMC4_IRQ_FIRST+4) /* 4: ERU0, SR3 */
#define XMC4_IRQ_ERU1_SR0 (XMC4_IRQ_FIRST+5) /* 5: ERU1, SR0 */
#define XMC4_IRQ_ERU1_SR1 (XMC4_IRQ_FIRST+6) /* 6: ERU1, SR1 */
#define XMC4_IRQ_ERU1_SR2 (XMC4_IRQ_FIRST+7) /* 7: ERU1, SR2 */
#define XMC4_IRQ_ERU1_SR3 (XMC4_IRQ_FIRST+8) /* 8: ERU1, SR3 */
#define XMC4_IRQ_RESVD009 (XMC4_IRQ_FIRST+9) /* 9: Reserved */
#define XMC4_IRQ_RESVD010 (XMC4_IRQ_FIRST+10) /* 10: Reserved */
#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+11) /* 11: Reserved */
#define XMC4_IRQ_PMU1_SR0 (XMC4_IRQ_FIRST+12) /* 12: PMU, SR0 */
#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+13) /* 13: Reserved */
#define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */
#define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */
#define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */
#define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */
#define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */
#define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */
#define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */
#define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */
#define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */
#define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */
#define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */
#define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */
#define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */
#define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */
#define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */
#define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */
#define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */
#define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */
#define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */
#define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */
#define XMC4_IRQ_DSD_SRM0 (XMC4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */
#define XMC4_IRQ_DSD_SRM1 (XMC4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */
#define XMC4_IRQ_DSD_SRM2 (XMC4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */
#define XMC4_IRQ_DSD_SRM3 (XMC4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */
#define XMC4_IRQ_DSD_SRA0 (XMC4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */
#define XMC4_IRQ_DSD_SRA1 (XMC4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */
#define XMC4_IRQ_DSD_SRA2 (XMC4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */
#define XMC4_IRQ_DSD_SRA3 (XMC4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */
#define XMC4_IRQ_DAC_SR0 (XMC4_IRQ_FIRST+42) /* 42: DAC, SR0 */
#define XMC4_IRQ_DAC_SR1 (XMC4_IRQ_FIRST+43) /* 43: DAC, SR1 */
#define XMC4_IRQ_CCU40_SR0 (XMC4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */
#define XMC4_IRQ_CCU40_SR1 (XMC4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */
#define XMC4_IRQ_CCU40_SR2 (XMC4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */
#define XMC4_IRQ_CCU40_SR3 (XMC4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */
#define XMC4_IRQ_CCU41_SR0 (XMC4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */
#define XMC4_IRQ_CCU41_SR1 (XMC4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */
#define XMC4_IRQ_CCU41_SR2 (XMC4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */
#define XMC4_IRQ_CCU41_SR3 (XMC4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */
#define XMC4_IRQ_CCU42_SR0 (XMC4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */
#define XMC4_IRQ_CCU42_SR1 (XMC4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */
#define XMC4_IRQ_CCU42_SR2 (XMC4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */
#define XMC4_IRQ_CCU42_SR3 (XMC4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */
#define XMC4_IRQ_CCU43_SR0 (XMC4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */
#define XMC4_IRQ_CCU43_SR1 (XMC4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */
#define XMC4_IRQ_CCU43_SR2 (XMC4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */
#define XMC4_IRQ_CCU43_SR3 (XMC4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */
#define XMC4_IRQ_CCU80_SR0 (XMC4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */
#define XMC4_IRQ_CCU80_SR1 (XMC4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */
#define XMC4_IRQ_CCU80_SR2 (XMC4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */
#define XMC4_IRQ_CCU80_SR3 (XMC4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */
#define XMC4_IRQ_CCU81_SR0 (XMC4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */
#define XMC4_IRQ_CCU81_SR1 (XMC4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */
#define XMC4_IRQ_CCU81_SR2 (XMC4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */
#define XMC4_IRQ_CCU81_SR3 (XMC4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */
#define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */
#define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */
#define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */
#define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */
#define XMC4_IRQ_RESVD072 (XMC4_IRQ_FIRST+72) /* 72: Reserved */
#define XMC4_IRQ_RESVD073 (XMC4_IRQ_FIRST+73) /* 73: Reserved */
#define XMC4_IRQ_RESVD074 (XMC4_IRQ_FIRST+74) /* 74: Reserved */
#define XMC4_IRQ_RESVD075 (XMC4_IRQ_FIRST+75) /* 75: Reserved */
#define XMC4_IRQ_CAN_SR0 (XMC4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */
#define XMC4_IRQ_CAN_SR1 (XMC4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */
#define XMC4_IRQ_CAN_SR2 (XMC4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */
#define XMC4_IRQ_CAN_SR3 (XMC4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */
#define XMC4_IRQ_CAN_SR4 (XMC4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */
#define XMC4_IRQ_CAN_SR5 (XMC4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */
#define XMC4_IRQ_CAN_SR6 (XMC4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */
#define XMC4_IRQ_CAN_SR7 (XMC4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */
#define XMC4_IRQ_USIC0_SR0 (XMC4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */
#define XMC4_IRQ_USIC0_SR1 (XMC4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */
#define XMC4_IRQ_USIC0_SR2 (XMC4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */
#define XMC4_IRQ_USIC0_SR3 (XMC4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */
#define XMC4_IRQ_USIC0_SR4 (XMC4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */
#define XMC4_IRQ_USIC0_SR5 (XMC4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */
#define XMC4_IRQ_USIC1_SR0 (XMC4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */
#define XMC4_IRQ_USIC1_SR1 (XMC4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */
#define XMC4_IRQ_USIC1_SR2 (XMC4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */
#define XMC4_IRQ_USIC1_SR3 (XMC4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */
#define XMC4_IRQ_USIC1_SR4 (XMC4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */
#define XMC4_IRQ_USIC1_SR5 (XMC4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */
#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */
#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */
#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */
#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */
#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */
#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */
#define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */
#define XMC4_IRQ_RESVD103 (XMC4_IRQ_FIRST+103) /* 103: Reserved */
#define XMC4_IRQ_FCR_SR0 (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */
#define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */
#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */
#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */
#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */
#define XMC4_IRQ_RESVD109 (XMC4_IRQ_FIRST+109) /* 109: Reserved */
#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */
#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST+111) /* 111: Reserved */
#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/
#define NR_VECTORS (XMC4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */
/* GPIO IRQ interrupts -- To be provided */
#define NR_IRQS NR_VECTORS
/*****************************************************************************
* Public Types
****************************************************************************/
/*****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/*****************************************************************************
* Public Functions
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H */

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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "XMC4xxx Configuration Options"
choice
prompt "XMC4xxx Chip Selection"
default ARCH_CHIP_XMC4500
depends on ARCH_CHIP_XMC4
config ARCH_CHIP_XMC4500
bool "XMC4500"
endchoice
# These "hidden" settings determine is a peripheral option is available for
# the selection MCU
# When there are multiple instances of a device, these "hidden" settings
# will automatically be selected and will represent the 'OR' of the
# instances selected.
config XMC4_USIC
bool
default n
config XMC4_USCI_UART
bool
default n
select MCU_SERIAL
config XMC4_USCI_LIN
bool
default n
config XMC4_USCI_SPI
bool
default n
config XMC4_USCI_I2C
bool
default n
config XMC4_USCI_I2S
bool
default n
# Chip families
menu "XMC4xxx Peripheral Support"
config XMC4_USIC0
bool "USIC0"
default n
select XMC4_USIC
---help---
Support USIC0
config XMC4_USIC1
bool "USIC1"
default n
---help---
Support USIC1
config XMC4_USIC2
bool "USIC3"
default n
select XMC4_USIC
---help---
Support USIC2
config XMC4_USIC3
bool "USIC3"
default n
select XMC4_USIC
---help---
Support USIC3
config XMC4_USIC4
bool "USIC4"
default n
select XMC4_USIC
---help---
Support USIC4
config XMC4_USIC5
bool "USIC5"
default n
select XMC4_USIC
---help---
Support USIC5
endmenu
menu "XMC4xxx USIC Configuration"
depends on XMC4_USIC
choice
prompt "USIC0 Configuration"
default XMC4_USIC0_ISUART
depends on XMC4_USIC0
config XMC4_USIC0_ISUART
bool "UART"
select UART0_SERIALDRIVER
select XMC4_USCI_UART
---help---
Configure USIC0 as a UART
config XMC4_USIC0_ISLIN
bool "LIN"
select XMC4_USCI_LIN
---help---
Configure USIC0 as a LIN UART
config XMC4_USIC0_ISSPI
bool "SPI"
select XMC4_USCI_SPI
---help---
Configure USIC0 For SPI communications
config XMC4_USIC0_ISI2C
bool "I2C"
select XMC4_USCI_I2C
---help---
Configure USIC0 For I2C communications
config XMC4_USIC0_ISI2S
bool "I2S"
select XMC4_USCI_I2S
---help---
Configure USIC0 For I2S audio
endchoice # USIC0 Configuration
choice
prompt "USIC1 Configuration"
default XMC4_USIC1_ISUART
depends on XMC4_USIC1
config XMC4_USIC1_ISUART
bool "UART"
select UART1_SERIALDRIVER
select XMC4_USCI_UART
---help---
Configure USIC1 as a UART
config XMC4_USIC1_ISLIN
bool "LIN"
select XMC4_USCI_LIN
---help---
Configure USIC1 as a LIN UART
config XMC4_USIC1_ISSPI
bool "SPI"
select XMC4_USCI_SPI
---help---
Configure USIC1 For SPI communications
config XMC4_USIC1_ISI2C
bool "I2C"
select XMC4_USCI_I2C
---help---
Configure USIC1 For I2C communications
config XMC4_USIC1_ISI2S
bool "I2S"
select XMC4_USCI_I2S
---help---
Configure USIC1 For I2S audio
endchoice # USIC1 Configuration
choice
prompt "USIC2 Configuration"
default XMC4_USIC2_ISUART
depends on XMC4_USIC2
config XMC4_USIC2_ISUART
bool "UART"
select UART2_SERIALDRIVER
select XMC4_USCI_UART
---help---
Configure USIC2 as a UART
config XMC4_USIC2_ISLIN
bool "LIN"
select XMC4_USCI_LIN
---help---
Configure USIC2 as a LIN UART
config XMC4_USIC2_ISSPI
bool "SPI"
select XMC4_USCI_SPI
---help---
Configure USIC2 For SPI communications
config XMC4_USIC2_ISI2C
bool "I2C"
select XMC4_USCI_I2C
---help---
Configure USIC2 For I2C communications
config XMC4_USIC2_ISI2S
bool "I2S"
select XMC4_USCI_I2S
---help---
Configure USIC2 For I2S audio
endchoice # USIC2 Configuration
choice
prompt "USIC3 Configuration"
default XMC4_USIC3_ISUART
depends on XMC4_USIC3
config XMC4_USIC3_ISUART
bool "UART"
select UART3_SERIALDRIVER
select XMC4_USCI_UART
---help---
Configure USIC3 as a UART
config XMC4_USIC3_ISLIN
bool "LIN"
select XMC4_USCI_LIN
---help---
Configure USIC3 as a LIN UART
config XMC4_USIC3_ISSPI
bool "SPI"
select XMC4_USCI_SPI
---help---
Configure USIC3 For SPI communications
config XMC4_USIC3_ISI2C
bool "I2C"
select XMC4_USCI_I2C
---help---
Configure USIC3 For I2C communications
config XMC4_USIC3_ISI2S
bool "I2S"
select XMC4_USCI_I2S
---help---
Configure USIC3 For I2S audio
endchoice # USIC3 Configuration
choice
prompt "USIC4 Configuration"
default XMC4_USIC4_ISUART
depends on XMC4_USIC4
config XMC4_USIC4_ISUART
bool "UART"
select UART4_SERIALDRIVER
select XMC4_USCI_UART
---help---
Configure USIC4 as a UART
config XMC4_USIC4_ISLIN
bool "LIN"
select XMC4_USCI_LIN
---help---
Configure USIC4 as a LIN UART
config XMC4_USIC4_ISSPI
bool "SPI"
select XMC4_USCI_SPI
---help---
Configure USIC4 For SPI communications
config XMC4_USIC4_ISI2C
bool "I2C"
select XMC4_USCI_I2C
---help---
Configure USIC4 For I2C communications
config XMC4_USIC4_ISI2S
bool "I2S"
select XMC4_USCI_I2S
---help---
Configure USIC4 For I2S audio
endchoice # USIC4 Configuration
choice
prompt "USIC5 Configuration"
default XMC4_USIC5_ISUART
depends on XMC4_USIC5
config XMC4_USIC5_ISUART
bool "UART"
select UART0_SERIALDRIVER
select XMC4_USCI_UART
---help---
Configure USIC5 as a UART
config XMC4_USIC5_ISLIN
bool "LIN"
select XMC4_USCI_LIN
---help---
Configure USIC5 as a LIN UART
config XMC4_USIC5_ISSPI
bool "SPI"
select XMC4_USCI_SPI
---help---
Configure USIC5 For SPI communications
config XMC4_USIC5_ISI2C
bool "I2C"
select XMC4_USCI_I2C
---help---
Configure USIC5 For I2C communications
config XMC4_USIC5_ISI2S
bool "I2S"
select XMC4_USCI_I2S
---help---
Configure USIC5 For I2S audio
endchoice # USIC5 Configuration
endmenu # XMC4xxx USIC Configuration

141
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############################################################################
# arch/arm/src/kinetis/Make.defs
#
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
HEAD_ASRC =
else
HEAD_ASRC = xmc4_vectors.S
endif
CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_ASRCS += up_testset.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_modifyreg8.c
CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasestack.c
CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_releasepending.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c
CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c
CMN_CSRCS += up_systemreset.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += up_stackcheck.c
endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S
else
CMN_ASRCS += up_exception.S
endif
CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y)
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif
# Use of common/up_etherstub.c is deprecated. The preferred mechanism is to
# use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in
# up_initialize(). Then this stub would not be needed.
ifeq ($(CONFIG_NET),y)
ifneq ($(CONFIG_XMC4_ENET),y)
CMN_CSRCS += up_etherstub.c
endif
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += up_itm_syslog.c
endif
# Required XMC4xxx files
CHIP_ASRCS =
CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clockutils.c
CHIP_CSRCS += xmc4_clrpend.c xmc4_idle.c xmc4_irq.c xmc4_lowputc.c
CHIP_CSRCS += xmc4_gpio.c xmc4_serial.c xmc4_start.c
# Configuration-dependent Kinetis files
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += xmc4_timerisr.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += xmc4_userspace.c xmc4_mpuinit.c
endif
ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
CHIP_CSRCS += xmc4_pindump.c
endif
ifeq ($(CONFIG_XMC4_DMA),y)
CHIP_CSRCS += xmc4_dma.c
endif
ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += xmc4_pwm.c
endif
ifeq ($(CONFIG_I2C),y)
CHIP_CSRCS += xmc4_i2c.c
endif

77
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/************************************************************************************
* arch/arm/src/xmc4/chip.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_CHIP_H
#define __ARCH_ARM_SRC_XMC4_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware files
* should then include this file for the proper setup.
*/
#include <arch/irq.h>
#include <arch/xmc4/chip.h>
#include "chip/xmc4_memorymap.h"
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported external
* interrupts which, for this architecture, is provided in the arch/xmc4/chip.h
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_XMC4_CHIP_H */

205
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/************************************************************************************
* arch/arm/src/xmc4/chip/xmc4_flash.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H
#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/xmc4_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
/* PMU Registers -- See ID register */
/* Prefetch Registers -- See PCON register */
/* FLASH Registers */
#define XMC4_FLASH_ID_OFFSET 0x1008 /* Flash Module Identification Register */
#define XMC4_FLASH_FSR_OFFSET 0x1010 /* Flash Status Register */
#define XMC4_FLASH_FCON_OFFSET 0x1014 /* Flash Configuration Register */
#define XMC4_FLASH_MARP_OFFSET 0x1018 /* Flash Margin Control Register PFLASH */
#define XMC4_FLASH_PROCON0_OFFSET 0x1020 /* Flash Protection Configuration User 0 */
#define XMC4_FLASH_PROCON1_OFFSET 0x1024 /* Flash Protection Configuration User 1 */
#define XMC4_FLASH_PROCON2_OFFSET 0x1028 /* Flash Protection Configuration User 2 */
/* Register Addresses ****************************************************************/
/* FLASH Registers */
#define XMC4_FLASH_ID (XMC4_FLASH0_BASE+XMC4_FLASH_ID_OFFSET)
#define XMC4_FLASH_FSR (XMC4_FLASH0_BASE+XMC4_FLASH_FSR_OFFSET)
#define XMC4_FLASH_FCON (XMC4_FLASH0_BASE+XMC4_FLASH_FCON_OFFSET)
#define XMC4_FLASH_MARP (XMC4_FLASH0_BASE+XMC4_FLASH_MARP_OFFSET)
#define XMC4_FLASH_PROCON0 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON0_OFFSET)
#define XMC4_FLASH_PROCON1 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON1_OFFSET)
#define XMC4_FLASH_PROCON2 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON2_OFFSET)
/* Register Bit-Field Definitions **************************************************/
/* FLASH Registers */
/* Flash Module Identification Register */
#define FLASH_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */
#define FLASH_ID_MOD_REV_MASK (0xff << FLASH_ID_MOD_REV_SHIFT)
#define FLASH_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */
#define FLASH_ID_MOD_TYPE_MASK (0xff << FLASH_ID_MOD_REV_SHIFT)
#define FLASH_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */
#define FLASH_ID_MOD_NUMBER_MASK (0xffff << FLASH_ID_MOD_NUMBER_SHIFT)
/* Flash Status Register */
#define FLASH_FSR_PBUSY (1 << 0) /* Bit 0: Program Flash Busy */
#define FLASH_FSR_FABUSY (1 << 1) /* Bit 1: Flash Array Busy */
#define FLASH_FSR_PROG (1 << 4) /* Bit 4: Programming State */
#define FLASH_FSR_ERASE (1 << 5) /* Bit 5: Erase State */
#define FLASH_FSR_PFPAGE (1 << 6) /* Bit 6: Program Flash in Page Mode */
#define FLASH_FSR_PFOPER (1 << 8) /* Bit 8: Program Flash Operation Error */
#define FLASH_FSR_SQER (1 << 10) /* Bit 10: Command Sequence Error */
#define FLASH_FSR_PROER (1 << 11) /* Bit 11: Protection Error */
#define FLASH_FSR_PFSBER (1 << 12) /* Bit 12: PFLASH Single-Bit Error and Correction */
#define FLASH_FSR_PFDBER (1 << 14) /* Bit 14: PFLASH Double-Bit Error */
#define FLASH_FSR_PROIN (1 << 16) /* Bit 16: Protection Installed */
#define FLASH_FSR_RPROIN (1 << 18) /* Bit 18: Read Protection Installed */
#define FLASH_FSR_RPRODIS (1 << 19) /* Bit 19: Read Protection Disable State */
#define FLASH_FSR_WPROIN0 (1 << 21) /* Bit 21: Sector Write Protection Installed for User 0 */
#define FLASH_FSR_WPROIN1 (1 << 22) /* Bit 22: Sector Write Protection Installed for User 1 */
#define FLASH_FSR_WPROIN2 (1 << 23) /* Bit 23: Sector Write Protection Installed for User 2 */
#define FLASH_FSR_WPRODIS0 (1 << 25) /* Bit 25: Sector Write Protection Disabled for User 0 */
#define FLASH_FSR_WPRODIS1 (1 << 26) /* Bit 26: Sector Write Protection Disabled for User 1 */
#define FLASH_FSR_SLM (1 << 28) /* Bit 28: Flash Sleep Mode */
#define FLASH_FSR_VER (1 << 31) /* Bit 31: Verify Error */
/* Flash Configuration Register */
#define FLASH_FCON_WSPFLASH_SHIFT (0) /* Bits 0-3: Wait States for read access to PFLASH */
#define FLASH_FCON_WSPFLASH_MASK (15 << FLASH_FCON_WSPFLASH_SHIFT)
# define FLASH_FCON_WSPFLASH(n) ((uint32_t)((n)-1) << FLASH_FCON_WSPFLASH_SHIFT)
#define FLASH_FCON_WSECPF (1 << 4) /* Bit 4: Wait State for Error Correction of PFLASH */
#define FLASH_FCON_IDLE (1 << 13) /* Bit 13: Dynamic Flash Idle */
#define FLASH_FCON_ESLDIS (1 << 14) /* Bit 14: External Sleep Request Disable */
#define FLASH_FCON_SLEEP (1 << 15) /* Bit 15: Flash SLEEP */
#define FLASH_FCON_RPA (1 << 16) /* Bit 16: Read Protection Activated */
#define FLASH_FCON_DCF (1 << 17) /* Bit 17: Disable Code Fetch from Flash Memory */
#define FLASH_FCON_DDF (1 << 18) /* Bit 18: Disable Any Data Fetch from Flash */
#define FLASH_FCON_VOPERM (1 << 24) /* Bit 24: Verify and Operation Error Interrupt Mask */
#define FLASH_FCON_SQERM (1 << 25) /* Bit 25: Command Sequence Error Interrupt Mask */
#define FLASH_FCON_PROERM (1 << 26) /* Bit 26: Protection Error Interrupt Mask */
#define FLASH_FCON_PFSBERM (1 << 27) /* Bit 27: PFLASH Single-Bit Error Interrupt Mask */
#define FLASH_FCON_PFDBERM (1 << 29) /* Bit 29: PFLASH Double-Bit Error Interrupt Mask */
#define FLASH_FCON_EOBM (1 << 31) /* Bit 31: End of Busy Interrupt Mask */
/* Flash Margin Control Register PFLASH */
#define FLASH_MARP_MARGIN_SHIFT (0) /* Bits 0-3: PFLASH Margin Selection */
#define FLASH_MARP_MARGIN_MASK (15 << FLASH_MARP_MARGIN_SHIFT)
#define FLASH_MARP_TRAPDIS (1 << 15) /* Bit 15: PFLASH Double-Bit Error Trap Disable */
/* Flash Protection Configuration User 0 */
#define FLASH_PROCON0_S0L (1 << 0) /* Bit 0: Sector 0 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S1L (1 << 1) /* Bit 1: Sector 1 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S2L (1 << 2) /* Bit 2: Sector 2 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S3L (1 << 3) /* Bit 3: Sector 3 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S4L (1 << 4) /* Bit 4: Sector 4 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S5L (1 << 5) /* Bit 5: Sector 5 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S6L (1 << 6) /* Bit 6: Sector 6 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S7L (1 << 7) /* Bit 7: Sector 7 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S8L (1 << 8) /* Bit 8: Sector 8 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S9L (1 << 9) /* Bit 9: Sector 9 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S10_S11L (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S12_S13L (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_S14_S15L (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 0 */
#define FLASH_PROCON0_RPRO (1 << 15) /* Bit 15: Read Protection Configuration */
/* Flash Protection Configuration User 1 */
#define FLASH_PROCON1_S0L (1 << 0) /* Bit 0: Sector 0 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S1L (1 << 1) /* Bit 1: Sector 1 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S2L (1 << 2) /* Bit 2: Sector 2 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S3L (1 << 3) /* Bit 3: Sector 3 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S4L (1 << 4) /* Bit 4: Sector 4 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S5L (1 << 5) /* Bit 5: Sector 5 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S6L (1 << 6) /* Bit 6: Sector 6 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S7L (1 << 7) /* Bit 7: Sector 7 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S8L (1 << 8) /* Bit 8: Sector 8 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S9L (1 << 9) /* Bit 9: Sector 9 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S10_S11L (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S12_S13L (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_S14_S15L (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 1 */
#define FLASH_PROCON1_PSR (1 << 16) /* Bit 16: */
/* Flash Protection Configuration User 2 */
#define FLASH_PROCON2_S0ROM (1 << 0) /* Bit 0: Sector 0 Locked Forever by User 2 */
#define FLASH_PROCON2_S1ROM (1 << 1) /* Bit 1: Sector 1 Locked Forever by User 2 */
#define FLASH_PROCON2_S2ROM (1 << 2) /* Bit 2: Sector 2 Locked Forever by User 2 */
#define FLASH_PROCON2_S3ROM (1 << 3) /* Bit 3: Sector 3 Locked Forever by User 2 */
#define FLASH_PROCON2_S4ROM (1 << 4) /* Bit 4: Sector 4 Locked Forever by User 2 */
#define FLASH_PROCON2_S5ROM (1 << 5) /* Bit 5: Sector 5 Locked Forever by User 2 */
#define FLASH_PROCON2_S6ROM (1 << 6) /* Bit 6: Sector 6 Locked Forever by User 2 */
#define FLASH_PROCON2_S7ROM (1 << 7) /* Bit 7: Sector 7 Locked Forever by User 2 */
#define FLASH_PROCON2_S8ROM (1 << 8) /* Bit 8: Sector 8 Locked Forever by User 2 */
#define FLASH_PROCON2_S9ROM (1 << 9) /* Bit 9: Sector 9 Locked Forever by User 2 */
#define FLASH_PROCON2_S10_S11ROM (1 << 10) /* Bit 10: Sectors 10 and 11 Locked Forever by User 2 */
#define FLASH_PROCON2_S12_S13ROM (1 << 11) /* Bit 11: Sectors 12 and 13 Locked Forever by User 2 */
#define FLASH_PROCON2_S14_S15ROM (1 << 12) /* Bit 12: Sectors 14 and 15 Locked Forever by User 2 */
#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H */

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/************************************************************************************
* arch/arm/src/xmc4/chip/xmc4_memorymap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H
#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Peripheral Memory Map ************************************************************/
/* Acronyms:
* ADC - Analog to Digital Converter
* CCU - Capture Compare Unit
* DAC - Digital to Analog Converter
* DSD - Delta Sigmoid Demodulator
* ERU - External Request Unit
* FCE - Flexible CRC Engine
* GPDMA - General Purpose DMA
* LEDTS - LED and Touch Sense Control Unit
* PMU - Program Management Unit
* POSIF - Position Interface
* SDMMC - Multi Media Card Interface
* USB - Universal Serial Bus
* USCI - Universal Serial Interface
*/
#define XMC4_PBA0_BASE 0x40000000
#define XMC4_VADC_BASE 0x40004000
#define XMC4_VADC_G0_BASE 0x40004400
#define XMC4_VADC_G1_BASE 0x40004800
#define XMC4_VADC_G2_BASE 0x40004c00
#define XMC4_VADC_G3_BASE 0x40005000
#define XMC4_DSD_BASE 0x40008000
#define XMC4_DSD_CH0_BASE 0x40008100
#define XMC4_DSD_CH1_BASE 0x40008200
#define XMC4_DSD_CH2_BASE 0x40008300
#define XMC4_DSD_CH3_BASE 0x40008400
#define XMC4_CCU40_BASE 0x4000c000
#define XMC4_CCU40_CC40_BASE 0x4000c100
#define XMC4_CCU40_CC41_BASE 0x4000c200
#define XMC4_CCU40_CC42_BASE 0x4000c300
#define XMC4_CCU40_CC43_BASE 0x4000c400
#define XMC4_CCU41_BASE 0x40010000
#define XMC4_CCU41_CC40_BASE 0x40010100
#define XMC4_CCU41_CC41_BASE 0x40010200
#define XMC4_CCU41_CC42_BASE 0x40010300
#define XMC4_CCU41_CC43_BASE 0x40010400
#define XMC4_CCU42_BASE 0x40014000
#define XMC4_CCU42_CC40_BASE 0x40014100
#define XMC4_CCU42_CC41_BASE 0x40014200
#define XMC4_CCU42_CC42_BASE 0x40014300
#define XMC4_CCU42_CC43_BASE 0x40014400
#define XMC4_CCU80_BASE 0x40020000
#define XMC4_CCU80_CC80_BASE 0x40020100
#define XMC4_CCU80_CC81_BASE 0x40020200
#define XMC4_CCU80_CC82_BASE 0x40020300
#define XMC4_CCU80_CC83_BASE 0x40020400
#define XMC4_CCU81_BASE 0x40024000
#define XMC4_CCU81_CC80_BASE 0x40024100
#define XMC4_CCU81_CC81_BASE 0x40024200
#define XMC4_CCU81_CC82_BASE 0x40024300
#define XMC4_CCU81_CC83_BASE 0x40024400
#define XMC4_POSIF0_BASE 0x40028000
#define XMC4_POSIF1_BASE 0x4002c000
#define XMC4_USIC0_BASE 0x40030000
#define XMC4_USIC0_CH0_BASE 0x40030000
#define XMC4_USIC0_CH1_BASE 0x40030200
#define XMC4_USIC0_RAM_BASE 0x40030400
#define XMC4_ERU1_BASE 0x40044000
#define XMC4_PBA1_BASE 0x48000000
#define XMC4_CCU43_BASE 0x48004000
#define XMC4_CCU43_CC40_BASE 0x48004100
#define XMC4_CCU43_CC41_BASE 0x48004200
#define XMC4_CCU43_CC42_BASE 0x48004300
#define XMC4_CCU43_CC43_BASE 0x48004400
#define XMC4_LEDTS0_BASE 0x48010000
#define XMC4_CAN_BASE 0x48014000
#define XMC4_CAN_NODE0_BASE 0x48014200
#define XMC4_CAN_NODE1_BASE 0x48014300
#define XMC4_CAN_NODE2_BASE 0x48014400
#define XMC4_CAN_NODE3_BASE 0x48014500
#define XMC4_CAN_NODE4_BASE 0x48014600
#define XMC4_CAN_NODE5_BASE 0x48014700
#define XMC4_CAN_MO_BASE 0x48015000
#define XMC4_DAC_BASE 0x48018000
#define XMC4_SDMMC_BASE 0x4801c000
#define XMC4_USIC1_BASE 0x48020000
#define XMC4_USIC1_CH0_BASE 0x48020000
#define XMC4_USIC1_CH1_BASE 0x48020200
#define XMC4_USIC1_RAM_BASE 0x48020400
#define XMC4_USIC2_BASE 0x48024000
#define XMC4_USIC2_CH0_BASE 0x48024000
#define XMC4_USIC2_CH1_BASE 0x48024200
#define XMC4_USIC2_RAM_BASE 0x48024400
#define XMC4_PORT_BASE(n) (0x48028000 + ((n) << 8))
#define XMC4_PORT0_BASE 0x48028000
#define XMC4_PORT1_BASE 0x48028100
#define XMC4_PORT2_BASE 0x48028200
#define XMC4_PORT3_BASE 0x48028300
#define XMC4_PORT4_BASE 0x48028400
#define XMC4_PORT5_BASE 0x48028500
#define XMC4_PORT6_BASE 0x48028600
#define XMC4_PORT7_BASE 0x48028700
#define XMC4_PORT8_BASE 0x48028800
#define XMC4_PORT9_BASE 0x48028900
#define XMC4_PORT14_BASE 0x48028e00
#define XMC4_PORT15_BASE 0x48028f00
#define XMC4_SCU_GENERAL_BASE 0x50004000
#define XMC4_ETH0_CON_BASE 0x50004040
#define XMC4_SCU_INTERRUPT_BASE 0x50004074
#define XMC4_SDMMC_CON_BASE 0x500040b4
#define XMC4_SCU_PARITY_BASE 0x5000413c
#define XMC4_SCU_TRAP_BASE 0x50004160
#define XMC4_SCU_POWER_BASE 0x50004200
#define XMC4_SCU_HIBERNATE_BASE 0x50004300
#define XMC4_SCU_RESET_BASE 0x50004400
#define XMC4_SCU_CLK_BASE 0x50004600
#define XMC4_SCU_OSC_BASE 0x50004700
#define XMC4_SCU_PLL_BASE 0x50004710
#define XMC4_ERU0_BASE 0x50004800
#define XMC4_DLR_BASE 0x50004900
#define XMC4_RTC_BASE 0x50004a00
#define XMC4_WDT_BASE 0x50008000
#define XMC4_ETH0_BASE 0x5000c000
#define XMC4_USB0_BASE 0x50040000
#define XMC4_USB0_CH0_BASE 0x50040500
#define XMC4_USB0_CH1_BASE 0x50040520
#define XMC4_USB0_CH2_BASE 0x50040540
#define XMC4_USB0_CH3_BASE 0x50040560
#define XMC4_USB0_CH4_BASE 0x50040580
#define XMC4_USB0_CH5_BASE 0x500405a0
#define XMC4_USB0_CH6_BASE 0x500405c0
#define XMC4_USB0_CH7_BASE 0x500405e0
#define XMC4_USB0_CH8_BASE 0x50040600
#define XMC4_USB0_CH9_BASE 0x50040620
#define XMC4_USB0_CH10_BASE 0x50040640
#define XMC4_USB0_CH11_BASE 0x50040660
#define XMC4_USB0_CH12_BASE 0x50040680
#define XMC4_USB0_CH13_BASE 0x500406a0
#define XMC4_USB_EP_BASE 0x50040900
#define XMC4_USB0_EP1_BASE 0x50040920
#define XMC4_USB0_EP2_BASE 0x50040940
#define XMC4_USB0_EP3_BASE 0x50040960
#define XMC4_USB0_EP4_BASE 0x50040980
#define XMC4_USB0_EP5_BASE 0x500409a0
#define XMC4_USB0_EP6_BASE 0x500409c0
#define XMC4_GPDMA0_CH0_BASE 0x50014000
#define XMC4_GPDMA0_CH1_BASE 0x50014058
#define XMC4_GPDMA0_CH2_BASE 0x500140b0
#define XMC4_GPDMA0_CH3_BASE 0x50014108
#define XMC4_GPDMA0_CH4_BASE 0x50014160
#define XMC4_GPDMA0_CH5_BASE 0x500141b8
#define XMC4_GPDMA0_CH6_BASE 0x50014210
#define XMC4_GPDMA0_CH7_BASE 0x50014268
#define XMC4_GPDMA0_BASE 0x500142c0
#define XMC4_GPDMA1_CH0_BASE 0x50018000
#define XMC4_GPDMA1_CH1_BASE 0x50018058
#define XMC4_GPDMA1_CH2_BASE 0x500180b0
#define XMC4_GPDMA1_CH3_BASE 0x50018108
#define XMC4_GPDMA1_BASE 0x500182c0
#define XMC4_FCE_BASE 0x50020000
#define XMC4_FCE_KE0_BASE 0x50020020
#define XMC4_FCE_KE1_BASE 0x50020040
#define XMC4_FCE_KE2_BASE 0x50020060
#define XMC4_FCE_KE3_BASE 0x50020080
#define XMC4_PMU0_BASE 0x58000500
#define XMC4_FLASH0_BASE 0x58001000
#define XMC4_PREF_BASE 0x58004000
#define XMC4_EBU_BASE 0x58008000
#define XMC4_PPB_BASE 0xe000e000
#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H */

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/************************************************************************************
* arch/arm/src/xmc4/chip/xmc4_pinmux.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMUX_H
#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMUX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMXU_H */

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/************************************************************************************
* arch/arm/src/xmc4/chip/xmc4_ports.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H
#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/xmc4_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
/* PORTS Registers */
#define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */
#define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */
#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & 3))
#define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */
#define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */
#define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */
#define XMC4_PORT_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */
#define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */
#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & 3))
#define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */
#define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */
#define XMC4_PORT_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */
#define XMC4_PORT_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */
#define XMC4_PORT_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */
/* Register Addresses ****************************************************************/
#define XMC4_PORT0_OUT (XMC4_PORT0_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT0_OMR (XMC4_PORT0_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT0_IOCR0 (XMC4_PORT0_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT0_IOCR4 (XMC4_PORT0_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT0_IOCR8 (XMC4_PORT0_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT0_IOCR12 (XMC4_PORT0_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT0_IN (XMC4_PORT0_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT0_PDR0 (XMC4_PORT0_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT0_PDR1 (XMC4_PORT0_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT0_PDISC (XMC4_PORT0_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT0_PPS (XMC4_PORT0_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT0_HWSEL (XMC4_PORT0_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT1_OUT (XMC4_PORT1_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT1_OMR (XMC4_PORT1_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT1_IOCR0 (XMC4_PORT1_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT1_IOCR4 (XMC4_PORT1_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT1_IOCR8 (XMC4_PORT1_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT1_IOCR12 (XMC4_PORT1_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT1_IN (XMC4_PORT1_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT1_PDR0 (XMC4_PORT1_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT1_PDR1 (XMC4_PORT1_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT1_PDISC (XMC4_PORT1_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT1_PPS (XMC4_PORT1_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT1_HWSEL (XMC4_PORT1_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT2_OUT (XMC4_PORT2_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT2_OMR (XMC4_PORT2_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT2_IOCR0 (XMC4_PORT2_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT2_IOCR4 (XMC4_PORT2_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT2_IOCR8 (XMC4_PORT2_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT2_IOCR12 (XMC4_PORT2_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT2_IN (XMC4_PORT2_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT2_PDR0 (XMC4_PORT2_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT2_PDR1 (XMC4_PORT2_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT2_PDISC (XMC4_PORT2_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT2_PPS (XMC4_PORT2_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT2_HWSEL (XMC4_PORT2_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT3_OUT (XMC4_PORT3_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT3_OMR (XMC4_PORT3_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT3_IOCR0 (XMC4_PORT3_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT3_IOCR4 (XMC4_PORT3_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT3_IOCR8 (XMC4_PORT3_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT3_IOCR12 (XMC4_PORT3_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT3_IN (XMC4_PORT3_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT3_PDR0 (XMC4_PORT3_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT3_PDR1 (XMC4_PORT3_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT3_PDISC (XMC4_PORT3_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT3_PPS (XMC4_PORT3_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT3_HWSEL (XMC4_PORT3_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT4_OUT (XMC4_PORT4_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT4_OMR (XMC4_PORT4_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT4_IOCR0 (XMC4_PORT4_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT4_IOCR4 (XMC4_PORT4_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT4_IOCR8 (XMC4_PORT4_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT4_IOCR12 (XMC4_PORT4_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT4_IN (XMC4_PORT4_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT4_PDR0 (XMC4_PORT4_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT4_PDR1 (XMC4_PORT4_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT4_PDISC (XMC4_PORT4_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT4_PPS (XMC4_PORT4_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT4_HWSEL (XMC4_PORT4_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT5_OUT (XMC4_PORT5_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT5_OMR (XMC4_PORT5_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT5_IOCR0 (XMC4_PORT5_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT5_IOCR4 (XMC4_PORT5_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT5_IOCR8 (XMC4_PORT5_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT5_IOCR12 (XMC4_PORT5_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT5_IN (XMC4_PORT5_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT5_PDR0 (XMC4_PORT5_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT5_PDR1 (XMC4_PORT5_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT5_PDISC (XMC4_PORT5_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT5_PPS (XMC4_PORT5_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT5_HWSEL (XMC4_PORT5_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT6_OUT (XMC4_PORT6_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT6_OMR (XMC4_PORT6_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT6_IOCR0 (XMC4_PORT6_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT6_IOCR4 (XMC4_PORT6_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT6_IOCR8 (XMC4_PORT6_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT6_IOCR12 (XMC4_PORT6_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT6_IN (XMC4_PORT6_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT6_PDR0 (XMC4_PORT6_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT6_PDR1 (XMC4_PORT6_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT6_PDISC (XMC4_PORT6_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT6_PPS (XMC4_PORT6_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT6_HWSEL (XMC4_PORT6_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT7_OUT (XMC4_PORT7_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT7_OMR (XMC4_PORT7_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT7_IOCR0 (XMC4_PORT7_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT7_IOCR4 (XMC4_PORT7_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT7_IOCR8 (XMC4_PORT7_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT7_IOCR12 (XMC4_PORT7_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT7_IN (XMC4_PORT7_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT7_PDR0 (XMC4_PORT7_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT7_PDR1 (XMC4_PORT7_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT7_PDISC (XMC4_PORT7_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT7_PPS (XMC4_PORT7_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT7_HWSEL (XMC4_PORT7_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT8_OUT (XMC4_PORT8_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT8_OMR (XMC4_PORT8_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT8_IOCR0 (XMC4_PORT8_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT8_IOCR4 (XMC4_PORT8_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT8_IOCR8 (XMC4_PORT8_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT8_IOCR12 (XMC4_PORT8_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT8_IN (XMC4_PORT8_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT8_PDR0 (XMC4_PORT8_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT8_PDR1 (XMC4_PORT8_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT8_PDISC (XMC4_PORT8_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT8_PPS (XMC4_PORT8_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT8_HWSEL (XMC4_PORT8_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT9_OUT (XMC4_PORT9_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT9_OMR (XMC4_PORT9_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT9_IOCR0 (XMC4_PORT9_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT9_IOCR4 (XMC4_PORT9_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT9_IOCR8 (XMC4_PORT9_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT9_IOCR12 (XMC4_PORT9_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT9_IN (XMC4_PORT9_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT9_PDR0 (XMC4_PORT9_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT9_PDR1 (XMC4_PORT9_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT9_PDISC (XMC4_PORT9_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT9_PPS (XMC4_PORT9_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT9_HWSEL (XMC4_PORT9_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT14_OUT (XMC4_PORT14_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT14_OMR (XMC4_PORT14_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT14_IOCR0 (XMC4_PORT14_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT14_IOCR4 (XMC4_PORT14_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT14_IOCR8 (XMC4_PORT14_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT14_IOCR12 (XMC4_PORT14_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT14_IN (XMC4_PORT14_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT14_PDR0 (XMC4_PORT14_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT14_PDR1 (XMC4_PORT14_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT14_PDISC (XMC4_PORT14_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT14_PPS (XMC4_PORT14_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT14_HWSEL (XMC4_PORT14_BASE+XMC4_PORT_HWSEL_OFFSET)
#define XMC4_PORT15_OUT (XMC4_PORT15_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT15_OMR (XMC4_PORT15_BASE+XMC4_PORT_OMR_OFFSET)
#define XMC4_PORT15_IOCR0 (XMC4_PORT15_BASE+XMC4_PORT_IOCR0_OFFSET)
#define XMC4_PORT15_IOCR4 (XMC4_PORT15_BASE+XMC4_PORT_IOCR4_OFFSET)
#define XMC4_PORT15_IOCR8 (XMC4_PORT15_BASE+XMC4_PORT_IOCR8_OFFSET)
#define XMC4_PORT15_IOCR12 (XMC4_PORT15_BASE+XMC4_PORT_IOCR12_OFFSET)
#define XMC4_PORT15_IN (XMC4_PORT15_BASE+XMC4_PORT_IN_OFFSET)
#define XMC4_PORT15_PDR0 (XMC4_PORT15_BASE+XMC4_PORT_PDR0_OFFSET)
#define XMC4_PORT15_PDR1 (XMC4_PORT15_BASE+XMC4_PORT_PDR1_OFFSET)
#define XMC4_PORT15_PDISC (XMC4_PORT15_BASE+XMC4_PORT_PDISC_OFFSET)
#define XMC4_PORT15_PPS (XMC4_PORT15_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT15_HWSEL (XMC4_PORT15_BASE+XMC4_PORT_HWSEL_OFFSET)
/* Register Bit-Field Definitions **************************************************/
/* Port Output Register, , Port Input Register, Port Pin Function Decision Control
* Register, Port Pin Power Save Register.
*/
#define PORT_PIN(n) (1 << (n))
/* Port Output Modification Register:
*
* PRx PSx Function
* 0 0 Bit Pn_OUT.Px is not changed.
* 0 1 Bit Pn_OUT.Px is set.
* 1 0 Bit Pn_OUT.Px is reset.
* 1 1 Bit Pn_OUT.Px is toggled.
*/
#define OMR_PS(n) (1 << (n))
#define OMR_PR(n) (1 << ((n) + 16))
/* Basic port input/output field values */
/* Direct Input */
#define IOCR_INPUT_NOPULL 0 /* No internal pull device active */
#define IOCR_INPUT_PULLDOWN 1 /* Internal pull-down device active */
#define IOCR_INPUT_PULLUP 2 /* Internal pull-down device active */
#define IOCR_INPUT_CONT 3 /* No internal pull device active; Pn_OUTx
* continuously samples the input value */
/* Any of the above input configurations may be OR'ed with */
/* Inverted Input */
#define IOCR_INPUT_INVERT 4 /* Inverted input modifier */
/* Push-pull Output (direct input) */
#define IOCR_OUTPUT 16 /* General-purpose output */
#define IOCR_OUTPUT_ALT1 17 /* Alternate output function 1 */
#define IOCR_OUTPUT_ALT2 18 /* Alternate output function 2 */
#define IOCR_OUTPUT_ALT3 19 /* Alternate output function 3 */
#define IOCR_OUTPUT_ALT4 20 /* Alternate output function 4 */
/* Any of the above may be OR'ed with */
/* Open drain output */
#define IOCR_OUTPUT_OPENDRAIN 8 /* Output drain output modifier */
/* Port Input/Output Control Register 0 */
#define PORT_IOCR0_PC_SHIFT(p) (((p) << 3) + 3)
#define PORT_IOCR0_PC_MASK(p) (31 << PORT_IOCR0_PC_SHIFT(p))
# define PORT_IOCR0_PC(p,n) ((uint32_t)(n) << PORT_IOCR0_PC_SHIFT(p))
#define PORT_IOCR0_PC0_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 0 */
#define PORT_IOCR0_PC0_MASK (31 << PORT_IOCR0_PC0_SHIFT)
# define PORT_IOCR0_PC0(n) ((uint32_t)(n) << PORT_IOCR0_PC0_SHIFT)
#define PORT_IOCR0_PC1_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 1 */
#define PORT_IOCR0_PC1_MASK (31 << PORT_IOCR0_PC1_SHIFT)
# define PORT_IOCR0_PC1(n) ((uint32_t)(n) << PORT_IOCR0_PC1_SHIFT)
#define PORT_IOCR0_PC2_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 2 */
#define PORT_IOCR0_PC2_MASK (31 << PORT_IOCR0_PC2_SHIFT)
# define PORT_IOCR0_PC2(n) ((uint32_t)(n) << PORT_IOCR0_PC2_SHIFT)
#define PORT_IOCR0_PC3_SHIFT (27) /* Bit 27-31: Port Control for Port 0 Pin 3 */
#define PORT_IOCR0_PC3_MASK (31 << PORT_IOCR0_PC3_SHIFT)
# define PORT_IOCR0_PC3(n) ((uint32_t)(n) << PORT_IOCR0_PC3_SHIFT)
/* Port Input/Output Control Register 4 */
#define PORT_IOCR4_PC_SHIFT(p) ((((p) - 4) << 3) + 3)
#define PORT_IOCR4_PC_MASK(p) (31 << PORT_IOCR4_PC_SHIFT(p))
# define PORT_IOCR4_PC(p,n) ((uint32_t)(n) << PORT_IOCR4_PC_SHIFT(p))
#define PORT_IOCR4_PC4_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 4 */
#define PORT_IOCR4_PC4_MASK (31 << PORT_IOCR4_PC4_SHIFT)
# define PORT_IOCR4_PC4(n) ((uint32_t)(n) << PORT_IOCR4_PC4_SHIFT)
#define PORT_IOCR4_PC5_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 5 */
#define PORT_IOCR4_PC5_MASK (31 << PORT_IOCR4_PC5_SHIFT)
# define PORT_IOCR4_PC5(n) ((uint32_t)(n) << PORT_IOCR4_PC5_SHIFT)
#define PORT_IOCR4_PC6_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 6 */
#define PORT_IOCR4_PC6_MASK (31 << PORT_IOCR4_PC6_SHIFT)
# define PORT_IOCR4_PC6(n) ((uint32_t)(n) << PORT_IOCR4_PC6_SHIFT)
#define PORT_IOCR4_PC7_SHIFT (27) /* Bit 27-31: Port Control for Port 0 Pin 7 */
#define PORT_IOCR4_PC7_MASK (31 << PORT_IOCR4_PC7_SHIFT)
# define PORT_IOCR4_PC7(n) ((uint32_t)(n) << PORT_IOCR4_PC7_SHIFT)
/* Port Input/Output Control Register 8 */
#define PORT_IOCR8_PC_SHIFT(p) ((((p) - 8) << 3) + 3)
#define PORT_IOCR8_PC_MASK(p) (31 << PORT_IOCR8_PC_SHIFT(p))
# define PORT_IOCR8_PC(p,n) ((uint32_t)(n) << PORT_IOCR8_PC_SHIFT(p))
#define PORT_IOCR8_PC8_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 8 */
#define PORT_IOCR8_PC8_MASK (31 << PORT_IOCR8_PC8_SHIFT)
# define PORT_IOCR8_PC8(n) ((uint32_t)(n) << PORT_IOCR8_PC8_SHIFT)
#define PORT_IOCR8_PC9_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 9 */
#define PORT_IOCR8_PC9_MASK (31 << PORT_IOCR8_PC9_SHIFT)
# define PORT_IOCR8_PC9(n) ((uint32_t)(n) << PORT_IOCR8_PC9_SHIFT)
#define PORT_IOCR8_PC10_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 10 */
#define PORT_IOCR8_PC10_MASK (31 << PORT_IOCR8_PC10_SHIFT)
# define PORT_IOCR8_PC10(n) ((uint32_t)(n) << PORT_IOCR8_PC10_SHIFT)
#define PORT_IOCR8_PC11_SHIFT (27) /* Bit 17-31: Port Control for Port 0 Pin 11 */
#define PORT_IOCR8_PC11_MASK (31 << PORT_IOCR8_PC11_SHIFT)
# define PORT_IOCR8_PC11(n) ((uint32_t)(n) << PORT_IOCR8_PC11_SHIFT)
/* Port Input/Output Control Register 12 */
#define PORT_IOCR12_PC_SHIFT(p) ((((p) - 12) << 3) + 3)
#define PORT_IOCR12_PC_MASK(p) (31 << PORT_IOCR12_PC_SHIFT(p))
# define PORT_IOCR12_PC(p,n) ((uint32_t)(n) << PORT_IOCR12_PC_SHIFT(p))
#define PORT_IOCR12_PC12_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 12 */
#define PORT_IOCR12_PC12_MASK (31 << PORT_IOCR12_PC12_SHIFT)
# define PORT_IOCR12_PC12(n) ((uint32_t)(n) << PORT_IOCR12_PC12_SHIFT)
#define PORT_IOCR12_PC13_SHIFT (11) /* Bit 3-7: Port Control for Port n Pin 13 */
#define PORT_IOCR12_PC13_MASK (31 << PORT_IOCR12_PC13_SHIFT)
# define PORT_IOCR12_PC13(n) ((uint32_t)(n) << PORT_IOCR12_PC13_SHIFT)
#define PORT_IOCR12_PC14_SHIFT (19) /* Bit 3-7: Port Control for Port n Pin 14 */
#define PORT_IOCR12_PC14_MASK (31 << PORT_IOCR12_PC14_SHIFT)
# define PORT_IOCR12_PC14(n) ((uint32_t)(n) << PORT_IOCR12_PC14_SHIFT)
#define PORT_IOCR12_PC15_SHIFT (27) /* Bit 3-7: Port Control for Port 0 Pin 15 */
#define PORT_IOCR12_PC15_MASK (31 << PORT_IOCR12_PC15_SHIFT)
# define PORT_IOCR12_PC15(n) ((uint32_t)(n) << PORT_IOCR12_PC15_SHIFT)
/* Pad driver field values */
/* Pad class A1: */
#define PDR_PADA1_MEDIUM 0 /* Medium driver */
#define PDR_PADA1_WEAK 1 /* Weak driver */
/* Pad class A1+: */
#define PDR_PADA1P_STRONGSOFT 0 /* Strong driver soft edge */
#define PDR_PADA1P_STRONGSLOW 1 /* Strong driver slow edge */
#define PDR_PADA1P_MEDIUM 4 /* Medium driver */
#define PDR_PADA1P_WEAK 5 /* Weak driver */
/* Pad class A2: */
#define PDR_PADA2_STRONGSHARP 0 /* Strong driver sharp edge */
#define PDR_PADA2_STRONGMEDIUM 1 /* Strong driver medium edge */
#define PDR_PADA2_STRONGSOFT 2 /* Strong driver soft edge */
#define PDR_PADA2_MEDIUM 4 /* Medium driver */
#define PDR_PADA2_WEAK 7 /* Weak driver */
/* Port Pad Driver Mode 0 Register */
#define PORT_PDR0_PD_SHIFT(p) ((p) << 2)
#define PORT_PDR0_PD_MASK(p) (7 << PORT_PDR0_PD_SHIFT(p))
# define PORT_PDR0_PD(p,n) ((uint32_t)(n) << PORT_PDR0_PD_SHIFT(p))
#define PORT_PDR0_PD0_SHIFT (0) /* Bit 0-2: Pad Driver Mode for Port n Pin 0 */
#define PORT_PDR0_PD0_MASK (7 << PORT_PDR0_PD0_SHIFT)
# define PORT_PDR0_PD0(n) ((uint32_t)(n) << PORT_PDR0_PD0_SHIFT)
#define PORT_PDR0_PD1_SHIFT (4) /* Bit 4-6: Pad Driver Mode for Port n Pin 1 */
#define PORT_PDR0_PD1_MASK (7 << PORT_PDR0_PD1_SHIFT)
# define PORT_PDR0_PD1(n) ((uint32_t)(n) << PORT_PDR0_PD1_SHIFT)
#define PORT_PDR0_PD2_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 2 */
#define PORT_PDR0_PD2_MASK (7 << PORT_PDR0_PD2_SHIFT)
# define PORT_PDR0_PD2(n) ((uint32_t)(n) << PORT_PDR0_PD2_SHIFT)
#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 3 */
#define PORT_PDR0_PD3_MASK (7 << PORT_PDR0_PD3_SHIFT)
# define PORT_PDR0_PD3(n) ((uint32_t)(n) << PORT_PDR0_PD3_SHIFT)
#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 4 */
#define PORT_PDR0_PD4_MASK (7 << PORT_PDR0_PD4_SHIFT)
# define PORT_PDR0_PD4(n) ((uint32_t)(n) << PORT_PDR0_PD4_SHIFT)
#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 5 */
#define PORT_PDR0_PD5_MASK (7 << PORT_PDR0_PD5_SHIFT)
# define PORT_PDR0_PD5(n) ((uint32_t)(n) << PORT_PDR0_PD5_SHIFT)
#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 6 */
#define PORT_PDR0_PD6_MASK (7 << PORT_PDR0_PD6_SHIFT)
# define PORT_PDR0_PD6(n) ((uint32_t)(n) << PORT_PDR0_PD6_SHIFT)
#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 7 */
#define PORT_PDR0_PD7_MASK (7 << PORT_PDR0_PD7_SHIFT)
# define PORT_PDR0_PD7(n) ((uint32_t)(n) << PORT_PDR0_PD7_SHIFT)
/* Port Pad Driver Mode 1 Register */
#define PORT_PDR1_PD_SHIFT(p) (((p) - 8) << 2)
#define PORT_PDR1_PD_MASK(p) (7 << PORT_PDR1_PD_SHIFT(p))
# define PORT_PDR1_PD(p,n) ((uint32_t)(n) << PORT_PDR1_PD_SHIFT(p))
#define PORT_PDR1_PD8_SHIFT (0) /* Bit 0-2: Pad Driver Mode for Port n Pin 8 */
#define PORT_PDR1_PD8_MASK (7 << PORT_PDR1_PD8_SHIFT)
# define PORT_PDR1_PD8(n) ((uint32_t)(n) << PORT_PDR1_PD8_SHIFT)
#define PORT_PDR1_PD9_SHIFT (4) /* Bit 4-6: Pad Driver Mode for Port n Pin 9 */
#define PORT_PDR1_PD9_MASK (7 << PORT_PDR1_PD9_SHIFT)
# define PORT_PDR1_PD9(n) ((uint32_t)(n) << PORT_PDR1_PD9_SHIFT)
#define PORT_PDR1_PD10_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 10 */
#define PORT_PDR1_PD10_MASK (7 << PORT_PDR1_PD10_SHIFT)
# define PORT_PDR1_PD10(n) ((uint32_t)(n) << PORT_PDR1_PD10_SHIFT)
#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 11 */
#define PORT_PDR1_PD11_MASK (7 << PORT_PDR1_PD11_SHIFT)
# define PORT_PDR1_PD11(n) ((uint32_t)(n) << PORT_PDR1_PD11_SHIFT)
#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 12 */
#define PORT_PDR1_PD12_MASK (7 << PORT_PDR1_PD12_SHIFT)
# define PORT_PDR1_PD12(n) ((uint32_t)(n) << PORT_PDR1_PD12_SHIFT)
#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 13 */
#define PORT_PDR1_PD13_MASK (7 << PORT_PDR1_PD13_SHIFT)
# define PORT_PDR1_PD13(n) ((uint32_t)(n) << PORT_PDR1_PD13_SHIFT)
#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 14 */
#define PORT_PDR1_PD14_MASK (7 << PORT_PDR1_PD14_SHIFT)
# define PORT_PDR1_PD14(n) ((uint32_t)(n) << PORT_PDR1_PD14_SHIFT)
#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 15 */
#define PORT_PDR1_PD15_MASK (7 << PORT_PDR1_PD15_SHIFT)
# define PORT_PDR1_PD15(n) ((uint32_t)(n) << PORT_PDR1_PD15_SHIFT)
/* Hardware select field values */
#define HWSEL_SW 0 /* Software control only */
#define HWSEL_HW0 1 /* HWI0/HWO0 control path can override
* the software configuration */
#define HWSEL_HW1 2 /* HWI1/HWO1 control path can override
* the software configuration */
/* Port Pin Hardware Select Register */
#define PORT_HWSEL_HW_SHIFT(p) ((p) << 1)
#define PORT_HWSEL_HW_MASK(p) (3 << PORT_HWSEL_HW_SHIFT(p))
# define PORT_HWSEL_HW(p,n) ((uint32_t)(n) << PORT_HWSEL_HW_SHIFT(p))
#define PORT_HWSEL_HW0_SHIFT (0) /* Bit 0-1: Port n Pin 0 Hardware Select */
#define PORT_HWSEL_HW0_MASK (3 << PORT_HWSEL_HW0_SHIFT)
# define PORT_HWSEL_HW0(n) ((uint32_t)(n) << PORT_HWSEL_HW0_SHIFT)
#define PORT_HWSEL_HW1_SHIFT (2) /* Bit 2-3: Port n Pin 1 Hardware Select */
#define PORT_HWSEL_HW1_MASK (3 << PORT_HWSEL_HW1_SHIFT)
# define PORT_HWSEL_HW1(n) ((uint32_t)(n) << PORT_HWSEL_HW1_SHIFT)
#define PORT_HWSEL_HW2_SHIFT (4) /* Bit 4-5: Port n Pin 2 Hardware Select */
#define PORT_HWSEL_HW2_MASK (3 << PORT_HWSEL_HW2_SHIFT)
# define PORT_HWSEL_HW2(n) ((uint32_t)(n) << PORT_HWSEL_HW2_SHIFT)
#define PORT_HWSEL_HW3_SHIFT (6) /* Bit 6-7: Port 0 Pin 3 Hardware Select */
#define PORT_HWSEL_HW3_MASK (3 << PORT_HWSEL_HW3_SHIFT)
# define PORT_HWSEL_HW3(n) ((uint32_t)(n) << PORT_HWSEL_HW3_SHIFT)
#define PORT_HWSEL_HW4_SHIFT (8) /* Bit 8-9: Port 0 Pin 4 Hardware Select */
#define PORT_HWSEL_HW4_MASK (3 << PORT_HWSEL_HW4_SHIFT)
# define PORT_HWSEL_HW4(n) ((uint32_t)(n) << PORT_HWSEL_HW4_SHIFT)
#define PORT_HWSEL_HW5_SHIFT (10) /* Bit 10-11: Port 0 Pin 5 Hardware Select */
#define PORT_HWSEL_HW5_MASK (3 << PORT_HWSEL_HW5_SHIFT)
# define PORT_HWSEL_HW5(n) ((uint32_t)(n) << PORT_HWSEL_HW5_SHIFT)
#define PORT_HWSEL_HW6_SHIFT (12) /* Bit 12-13: Port 0 Pin 6 Hardware Select */
#define PORT_HWSEL_HW6_MASK (3 << PORT_HWSEL_HW6_SHIFT)
# define PORT_HWSEL_HW6(n) 14uint32_t)(n) << PORT_HWSEL_HW6_SHIFT)
#define PORT_HWSEL_HW7_SHIFT (14) /* Bit 14-15: Port 0 Pin 7 Hardware Select */
#define PORT_HWSEL_HW7_MASK (3 << PORT_HWSEL_HW7_SHIFT)
# define PORT_HWSEL_HW7(n) ((uint32_t)(n) << PORT_HWSEL_HW7_SHIFT)
#define PORT_HWSEL_HW8_SHIFT (16) /* Bit 16-17: Port n Pin 8 Hardware Select */
#define PORT_HWSEL_HW8_MASK (3 << PORT_HWSEL_HW8_SHIFT)
# define PORT_HWSEL_HW8(n) ((uint32_t)(n) << PORT_HWSEL_HW8_SHIFT)
#define PORT_HWSEL_HW9_SHIFT (18) /* Bit 18-19: Port n Pin 9 Hardware Select */
#define PORT_HWSEL_HW9_MASK (3 << PORT_HWSEL_HW9_SHIFT)
# define PORT_HWSEL_HW9(n) ((uint32_t)(n) << PORT_HWSEL_HW9_SHIFT)
#define PORT_HWSEL_HW10_SHIFT (20) /* Bit 20-21: Port n Pin 10 Hardware Select */
#define PORT_HWSEL_HW10_MASK (3 << PORT_HWSEL_HW10_SHIFT)
# define PORT_HWSEL_HW10(n) ((uint32_t)(n) << PORT_HWSEL_HW10_SHIFT)
#define PORT_HWSEL_HW11_SHIFT (22) /* Bit 22-23: Port 0 Pin 11 Hardware Select */
#define PORT_HWSEL_HW11_MASK (3 << PORT_HWSEL_HW11_SHIFT)
# define PORT_HWSEL_HW11(n) ((uint32_t)(n) << PORT_HWSEL_HW11_SHIFT)
#define PORT_HWSEL_HW12_SHIFT (24) /* Bit 24-25: Port 0 Pin 12 Hardware Select */
#define PORT_HWSEL_HW12_MASK (3 << PORT_HWSEL_HW12_SHIFT)
# define PORT_HWSEL_HW12(n) ((uint32_t)(n) << PORT_HWSEL_HW12_SHIFT)
#define PORT_HWSEL_HW13_SHIFT (26) /* Bit 26-27: Port 0 Pin 13 Hardware Select */
#define PORT_HWSEL_HW13_MASK (3 << PORT_HWSEL_HW13_SHIFT)
# define PORT_HWSEL_HW13(n) ((uint32_t)(n) << PORT_HWSEL_HW13_SHIFT)
#define PORT_HWSEL_HW14_SHIFT (28) /* Bit 28-29: Port 0 Pin 14 Hardware Select */
#define PORT_HWSEL_HW14_MASK (3 << PORT_HWSEL_HW14_SHIFT)
# define PORT_HWSEL_HW14(n) 14uint32_t)(n) << PORT_HWSEL_HW14_SHIFT)
#define PORT_HWSEL_HW15_SHIFT (30) /* Bit 30-31: Port 0 Pin 15 Hardware Select */
#define PORT_HWSEL_HW15_MASK (3 << PORT_HWSEL_HW15_SHIFT)
# define PORT_HWSEL_HW15(n) ((uint32_t)(n) << PORT_HWSEL_HW15_SHIFT)
#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H */

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/************************************************************************************
* arch/arm/src/xmc4/chip/xmc4_scu.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H
#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/xmc4_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
/* General SCU Registers */
#define XMC4_SCU_ID_OFFSET 0x0000 /* Module Identification Register */
#define XMC4_SCU_IDCHIP_OFFSET 0x0004 /* Chip ID */
#define XMC4_SCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */
#define XMC4_SCU_STCON_OFFSET 0x0010 /* Start-up Control */
#define XMC4_SCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */
#define XMC4_SCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */
#define XMC4_SCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */
#define XMC4_SCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */
#define XMC4_SCU_DTSCON_OFFSET 0x008c /* DTS Control */
#define XMC4_SCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */
#define XMC4_SCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */
#define XMC4_SCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */
#define XMC4_SCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */
#define XMC4_SCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */
#define XMC4_SCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */
#define XMC4_SCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */
/* Ethernet Control SCU Resters */
#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */
/* Interrupt Control SCU Registers */
#define XMC4_SCU_SRSTAT_OFFSET 0x0000 /* Service Request Status */
#define XMC4_SCU_SRRAW_OFFSET 0x0004 /* RAW Service Request Status */
#define XMC4_SCU_SRMSK_OFFSET 0x0008 /* Service Request Mask */
#define XMC4_SCU_SRCLR_OFFSET 0x000c /* Service Request Clear */
#define XMC4_SCU_SRSET_OFFSET 0x0010 /* Service Request Set */
#define XMC4_SCU_NMIREQEN_OFFSET 0x0014 /* Enable Promoting Events to NMI Request */
/* SDMMC Control SCU Registers */
#define XMC4_SCU_SDMMCCON_OFFSET 0x0000 /* SDMMC Configuration */
/* Parity Control Registers */
#define XMC4_SCU_PEEN_OFFSET 0x0000 /* Parity Error Enable Register */
#define XMC4_SCU_MCHKCON_OFFSET 0x0004 /* Memory Checking Control Register */
#define XMC4_SCU_PETE_OFFSET 0x0008 /* Parity Error Trap Enable Register */
#define XMC4_SCU_PERSTEN_OFFSET 0x000c /* Reset upon Parity Error Enable Register */
#define XMC4_SCU_PEFLAG_OFFSET 0x0014 /* Parity Error Control Register */
#define XMC4_SCU_PMTPR_OFFSET 0x0018 /* Parity Memory Test Pattern Register */
#define XMC4_SCU_PMTSR_OFFSET 0x001c /* Parity Memory Test Select Register */
/* Trap Control Registers */
#define XMC4_SCU_TRAPSTAT_OFFSET 0x0000 /* Trap Status Register */
#define XMC4_SCU_TRAPRAW_OFFSET 0x0004 /* Trap Raw Status Register */
#define XMC4_SCU_TRAPDIS_OFFSET 0x0008 /* Trap Mask Register */
#define XMC4_SCU_TRAPCLR_OFFSET 0x000c /* Trap Clear Register */
#define XMC4_SCU_TRAPSET_OFFSET 0x0010 /* Trap Set Register */
/* Power Control SCU Registers */
#define XMC4_SCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */
#define XMC4_SCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */
#define XMC4_SCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */
#define XMC4_SCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */
#define XMC4_SCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */
#define XMC4_SCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */
/* Hibernation SCU Registers */
#define XMC4_SCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */
#define XMC4_SCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */
#define XMC4_SCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */
#define XMC4_SCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */
#define XMC4_SCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */
#define XMC4_SCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */
#define XMC4_SCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */
/* Reset SCU Registers */
#define XMC4_SCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */
#define XMC4_SCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */
#define XMC4_SCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */
#define XMC4_SCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */
#define XMC4_SCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */
#define XMC4_SCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */
#define XMC4_SCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */
#define XMC4_SCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */
#define XMC4_SCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */
#define XMC4_SCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */
#define XMC4_SCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */
#define XMC4_SCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */
#define XMC4_SCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */
#define XMC4_SCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */
#define XMC4_SCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */
/* Clock Control SCU Registers */
#define XMC4_SCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */
#define XMC4_SCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */
#define XMC4_SCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */
#define XMC4_SCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */
#define XMC4_SCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */
#define XMC4_SCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */
#define XMC4_SCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */
#define XMC4_SCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */
#define XMC4_SCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */
#define XMC4_SCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */
#define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */
#define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */
#define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */
#define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */
#define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */
#define XMC4_SCU_CGATCLR0_OFFSET 0x0048 /* Peripheral 0 Clock Gating Clear */
#define XMC4_SCU_CGATSTAT1_OFFSET 0x004c /* Peripheral 1 Clock Gating Status */
#define XMC4_SCU_CGATSET1_OFFSET 0x0050 /* Peripheral 1 Clock Gating Set */
#define XMC4_SCU_CGATCLR1_OFFSET 0x0054 /* Peripheral 1 Clock Gating Clear */
#define XMC4_SCU_CGATSTAT2_OFFSET 0x0058 /* Peripheral 2 Clock Gating Status */
#define XMC4_SCU_CGATSET2_OFFSET 0x005c /* Peripheral 2 Clock Gating Set */
#define XMC4_SCU_CGATCLR2_OFFSET 0x0060 /* Peripheral 2 Clock Gating Clear */
#define XMC4_SCU_CGATSTAT3_OFFSET 0x0064 /* Peripheral 3 Clock Gating Status */
#define XMC4_SCU_CGATSET3_OFFSET 0x0068 /* Peripheral 3 Clock Gating Set */
#define XMC4_SCU_CGATCLR3_OFFSET 0x006c /* Peripheral 3 Clock Gating Clear */
/* Oscillator Control SCU Registers */
#define XMC4_SCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */
#define XMC4_SCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */
#define XMC4_SCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */
/* PLL Control SCU Registers */
#define XMC4_SCU_PLLSTAT_OFFSET 0x0000 /* System PLL Status Register */
#define XMC4_SCU_PLLCON0_OFFSET 0x0004 /* System PLL Configuration 0 Register */
#define XMC4_SCU_PLLCON1_OFFSET 0x0008 /* System PLL Configuration 1 Register */
#define XMC4_SCU_PLLCON2_OFFSET 0x000c /* System PLL Configuration 2 Register */
#define XMC4_SCU_USBPLLSTAT_OFFSET 0x0010 /* USB PLL Status Register */
#define XMC4_SCU_USBPLLCON_OFFSET 0x0014 /* USB PLL Control Register */
#define XMC4_SCU_CLKMXSTAT_OFFSET 0x0028 /* Clock Multiplexing Status Register */
/* Register Addresses ***************************************************************/
/* General SCU Registers */
#define XMC4_SCU_ID (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ID_OFFSET)
#define XMC4_SCU_IDCHIP (XMC4_SCU_GENERAL_BASE+XMC4_SCU_IDCHIP_OFFSET)
#define XMC4_SCU_IDMANUF (XMC4_SCU_GENERAL_BASE+XMC4_SCU_IDMANUF_OFFSET)
#define XMC4_SCU_STCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_STCON_OFFSET)
#define XMC4_SCU_GPR0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR0_OFFSET)
#define XMC4_SCU_GPR1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR1_OFFSET)
#define XMC4_SCU_ETH0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ETH0CON_OFFSET)
#define XMC4_SCU_CCUCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_CCUCON_OFFSET)
#define XMC4_SCU_DTSCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSCON_OFFSET)
#define XMC4_SCU_DTSSTAT (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSSTAT_OFFSET)
#define XMC4_SCU_SDMMCDEL (XMC4_SCU_GENERAL_BASE+XMC4_SCU_SDMMCDEL_OFFSET)
#define XMC4_SCU_G0ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G0ORCEN_OFFSET)
#define XMC4_SCU_G1ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G1ORCEN_OFFSET)
#define XMC4_SCU_MIRRSTS (XMC4_SCU_GENERAL_BASE+XMC4_SCU_MIRRSTS_OFFSET)
#define XMC4_SCU_RMACR (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMACR_OFFSET)
#define XMC4_SCU_RMADATA (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMADATA_OFFSET)
/* Ethernet Control SCU Registers */
#define XMC4_SCU_ETHCON (XMC4_ETH0_CON_BASE+XMC4_SCU_ETHCON_OFFSET)
/* Parity Control Registers */
#define XMC4_SCU_PEEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEEN_OFFSET)
#define XMC4_SCU_MCHKCON (XMC4_SCU_PARITY_BASE+XMC4_SCU_MCHKCON_OFFSET)
#define XMC4_SCU_PETE (XMC4_SCU_PARITY_BASE+XMC4_SCU_PETE_OFFSET)
#define XMC4_SCU_PERSTEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PERSTEN_OFFSET)
#define XMC4_SCU_PEFLAG (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEFLAG_OFFSET)
#define XMC4_SCU_PMTPR (XMC4_SCU_PARITY_BASE+XMC4_SCU_PMTPR_OFFSET)
#define XMC4_SCU_PMTSR (XMC4_SCU_PARITY_BASE+XMC4_SCU_PMTSR_OFFSET)
/* Trap Control Registers */
#define XMC4_SCU_TRAPSTAT (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSTAT_OFFSET)
#define XMC4_SCU_TRAPRAW (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPRAW_OFFSET)
#define XMC4_SCU_TRAPDIS (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPDIS_OFFSET)
#define XMC4_SCU_TRAPCLR (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPCLR_OFFSET)
#define XMC4_SCU_TRAPSET (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSET_OFFSET)
/* Ethernet Control SCU Resters */
#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */
#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */
/* Interrupt Control SCU Registers */
#define XMC4_SCU_SRSTAT (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSTAT_OFFSET)
#define XMC4_SCU_SRRAW (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRRAW_OFFSET)
#define XMC4_SCU_SRMSK (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRMSK_OFFSET)
#define XMC4_SCU_SRCLR (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRCLR_OFFSET)
#define XMC4_SCU_SRSET (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSET_OFFSET)
#define XMC4_SCU_NMIREQEN (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_NMIREQEN_OFFSET)
/* SDMMC Control SCU Registers */
#define XMC4_SCU_SDMMCCON (XMC4_SDMMC_CON_BASE+XMC4_SCU_SDMMCCON_OFFSET)
/* Power control SCU Registers */
#define XMC4_SCU_PWRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSTAT_OFFSET)
#define XMC4_SCU_PWRSET (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSET_OFFSET)
#define XMC4_SCU_PWRCLR (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRCLR_OFFSET)
#define XMC4_SCU_EVRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_EVRSTAT_OFFSET)
#define XMC4_SCU_EVRVADCSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_EVRVADCSTAT_OFFSET)
#define XMC4_SCU_PWRMON (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRMON_OFFSET)
/* Hibernation SCU Registers */
#define XMC4_SCU_HDSTAT (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDSTAT_OFFSET)
#define XMC4_SCU_HDCLR (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDCLR_OFFSET)
#define XMC4_SCU_HDSET (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDSET_OFFSET)
#define XMC4_SCU_HDCR (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDCR_OFFSET)
#define XMC4_SCU_OSCSICTRL (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCSICTRL_OFFSET)
#define XMC4_SCU_OSCULSTAT (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCULSTAT_OFFSET)
#define XMC4_SCU_OSCULCTRL (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCULCTRL_OFFSET)
/* Reset SCU Registers */
#define XMC4_SCU_RSTSTAT (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTSTAT_OFFSET)
#define XMC4_SCU_RSTSET (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTSET_OFFSET)
#define XMC4_SCU_RSTCLR (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTCLR_OFFSET)
#define XMC4_SCU_PRSTAT0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT0_OFFSET)
#define XMC4_SCU_PRSET0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET0_OFFSET)
#define XMC4_SCU_PRCLR0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR0_OFFSET)
#define XMC4_SCU_PRSTAT1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT1_OFFSET)
#define XMC4_SCU_PRSET1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET1_OFFSET)
#define XMC4_SCU_PRCLR1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR1_OFFSET)
#define XMC4_SCU_PRSTAT2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT2_OFFSET)
#define XMC4_SCU_PRSET2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET2_OFFSET)
#define XMC4_SCU_PRCLR2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR2_OFFSET)
#define XMC4_SCU_PRSTAT3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT3_OFFSET)
#define XMC4_SCU_PRSET3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET3_OFFSET)
#define XMC4_SCU_PRCLR3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR3_OFFSET)
/* Clock Control SCU Registers */
#define XMC4_SCU_CLKSTAT (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKSTAT_OFFSET)
#define XMC4_SCU_CLKSET (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKSET_OFFSET)
#define XMC4_SCU_CLKCLR (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKCLR_OFFSET)
#define XMC4_SCU_SYSCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SYSCLKCR_OFFSET)
#define XMC4_SCU_CPUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_CPUCLKCR_OFFSET)
#define XMC4_SCU_PBCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_PBCLKCR_OFFSET)
#define XMC4_SCU_USBCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_USBCLKCR_OFFSET)
#define XMC4_SCU_EBUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EBUCLKCR_OFFSET)
#define XMC4_SCU_CCUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_CCUCLKCR_OFFSET)
#define XMC4_SCU_WDTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_WDTCLKCR_OFFSET)
#define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET)
#define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET)
#define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET)
#define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET)
#define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET)
#define XMC4_SCU_CGATCLR0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR0_OFFSET)
#define XMC4_SCU_CGATSTAT1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT1_OFFSET)
#define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET)
#define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET)
#define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET)
#define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET
#define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET
#define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET
#define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET
#define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET_
/* Oscillator Control SCU Registers */
#define XMC4_SCU_OSCHPSTAT (XMC4_SCU_OSC_BASE+XMC4_SCU_OSCHPSTAT_OFFSET)
#define XMC4_SCU_OSCHPCTRL (XMC4_SCU_OSC_BASE+XMC4_SCU_OSCHPCTRL_OFFSET)
#define XMC4_SCU_CLKCALCONST (XMC4_SCU_OSC_BASE+XMC4_SCU_CLKCALCONST_OFFSET)
/* PLL Control SCU Registers */
#define XMC4_SCU_PLLSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLSTAT_OFFSET)
#define XMC4_SCU_PLLCON0 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON0_OFFSET)
#define XMC4_SCU_PLLCON1 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON1_OFFSET)
#define XMC4_SCU_PLLCON2 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON2_OFFSET)
#define XMC4_SCU_USBPLLSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLSTAT_OFFSET)
#define XMC4_SCU_USBPLLCON (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLCON_OFFSET)
#define XMC4_SCU_CLKMXSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_CLKMXSTAT_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* General SCU Registers */
/* Module Identification Register */
#define SCU_ID_
/* Chip ID */
#define SCU_IDCHIP_
/* Manufactory ID */
#define SCU_IDMANUF_
/* Start-up Control */
#define SCU_STCON_
/* General Purpose Register 0 */
#define SCU_GPR0_
/* General Purpose Register 1 */
#define SCU_GPR1_
/* Ethernet 0 Port Control */
#define SCU_ETH0CON_
/* CCUx Global Start Control Register */
#define SCU_CCUCON_
/* DTS Control */
#define SCU_DTSCON_
/* DTS Status */
#define SCU_DTSSTAT_
/* SD-MMC Delay Control Register */
#define SCU_SDMMCDEL_
/* Out-Of-Range Comparator Enable Register 0 */
#define SCU_G0ORCEN_
/* Out-Of-Range Comparator Enable Register 1 */
#define SCU_G1ORCEN_
/* Mirror Update Status Register */
#define SCU_MIRRSTS_HDCLR (1 << 1) /* Bit 1: HDCLR Mirror Register Write Status */
#define SCU_MIRRSTS_HDSET (1 << 2) /* Bit 2: HDSET Mirror Register Write Status */
#define SCU_MIRRSTS_HDCR (1 << 3) /* Bit 3: HDCR Mirror Register Write Status */
#define SCU_MIRRSTS_OSCSICTRL (1 << 5) /* Bit 5: OSCSICTRL Mirror Register Write Status */
#define SCU_MIRRSTS_OSCULSTAT (1 << 6) /* Bit 6: OSCULSTAT Mirror Register Write Status */
#define SCU_MIRRSTS_OSCULCTRL (1 << 7) /* Bit 7: OSCULCTRL Mirror Register Write Status */
#define SCU_MIRRSTS_RTC_CTR (1 << 8) /* Bit 8: RTC CTR Mirror Register Write Status */
#define SCU_MIRRSTS_RTC_ATIM0 (1 << 9) /* Bit 9: RTC ATIM0 Mirror Register Write Status */
#define SCU_MIRRSTS_RTC_ATIM1 (1 << 10) /* Bit 10: RTC ATIM1 Mirror Register Write Status */
#define SCU_MIRRSTS_RTC_TIM0 (1 << 11) /* Bit 11: RTC TIM0 Mirror Register Write Status */
#define SCU_MIRRSTS_RTC_TIM1 (1 << 12) /* Bit 12: RTC TIM1 Mirror Register Write Status */
#define SCU_MIRRSTS_RMX (1 << 13) /* Bit 13: Retention Memory Access Register Update Status */
#define SCU_MIRRSTS_RTC_MSKSR (1 << 14) /* Bit 14: RTC MSKSSR Mirror Register Write Status */
#define SCU_MIRRSTS_RTC_CLRSR (1 << 15) /* Bit 15: RTC CLRSR Mirror Register Write Status */
/* Ethernet Control SCU Resters */
/* Ethernet 0 Port Control Register */
#define SCU_ETHCON_
/* Interrupt Control SCU Registers */
/* Service Request Status */
#define SCU_SRSTAT_
/* RAW Service Request Status */
#define SCU_SRRAW_
/* Service Request Mask */
#define SCU_SRMSK_
/* Service Request Clear */
#define SCU_SRCLR_
/* Service Request Set */
#define SCU_SRSET_
/* Enable Promoting Events to NMI Request */
#define SCU_NMIREQEN_
/* Retention Memory Access Control Register */
#define SCU_RMACR_
/* Retention Memory Access Data Register */
#define SCU_RMADATA_
/* Parity Error Enable Register */
/* SDMMC Control SCU Registers */
/* SDMMC Configuration */
#define SCU_SDMMCCON_
/* Parity Control Registers */
#define SCU_PEEN_
/* Memory Checking Control Register */
#define SCU_MCHKCON_
/* Parity Error Trap Enable Register */
#define SCU_PETE_
/* Reset upon Parity Error Enable Register */
#define SCU_PERSTEN_
/* Parity Error Control Register */
#define SCU_PEFLAG_
/* Parity Memory Test Pattern Register */
#define SCU_PMTPR_
/* Parity Memory Test Select Register */
#define SCU_PMTSR_
/* Trap Control Registers */
/* Trap Status Register, Trap Raw Status Register, Trap Mask Register, Trap Clear
* Register, and Trap Set Register
*/
#define SCU_TRAP_SOSCWDGT (1 << 0) /* Bit 0: OSC_HP Oscillator Watchdog Trap */
#define SCU_TRAP_SVCOLCKT (1 << 2) /* Bit 2: System VCO Lock Trap */
#define SCU_TRAP_UVCOLCKT (1 << 3) /* Bit 3: USB VCO Lock Trap */
#define SCU_TRAP_PET (1 << 4) /* Bit 4: Parity Error Trap */
#define SCU_TRAP_BRWNT (1 << 5) /* Bit 5: Brown Out Trap */
#define SCU_TRAP_ULPWDGT (1 << 6) /* Bit 6: OSC_ULP Oscillator Watchdog Trap */
#define SCU_TRAP_BWERR0T (1 << 7) /* Bit 7: Peripheral Bridge 0 Trap */
#define SCU_TRAP_BWERR1T (1 << 8) /* Bit 8: Peripheral Bridge 1 Trap */
/* Power Control SCU Registers */
/* Power Status Register, Power Set Control Register, and Power Clear
* Control Register
*/
#define SCU_PWR_HIBEN (1 << 0) /* Bit 0: Hibernate Domain Enable State */
#define SCU_PWR_USBPHYPDQ (1 << 16) /* Bit 16: USB PHY Transceiver State */
#define SCU_PWR_USBOTGEN (1 << 17) /* Bit 17: USB On-The-Go Comparators State */
#define SCU_PWR_USBPUWQ (1 << 18) /* Bit 18: USB Weak Pull-Up at PADN State */
/* EVR Status Register */
#define SCU_EVRSTAT_
/* EVR VADC Status Register */
#define SCU_EVRVADCSTAT_
/* Power Monitor Value */
#define SCU_PWRMON_
/* Hibernation SCU Registers */
/* Hibernate Domain Status Register */
#define SCU_HDSTAT_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Status */
#define SCU_HDSTAT_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Status */
#define SCU_HDSTAT_RTCEV (1 << 2) /* Bit 2: RTC Event Status */
#define SCU_HDSTAT_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Status */
#define SCU_HDSTAT_HIBNOUT (1 << 4) /* Bit 3: Hibernate Control Status */
/* Hibernate Domain Status Clear Register */
#define SCU_HDCLR_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Clear */
#define SCU_HDCLR_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Clear */
#define SCU_HDCLR_RTCEV (1 << 2) /* Bit 2: RTC Event Clear */
#define SCU_HDCLR_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Clear */
/* Hibernate Domain Status Set Register */
#define SCU_HDSET_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Set */
#define SCU_HDSET_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Set */
#define SCU_HDSET_RTCEV (1 << 2) /* Bit 2: RTC Event Set */
#define SCU_HDSET_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Set */
/* Hibernate Domain Control Register */
#define SCU_HDCR_WKPEP (1 << 0) /* Bit 0: Wake-Up on Pin Event Positive Edge Enable */
#define SCU_HDCR_WKPEN (1 << 1) /* Bit 1: Wake-up on Pin Event Negative Edge Enable */
#define SCU_HDCR_RTCE (1 << 2) /* Bit 2: Wake-up on RTC Event Enable */
#define SCU_HDCR_ULPWDGEN (1 << 3) /* Bit 3: ULP WDG Alarm Enable */
#define SCU_HDCR_HIB (1 << 4) /* Bit 4: Hibernate Request Value Set */
#define SCU_HDCR_RCS (1 << 6) /* Bit 6: fRTC Clock Selection */
# define SCU_HDCR_RCS_OSI (0) /* 0=fOSI */
# define SCU_HDCR_RCS_ULP (1 << 6) /* 1=fULP */
#define SCU_HDCR_STDBYSEL (1 << 7) /* Bit 7: fSTDBY Clock Selection */
# define SCU_HDCR_STDBYSEL_OSI (0) /* 0=fOSI */
# define SCU_HDCR_STDBYSEL_ULP (1 << 7) /* 1=fULP */
#define SCU_HDCR_WKUPSEL (1 << 8) /* Bit 8: Wake-Up from Hibernate Trigger Input Select */
# define SCU_HDCR_WKUPSEL_HIBIO1 (0) /* 0=HIB_IO_1 pin selected */
# define SCU_HDCR_WKUPSEL_HIBIO0 (1 << 8) /* 1=HIB_IO_0 pin selected */
#define SCU_HDCR_GPI0SEL (1 << 10) /* Bit 10: General Purpose Input 0 Selection */
# define SCU_HDCR_GPIOSEL_HIBIO1 (0) /* 0=HIB_IO_1 pin selected */
# define SCU_HDCR_GPIOSEL_HIBIO0 (1 << 10) /* 1=HIB_IO_0 pin selected */
#define SCU_HDCR_HIBIO0POL (1 << 12) /* Bit 12: HIBIO0 Polarity Set */
# define SCU_HDCR_HIBIO0POL_DIR (0) /* 0=Direct */
# define SCU_HDCR_HIBIO0POL_INV (1 << 12) /* 1=Inverted */
#define SCU_HDCR_HIBIO1POL (1 << 13) /* Bit 13: HIBIO1 Polarity Set */
# define SCU_HDCR_HIBIO1POL_DIR (0) /* 0=Direct */
# define SCU_HDCR_HIBIO1POL_INV (1 << 13) /* 1=Inverted */
#define SCU_HDCR_HIBIO0SEL_SHIFT (16) /* Bits 16-19: HIB_IO_0 Pin I/O Control */
#define SCU_HDCR_HIBIO0SEL_MASK (15 << SCU_HDCR_HIBIO0SEL_SHIFT)
# define SCU_HDCR_HIBIO0SEL_DIR (0 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input */
# define SCU_HDCR_HIBIO0SEL_DIRPD (1 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input, Input pull-down */
# define SCU_HDCR_HIBIO0SEL_DIRPU (2 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input, Input pull-up */
# define SCU_HDCR_HIBIO0SEL_PP (8 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull HIB Control output */
# define SCU_HDCR_HIBIO0SEL_PPWDT (9 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull WDT service output */
# define SCU_HDCR_HIBIO0SEL_PPGPIO (10 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull GPIO output */
# define SCU_HDCR_HIBIO0SEL_OD (12 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain HIB Control output */
# define SCU_HDCR_HIBIO0SEL_ODWDT (13 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain WDT service output */
# define SCU_HDCR_HIBIO0SEL_ODGPIO (14 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain GPIO output */
#define SCU_HDCR_HIBIO1SEL_SHIFT (20) /* Bits 20-23: HIB_IO_1 Pin I/O Control */
#define SCU_HDCR_HIBIO1SEL_MASK (15 << SCU_HDCR_HIBIO1SEL_SHIFT)
# define SCU_HDCR_HIBIO1SEL_DIR (0 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input */
# define SCU_HDCR_HIBIO1SEL_DIRPD (1 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input, Input pull-down */
# define SCU_HDCR_HIBIO1SEL_DIRPU (2 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input, Input pull-up */
# define SCU_HDCR_HIBIO1SEL_PP (8 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull HIB Control output */
# define SCU_HDCR_HIBIO1SEL_PPWDT (9 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull WDT service output */
# define SCU_HDCR_HIBIO1SEL_PPGPIO (10 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull GPIO output */
# define SCU_HDCR_HIBIO1SEL_OD (12 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain HIB Control output */
# define SCU_HDCR_HIBIO1SEL_ODWDT (13 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain WDT service output */
# define SCU_HDCR_HIBIO1SEL_ODGPIO (14 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain GPIO output */
/* Internal 32.768 kHz Clock Source Control Register */
#define SCU_OSCSICTRL_
/* OSC_ULP Status Register */
#define SCU_OSCULSTAT_X1D (1 << 0) /* Bit 0: XTAL1 Data Value */
/* OSC_ULP Control Register */
#define SCU_OSCULCTRL_X1DEN (1 << 0) /* Bit 0: XTAL1 Data General Purpose Input Enable */
#define SCU_OSCULCTRL_MODE_SHIFT (4) /* Bits 4-5: Oscillator Mode */
#define SCU_OSCULCTRL_MODE_MASK (3 << SCU_OSCULCTRL_MODE_SHIFT)
# define SCU_OSCULCTRL_MODE_OPER (0 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC enabled in operation */
# define SCU_OSCULCTRL_MODE_BYPASS (1 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC enabled in bypass */
# define SCU_OSCULCTRL_MODE_PDN (2 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC power down */
# define SCU_OSCULCTRL_MODE_PDNGPI (3 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC power down, GPI possible */
/* Reset SCU Registers */
/* System Reset Status */
#define SCU_RSTSTAT_RSTSTAT_SHIFT (0) /* Bits 0-7: Reset Status Information */
#define SCU_RSTSTAT_RSTSTAT_MASK (0xff << SCU_RSTSTAT_RSTSTAT_SHIFT)
# define SCU_RSTSTAT_RSTSTAT_PORST (1 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* PORST reset */
# define SCU_RSTSTAT_RSTSTAT_SWD (2 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* SWD reset */
# define SCU_RSTSTAT_RSTSTAT_PV (4 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* PV reset */
# define SCU_RSTSTAT_RSTSTAT_CPUSYS (8 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* CPU system reset */
# define SCU_RSTSTAT_RSTSTAT_CPULOCK (16 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* CPU lockup reset */
# define SCU_RSTSTAT_RSTSTAT_WDT (32 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* WDT reset */
# define SCU_RSTSTAT_RSTSTAT_PERR (128 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* Parity Error reset */
#define SCU_RSTSTAT_HIBWK (1 << 8) /* Bit 8: Hibernate Wake-up Status */
#define SCU_RSTSTAT_HIBRS (1 << 9) /* Bit 9: Hibernate Reset Status */
#define SCU_RSTSTAT_LCKEN (1 << 10) /* Bit 10: Enable Lockup Status */
/* Reset Set Register */
#define SCU_RSTSET_HIBWK (1 << 8) /* Bit 8: Hibernate Wake-up Reset Status */
#define SCU_RSTSET_HIBRS (1 << 9) /* Bit 9: Hibernate Reset Reset Status */
#define SCU_RSTSET_LCKEN (1 << 10) /* Bit 10: Enable Lockup Reset Status */
/* Reset Clear Register */
#define SCU_RSTCLR_RSCLR (1 << 0) /* Bit 0: Clear Reset Status */
#define SCU_RSTCLR_HIBWK (1 << 8) /* Bit 8: Clear Hibernate Wake-up Reset Status */
#define SCU_RSTCLR_HIBRS (1 << 9) /* Bit 9: Clear Hibernate Reset */
#define SCU_RSTCLR_LCKEN (1 << 10) /* Bit 10: Clear Hibernate Reset */
/* Peripheral Reset Status Register 0 */
#define SCU_PRSTAT0_
/* Peripheral Reset Set Register 0 */
#define SCU_PRSET0_
/* Peripheral Reset Clear Register 0 */
#define SCU_PRCLR0_
/* Peripheral Reset Status Register 1 */
#define SCU_PRSTAT1_
/* Peripheral Reset Set Register 1 */
#define SCU_PRSET1_
/* Peripheral Reset Clear Register 1 */
#define SCU_PRCLR1_
/* Peripheral Reset Status Register 2 */
#define SCU_PRSTAT2_
/* Peripheral Reset Set Register 2 */
#define SCU_PRSET2_
/* Peripheral Reset Clear Register 2 */
#define SCU_PRCLR2_
/* Peripheral Reset Status Register 3 */
#define SCU_PRSTAT3_
/* Peripheral Reset Set Register 3 */
#define SCU_PRSET3_
/* Peripheral Reset Clear Register 3 */
#define SCU_PRCLR3_
/* Clock Control SCU Registers */
/* Clock Status Register */
#define SCU_CLKSTAT_
/* Clock Set Control Register */
#define SCU_CLKSET_
/* Clock clear Control Register */
#define SCU_CLKCLR_
/* System Clock Control */
#define SCU_SYSCLKCR_SYSDIV_SHIFT (0) /* Bits 0-7: System Clock Division Value */
#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_SYSCLKCR_SYSDIV_SHIFT)
# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_SYSCLKCR_SYSDIV_SHIFT)
#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */
# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */
# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */
/* CPU Clock Control */
#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */
/* Peripheral Bus Clock Control */
#define SCU_PBCLKCR_
/* USB Clock Control */
#define SCU_USBCLKCR_USBDIV_SHIFT (0) /* Bits 0-2: USB Clock Divider Value */
#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_USBCLKCR_USBDIV_SHIFT)
# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_USBCLKCR_USBDIV_SHIFT)
#define SCU_USBCLKCR_USBSEL (1 << 16) /* Bit 16: USB Clock Selection Value */
# define SCU_USBCLKCR_USBSEL_USBPLL (0) /* 0=USB PLL Clock */
# define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */
/* EBU Clock Control */
#define SCU_EBUCLKCR_
/* CCU Clock Control */
#define SCU_CCUCLKCR_
/* WDT Clock Control */
#define SCU_WDTCLKCR_
/* External clock Control Register */
#define SCU_EXTCLKCR_
/* Sleep Control Register */
#define SCU_SLEEPCR_
/* Deep Sleep Control Register */
#define SCU_DSLEEPCR_
/* Peripheral 0 Clock Gating Status */
#define SCU_CGATSTAT0_
/* Peripheral 0 Clock Gating Set */
#define SCU_CGATSET0_
/* Peripheral 0 Clock Gating Clear */
#define SCU_CGATCLR0_
/* Peripheral 1 Clock Gating Status */
#define SCU_CGATSTAT1_
/* Peripheral 1 Clock Gating Set */
#define SCU_CGATSET1_
/* Peripheral 1 Clock Gating Clear */
#define SCU_CGATCLR1_
/* Peripheral 2 Clock Gating Status */
#define SCU_CGATSTAT2_
/* Peripheral 2 Clock Gating Set */
#define SCU_CGATSET2_
/* Peripheral 2 Clock Gating Clear */
#define SCU_CGATCLR2_
/* Peripheral 3 Clock Gating Status */
#define SCU_CGATSTAT3_
/* Peripheral 3 Clock Gating Set */
#define SCU_CGATSET3_
/* Peripheral 3 Clock Gating Clear */
#define SCU_CGATCLR3_
/* Oscillator Control SCU Registers */
/* OSC_HP Status Register */
#define SCU_OSCHPSTAT_
/* OSC_HP Control Register */
#define SCU_OSCHPCTRL_X1DEN (1 << 0) /* Bit 0: XTAL1 Data Enable */
#define SCU_OSCHPCTRL_SHBY (1 << 1) /* Bit 1: Shaper Bypass */
#define SCU_OSCHPCTRL_GAINSEL_SHIFT (2) /* Bits 2-3: */
#define SCU_OSCHPCTRL_GAINSEL_MASK (3 << SCU_OSCHPCTRL_GAINSEL_SHIFT)
# define SCU_OSCHPCTRL_GAINSEL(n) ((uint32_t)(n) << SCU_OSCHPCTRL_GAINSEL_SHIFT)
#define SCU_OSCHPCTRL_MODE_SHIFT (4)
#define SCU_OSCHPCTRL_MODE_MASK (3 << SCU_OSCHPCTRL_MODE_SHIFT)
# define SCU_OSCHPCTRL_MODE_XTAL (0 << SCU_OSCHPCTRL_MODE_SHIFT) /* External Crystal Mode */
# define SCU_OSCHPCTRL_MODE_DIS (1 << SCU_OSCHPCTRL_MODE_SHIFT) /* OSC is disabled */
# define SCU_OSCHPCTRL_MODE_EXTIN (2 << SCU_OSCHPCTRL_MODE_SHIFT) /* External Input Clock Mode */
# define SCU_OSCHPCTRL_MODE_DISPSM (3 << SCU_OSCHPCTRL_MODE_SHIFT) /* OSC is disabled, Power-Saving Mode */
#define SCU_OSCHPCTRL_OSCVAL_SHIFT (16)
#define SCU_OSCHPCTRL_OSCVAL_MASK (15 << SCU_OSCHPCTRL_OSCVAL_SHIFT)
# define SCU_OSCHPCTRL_OSCVAL(n) ((uint32_t)((n)-1) << SCU_OSCHPCTRL_OSCVAL_SHIFT)
/* Clock Calibration Constant Register */
#define SCU_CLKCALCONST_
/* PLL Control SCU Registers */
/* System PLL Status Register */
#define SCU_PLLSTAT_VCOBYST (1 << 0) /* Bit 0: VCO Bypass Status */
#define SCU_PLLSTAT_PWDSTAT (1 << 1) /* Bit 1: PLL Power-saving Mode Status */
#define SCU_PLLSTAT_VCOLOCK (1 << 2) /* Bit 2: PLL LOCK Status */
#define SCU_PLLSTAT_K1RDY (1 << 4) /* Bit 4: K1 Divider Ready Status */
#define SCU_PLLSTAT_K2RDY (1 << 5) /* Bit 5: K2 Divider Ready Status */
#define SCU_PLLSTAT_BY (1 << 6) /* Bit 6: Bypass Mode Status */
#define SCU_PLLSTAT_PLLLV (1 << 7) /* Bit 7: Oscillator for PLL Valid Low Status */
#define SCU_PLLSTAT_PLLHV (1 << 8) /* Bit 8: Oscillator for PLL Valid High Status */
#define SCU_PLLSTAT_PLLSP (1 << 9) /* Bit 9: Oscillator for PLL Valid Spike Status */
/* System PLL Configuration 0 Register */
#define SCU_PLLCON0_VCOBYP (1 << 0) /* Bit 0: VCO Bypass */
#define SCU_PLLCON0_VCOPWD (1 << 1) /* Bit 1: VCO Power Saving Mode */
#define SCU_PLLCON0_VCOTR (1 << 2) /* Bit 2: VCO Trim Control */
#define SCU_PLLCON0_FINDIS (1 << 4) /* Bit 4: Disconnect Oscillator from VCO */
#define SCU_PLLCON0_OSCDISCDIS (1 << 6) /* Bit 6: Oscillator Disconnect Disable */
#define SCU_PLLCON0_PLLPWD (1 << 16) /* Bit 16: PLL Power Saving Mode */
#define SCU_PLLCON0_OSCRES (1 << 17) /* Bit 17: Oscillator Watchdog Reset */
#define SCU_PLLCON0_RESLD (1 << 18) /* Bit 18: Restart VCO Lock Detection */
#define SCU_PLLCON0_AOTREN (1 << 19) /* Bit 19: Automatic Oscillator Calibration Enable */
#define SCU_PLLCON0_FOTR (1 << 20) /* Bit 20: Factory Oscillator Calibration */
/* System PLL Configuration 1 Register */
#define SCU_PLLCON1_K1DIV_SHIFT (0) /* Bits 0-6: K1-Divider Value */
#define SCU_PLLCON1_K1DIV_MASK (0x7f << SCU_PLLCON1_K1DIV_SHIFT)
# define SCU_PLLCON1_K1DIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_K1DIV_SHIFT)
#define SCU_PLLCON1_NDIV_SHIFT (8) /* Bits 8-14: N-Divider Value */
#define SCU_PLLCON1_NDIV_MASK (0x7f << SCU_PLLCON1_NDIV_SHIFT)
# define SCU_PLLCON1_NDIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_NDIV_SHIFT)
#define SCU_PLLCON1_K2DIV_SHIFT (16) /* Bit 16-22: K2-Divider Value */
#define SCU_PLLCON1_K2DIV_MASK (0x7f << SCU_PLLCON1_K2DIV_SHIFT)
# define SCU_PLLCON1_K2DIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_K2DIV_SHIFT)
#define SCU_PLLCON1_PDIV_SHIFT (24) /* Bits 24-27: P-Divider Value */
#define SCU_PLLCON1_PDIV_MASK (0x7f << SCU_PLLCON1_PDIV_SHIFT)
# define SCU_PLLCON1_PDIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_PDIV_SHIFT)
/* System PLL Configuration 2 Register */
#define SCU_PLLCON2_PINSEL (1 << 0) /* Bit 0: P-Divider Input Selection */
# define SCU_PLLCON2_PINSEL_PLL (0) /* 0=PLL external oscillator selected */
# define SCU_PLLCON2_PINSEL_OFI (1 << 0) /* 1=Backup clock source selected */
#define SCU_PLLCON2_K1INSEL (1 << 8) /* Bit 8: K1-Divider Input */
# define SCU_PLLCON2_K1INSEL_PLL (0) /* 0=PLL external oscillator selected */
# define SCU_PLLCON2_K1INSEL_OFI (1 << 8) /* 1=Backup clock source selected */
/* USB PLL Status Register */
#define SCU_USBPLLSTAT_VCOBYST (1 << 0) /* Bit 0: VCO Bypass Status */
#define SCU_USBPLLSTAT_PWDSTAT (1 << 1) /* Bit 1: PLL Power-saving Mode Status */
#define SCU_USBPLLSTAT_VCOLOCK (1 << 2) /* Bit 2: PLL VCO Lock Status */
#define SCU_USBPLLSTAT_BY (1 << 6) /* Bit 6: Bypass Mode Status */
#define SCU_USBPLLSTAT_VCOLOCKED (1 << 7) /* Bit 7: PLL LOCK Status */
/* USB PLL Control Register */
#define SCU_USBPLLCON_VCOBYP (1 << 0) /* Bit 0: VCO Bypass */
#define SCU_USBPLLCON_VCOPWD (1 << 1) /* Bit 1: VCO Power Saving Mode */
#define SCU_USBPLLCON_VCOTR (1 << 2) /* Bit 2: VCO Trim Control */
#define SCU_USBPLLCON_FINDIS (1 << 4) /* Bit 4: Disconnect Oscillator from VCO */
#define SCU_USBPLLCON_OSCDISCDIS (1 << 6) /* Bit 6: Oscillator Disconnect Disable */
#define SCU_USBPLLCON_NDIV_SHIFT (8) /* Bits 8-14: N-Divider Val */
#define SCU_USBPLLCON_NDIV_MASK (0x7f << SCU_USBPLLCON_NDIV_SHIFT)
# define SCU_USBPLLCON_NDIV(n) ((uint32_t)((n)-1) << SCU_USBPLLCON_NDIV_SHIFT)
#define SCU_USBPLLCON_PLLPWD (1 << 16) /* Bit 16: PLL Power Saving Mode */
#define SCU_USBPLLCON_RESLD (1 << 18) /* Bit 18: Restart VCO Lock Detection */
#define SCU_USBPLLCON_PDIV_SHIFT (24) /* Bits 24-27: P-Divider Value */
#define SCU_USBPLLCON_PDIV_MASK (15 << SCU_USBPLLCON_PDIV_SHIFT)
# define SCU_USBPLLCON_PDIV(n) ((uint32_t)((n)-1) << SCU_USBPLLCON_PDIV_SHIFT)
/* Clock Multiplexing Status Register */
#define SCU_CLKMXSTAT_SYSCLKMUX_SHIFT (0) /* Bits 0-1: System Clock Multiplexing Status */
#define SCU_CLKMXSTAT_SYSCLKMUX_MASK (3 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT)
# define SCU_CLKMXSTAT_SYSCLKMUX_OFI (1 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT)
# define SCU_CLKMXSTAT_SYSCLKMUX_PLL (2 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT)
#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */

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/************************************************************************************
* arch/arm/src/xmc4/chip/xmc4_usic.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H
#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/xmc4_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
/* PMU Registers -- See ID register */
/* Prefetch Registers -- See PCON register */
/* Kernal Registers */
#define XMC4_USIC_ID_OFFSET 0x0008 /* Kernel State Configuration Register */
/* USIC Channel Registers */
#define XMC4_USIC_CCFG_OFFSET 0x0004 /* Channel Configuration Register */
#define XMC4_USIC_KSCFG_OFFSET 0x000c /* Kernel State Configuration Register */
#define XMC4_USIC_FDR_OFFSET 0x0010 /* Fractional Divider Register */
#define XMC4_USIC_BRG_OFFSET 0x0014 /* Baud Rate Generator Register */
#define XMC4_USIC_INPR_OFFSET 0x0018 /* Interrupt Node Pointer Register */
#define XMC4_USIC_DX0CR_OFFSET 0x001c /* Input Control Register 0 */
#define XMC4_USIC_DX1CR_OFFSET 0x0020 /* Input Control Register 1 */
#define XMC4_USIC_DX2CR_OFFSET 0x0024 /* Input Control Register 2 */
#define XMC4_USIC_DX3CR_OFFSET 0x0028 /* Input Control Register 3 */
#define XMC4_USIC_DX4CR_OFFSET 0x002c /* Input Control Register 4 */
#define XMC4_USIC_DX5CR_OFFSET 0x0030 /* Input Control Register 5 */
#define XMC4_USIC_SCTR_OFFSET 0x0034 /* Shift Control Register */
#define XMC4_USIC_TCSR_OFFSET 0x0038 /* Transmit Control/Status Register */
#define XMC4_USIC_PCR_OFFSET 0x003c /* Protocol Control Register */
#define XMC4_USIC_CCR_OFFSET 0x0040 /* Channel Control Register */
#define XMC4_USIC_CMTR_OFFSET 0x0044 /* Capture Mode Timer Register */
#define XMC4_USIC_PSR_OFFSET 0x0048 /* Protocol Status Register */
#define XMC4_USIC_PSCR_OFFSET 0x004c /* Protocol Status Clear Register */
#define XMC4_USIC_RBUFSR_OFFSET 0x0050 /* Receiver Buffer Status Register */
#define XMC4_USIC_RBUF_OFFSET 0x0054 /* Receiver Buffer Register */
#define XMC4_USIC_RBUFD_OFFSET 0x0058 /* Receiver Buffer Register for Debugger */
#define XMC4_USIC_RBUF0_OFFSET 0x005c /* Receiver Buffer Register 0 */
#define XMC4_USIC_RBUF1_OFFSET 0x0060 /* Receiver Buffer Register 1 */
#define XMC4_USIC_RBUF01SR_OFFSET 0x0064 /* Receiver Buffer 01 Status Register */
#define XMC4_USIC_FMR_OFFSET 0x0068 /* Flag Modification Register */
#define XMC4_USIC_TBUF_OFFSET 0x0080 /* Transmit Buffer (32 x 4-bytes) */
/* USIC FIFO Registers */
#define XMC4_USIC_BYP_OFFSET 0x0100 /* Bypass Data Register */
#define XMC4_USIC_BYPCR_OFFSET 0x0104 /* Bypass Control Register */
#define XMC4_USIC_TBCTR_OFFSET 0x0108 /* Transmitter Buffer Control Register */
#define XMC4_USIC_RBCTR_OFFSET 0x010c /* Receiver Buffer Control Register */
#define XMC4_USIC_TRBPTR_OFFSET 0x0110 /* Transmit/Receive Buffer Pointer Register */
#define XMC4_USIC_TRBSR_OFFSET 0x0114 /* Transmit/Receive Buffer Status Register */
#define XMC4_USIC_TRBSCR_OFFSET 0x0118 /* Transmit/Receive Buffer Status Clear Register */
#define XMC4_USIC_OUTR_OFFSET 0x011c /* Receiver Buffer Output Register */
#define XMC4_USIC_OUTDR_OFFSET 0x0120 /* Receiver Buffer Output Register L for Debugger */
#define XMC4_USIC_IN_OFFSET 0x0180 /* Transmit FIFO Buffer (32 x 4-bytes) */
/* Register Addresses ****************************************************************/
/* USIC0 Registers */
/* Kernal Registers */
#define XMC4_USIC0_ID (XMC4_USIC0_BASE+XMC4_USIC_ID_OFFSET)
/* USIC0 Channel 0 Registers */
#define XMC4_USIC00_CCFG (XMC4_USIC0_CH0_BASE+XMC4_USIC_CCFG_OFFSET)
#define XMC4_USIC00_KSCFG (XMC4_USIC0_CH0_BASE+XMC4_USIC_KSCFG_OFFSET)
#define XMC4_USIC00_FDR (XMC4_USIC0_CH0_BASE+XMC4_USIC_FDR_OFFSET)
#define XMC4_USIC00_BRG (XMC4_USIC0_CH0_BASE+XMC4_USIC_BRG_OFFSET)
#define XMC4_USIC00_INPR (XMC4_USIC0_CH0_BASE+XMC4_USIC_INPR_OFFSET)
#define XMC4_USIC00_DX0CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX0CR_OFFSET)
#define XMC4_USIC00_DX1CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX1CR_OFFSET)
#define XMC4_USIC00_DX2CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX2CR_OFFSET)
#define XMC4_USIC00_DX3CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX3CR_OFFSET)
#define XMC4_USIC00_DX4CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX4CR_OFFSET)
#define XMC4_USIC00_DX5CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX5CR_OFFSET)
#define XMC4_USIC00_SCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_SCTR_OFFSET)
#define XMC4_USIC00_TCSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TCSR_OFFSET)
#define XMC4_USIC00_PCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PCR_OFFSET)
#define XMC4_USIC00_CCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_CCR_OFFSET)
#define XMC4_USIC00_CMTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_CMTR_OFFSET)
#define XMC4_USIC00_PSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PSR_OFFSET)
#define XMC4_USIC00_PSCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PSCR_OFFSET)
#define XMC4_USIC00_RBUFSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET)
#define XMC4_USIC00_RBUF (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF_OFFSET)
#define XMC4_USIC00_RBUFD (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUFD_OFFSET)
#define XMC4_USIC00_RBUF0 (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF0_OFFSET)
#define XMC4_USIC00_RBUF1 (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF1_OFFSET)
#define XMC4_USIC00_RBUF01SR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET)
#define XMC4_USIC00_FMR (XMC4_USIC0_CH0_BASE+XMC4_USIC_FMR_OFFSET)
#define XMC4_USIC00_TBUF (XMC4_USIC0_CH0_BASE+XMC4_USIC_TBUF_OFFSET)
/* USIC0 Channel 0 FIFO Registers */
#define XMC4_USIC00_BYP (XMC4_USIC0_CH0_BASE+XMC4_USIC_BYP_OFFSET)
#define XMC4_USIC00_BYPCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_BYPCR_OFFSET)
#define XMC4_USIC00_TBCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TBCTR_OFFSET)
#define XMC4_USIC00_RBCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBCTR_OFFSET)
#define XMC4_USIC00_TRBPTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET)
#define XMC4_USIC00_TRBSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBSR_OFFSET)
#define XMC4_USIC00_TRBSCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET)
#define XMC4_USIC00_OUTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_OUTR_OFFSET)
#define XMC4_USIC00_OUTDR (XMC4_USIC0_CH0_BASE+XMC4_USIC_OUTDR_OFFSET)
#define XMC4_USIC00_IN (XMC4_USIC0_CH0_BASE+XMC4_USIC_IN_OFFSET)
/* USIC0 Channel 1 Registers */
#define XMC4_USIC01_CCFG (XMC4_USIC0_CH1_BASE+XMC4_USIC_CCFG_OFFSET)
#define XMC4_USIC01_KSCFG (XMC4_USIC0_CH1_BASE+XMC4_USIC_KSCFG_OFFSET)
#define XMC4_USIC01_FDR (XMC4_USIC0_CH1_BASE+XMC4_USIC_FDR_OFFSET)
#define XMC4_USIC01_BRG (XMC4_USIC0_CH1_BASE+XMC4_USIC_BRG_OFFSET)
#define XMC4_USIC01_INPR (XMC4_USIC0_CH1_BASE+XMC4_USIC_INPR_OFFSET)
#define XMC4_USIC01_DX0CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX0CR_OFFSET)
#define XMC4_USIC01_DX1CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX1CR_OFFSET)
#define XMC4_USIC01_DX2CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX2CR_OFFSET)
#define XMC4_USIC01_DX3CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX3CR_OFFSET)
#define XMC4_USIC01_DX4CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX4CR_OFFSET)
#define XMC4_USIC01_DX5CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX5CR_OFFSET)
#define XMC4_USIC01_SCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_SCTR_OFFSET)
#define XMC4_USIC01_TCSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TCSR_OFFSET)
#define XMC4_USIC01_PCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PCR_OFFSET)
#define XMC4_USIC01_CCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_CCR_OFFSET)
#define XMC4_USIC01_CMTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_CMTR_OFFSET)
#define XMC4_USIC01_PSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PSR_OFFSET)
#define XMC4_USIC01_PSCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PSCR_OFFSET)
#define XMC4_USIC01_RBUFSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET)
#define XMC4_USIC01_RBUF (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF_OFFSET)
#define XMC4_USIC01_RBUFD (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUFD_OFFSET)
#define XMC4_USIC01_RBUF0 (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF0_OFFSET)
#define XMC4_USIC01_RBUF1 (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF1_OFFSET)
#define XMC4_USIC01_RBUF01SR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET)
#define XMC4_USIC01_FMR (XMC4_USIC0_CH1_BASE+XMC4_USIC_FMR_OFFSET)
#define XMC4_USIC01_TBUF (XMC4_USIC0_CH1_BASE+XMC4_USIC_TBUF_OFFSET)
/* USIC0 Channel 1 FIFO Registers */
#define XMC4_USIC01_BYP (XMC4_USIC0_CH1_BASE+XMC4_USIC_BYP_OFFSET)
#define XMC4_USIC01_BYPCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_BYPCR_OFFSET)
#define XMC4_USIC01_TBCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TBCTR_OFFSET)
#define XMC4_USIC01_RBCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBCTR_OFFSET)
#define XMC4_USIC01_TRBPTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET)
#define XMC4_USIC01_TRBSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBSR_OFFSET)
#define XMC4_USIC01_TRBSCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET)
#define XMC4_USIC01_OUTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_OUTR_OFFSET)
#define XMC4_USIC01_OUTDR (XMC4_USIC0_CH1_BASE+XMC4_USIC_OUTDR_OFFSET)
#define XMC4_USIC01_IN (XMC4_USIC0_CH1_BASE+XMC4_USIC_IN_OFFSET)
/* USIC1 Registers */
/* Kernal Registers */
#define XMC4_USIC1_ID (XMC4_USIC1_BASE+XMC4_USIC_ID_OFFSET)
/* USIC1 Channel 0 Registers */
#define XMC4_USIC10_CCFG (XMC4_USIC1_CH0_BASE+XMC4_USIC_CCFG_OFFSET)
#define XMC4_USIC10_KSCFG (XMC4_USIC1_CH0_BASE+XMC4_USIC_KSCFG_OFFSET)
#define XMC4_USIC10_FDR (XMC4_USIC1_CH0_BASE+XMC4_USIC_FDR_OFFSET)
#define XMC4_USIC10_BRG (XMC4_USIC1_CH0_BASE+XMC4_USIC_BRG_OFFSET)
#define XMC4_USIC10_INPR (XMC4_USIC1_CH0_BASE+XMC4_USIC_INPR_OFFSET)
#define XMC4_USIC10_DX0CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX0CR_OFFSET)
#define XMC4_USIC10_DX1CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX1CR_OFFSET)
#define XMC4_USIC10_DX2CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX2CR_OFFSET)
#define XMC4_USIC10_DX3CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX3CR_OFFSET)
#define XMC4_USIC10_DX4CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX4CR_OFFSET)
#define XMC4_USIC10_DX5CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX5CR_OFFSET)
#define XMC4_USIC10_SCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_SCTR_OFFSET)
#define XMC4_USIC10_TCSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TCSR_OFFSET)
#define XMC4_USIC10_PCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PCR_OFFSET)
#define XMC4_USIC10_CCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_CCR_OFFSET)
#define XMC4_USIC10_CMTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_CMTR_OFFSET)
#define XMC4_USIC10_PSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PSR_OFFSET)
#define XMC4_USIC10_PSCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PSCR_OFFSET)
#define XMC4_USIC10_RBUFSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET)
#define XMC4_USIC10_RBUF (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF_OFFSET)
#define XMC4_USIC10_RBUFD (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUFD_OFFSET)
#define XMC4_USIC10_RBUF0 (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF0_OFFSET)
#define XMC4_USIC10_RBUF1 (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF1_OFFSET)
#define XMC4_USIC10_RBUF01SR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET)
#define XMC4_USIC10_FMR (XMC4_USIC1_CH0_BASE+XMC4_USIC_FMR_OFFSET)
#define XMC4_USIC10_TBUF (XMC4_USIC1_CH0_BASE+XMC4_USIC_TBUF_OFFSET)
/* USIC1 Channel 0 FIFO Registers */
#define XMC4_USIC10_BYP (XMC4_USIC1_CH0_BASE+XMC4_USIC_BYP_OFFSET)
#define XMC4_USIC10_BYPCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_BYPCR_OFFSET)
#define XMC4_USIC10_TBCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TBCTR_OFFSET)
#define XMC4_USIC10_RBCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBCTR_OFFSET)
#define XMC4_USIC10_TRBPTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET)
#define XMC4_USIC10_TRBSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBSR_OFFSET)
#define XMC4_USIC10_TRBSCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET)
#define XMC4_USIC10_OUTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_OUTR_OFFSET)
#define XMC4_USIC10_OUTDR (XMC4_USIC1_CH0_BASE+XMC4_USIC_OUTDR_OFFSET)
#define XMC4_USIC10_IN (XMC4_USIC1_CH0_BASE+XMC4_USIC_IN_OFFSET)
/* USIC1 Channel 1 Registers */
#define XMC4_USCI11_CCFG (XMC4_USIC1_CH1_BASE+XMC4_USIC_CCFG_OFFSET)
#define XMC4_USCI11_KSCFG (XMC4_USIC1_CH1_BASE+XMC4_USIC_KSCFG_OFFSET)
#define XMC4_USCI11_FDR (XMC4_USIC1_CH1_BASE+XMC4_USIC_FDR_OFFSET)
#define XMC4_USCI11_BRG (XMC4_USIC1_CH1_BASE+XMC4_USIC_BRG_OFFSET)
#define XMC4_USCI11_INPR (XMC4_USIC1_CH1_BASE+XMC4_USIC_INPR_OFFSET)
#define XMC4_USCI11_DX0CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX0CR_OFFSET)
#define XMC4_USCI11_DX1CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX1CR_OFFSET)
#define XMC4_USCI11_DX2CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX2CR_OFFSET)
#define XMC4_USCI11_DX3CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX3CR_OFFSET)
#define XMC4_USCI11_DX4CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX4CR_OFFSET)
#define XMC4_USCI11_DX5CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX5CR_OFFSET)
#define XMC4_USCI11_SCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_SCTR_OFFSET)
#define XMC4_USCI11_TCSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TCSR_OFFSET)
#define XMC4_USCI11_PCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PCR_OFFSET)
#define XMC4_USCI11_CCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_CCR_OFFSET)
#define XMC4_USCI11_CMTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_CMTR_OFFSET)
#define XMC4_USCI11_PSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PSR_OFFSET)
#define XMC4_USCI11_PSCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PSCR_OFFSET)
#define XMC4_USCI11_RBUFSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET)
#define XMC4_USCI11_RBUF (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF_OFFSET)
#define XMC4_USCI11_RBUFD (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUFD_OFFSET)
#define XMC4_USCI11_RBUF0 (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF0_OFFSET)
#define XMC4_USCI11_RBUF1 (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF1_OFFSET)
#define XMC4_USCI11_RBUF01SR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET)
#define XMC4_USCI11_FMR (XMC4_USIC1_CH1_BASE+XMC4_USIC_FMR_OFFSET)
#define XMC4_USCI11_TBUF (XMC4_USIC1_CH1_BASE+XMC4_USIC_TBUF_OFFSET)
/* USIC1 Channel 1 FIFO Registers */
#define XMC4_USCI11_BYP (XMC4_USIC1_CH1_BASE+XMC4_USIC_BYP_OFFSET)
#define XMC4_USCI11_BYPCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_BYPCR_OFFSET)
#define XMC4_USCI11_TBCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TBCTR_OFFSET)
#define XMC4_USCI11_RBCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBCTR_OFFSET)
#define XMC4_USCI11_TRBPTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET)
#define XMC4_USCI11_TRBSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBSR_OFFSET)
#define XMC4_USCI11_TRBSCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET)
#define XMC4_USCI11_OUTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_OUTR_OFFSET)
#define XMC4_USCI11_OUTDR (XMC4_USIC1_CH1_BASE+XMC4_USIC_OUTDR_OFFSET)
#define XMC4_USCI11_IN (XMC4_USIC1_CH1_BASE+XMC4_USIC_IN_OFFSET)
/* USCI2 Registers */
/* Kernal Registers */
#define XMC4_USCI2_ID (XMC4_USCI2_BASE+XMC4_USIC_ID_OFFSET)
/* USCI2 Channel 0 Registers */
#define XMC4_USCI20_CCFG (XMC4_USCI2_CH0_BASE+XMC4_USIC_CCFG_OFFSET)
#define XMC4_USCI20_KSCFG (XMC4_USCI2_CH0_BASE+XMC4_USIC_KSCFG_OFFSET)
#define XMC4_USCI20_FDR (XMC4_USCI2_CH0_BASE+XMC4_USIC_FDR_OFFSET)
#define XMC4_USCI20_BRG (XMC4_USCI2_CH0_BASE+XMC4_USIC_BRG_OFFSET)
#define XMC4_USCI20_INPR (XMC4_USCI2_CH0_BASE+XMC4_USIC_INPR_OFFSET)
#define XMC4_USCI20_DX0CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX0CR_OFFSET)
#define XMC4_USCI20_DX1CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX1CR_OFFSET)
#define XMC4_USCI20_DX2CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX2CR_OFFSET)
#define XMC4_USCI20_DX3CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX3CR_OFFSET)
#define XMC4_USCI20_DX4CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX4CR_OFFSET)
#define XMC4_USCI20_DX5CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX5CR_OFFSET)
#define XMC4_USCI20_SCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_SCTR_OFFSET)
#define XMC4_USCI20_TCSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TCSR_OFFSET)
#define XMC4_USCI20_PCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PCR_OFFSET)
#define XMC4_USCI20_CCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_CCR_OFFSET)
#define XMC4_USCI20_CMTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_CMTR_OFFSET)
#define XMC4_USCI20_PSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PSR_OFFSET)
#define XMC4_USCI20_PSCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PSCR_OFFSET)
#define XMC4_USCI20_RBUFSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET)
#define XMC4_USCI20_RBUF (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF_OFFSET)
#define XMC4_USCI20_RBUFD (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUFD_OFFSET)
#define XMC4_USCI20_RBUF0 (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF0_OFFSET)
#define XMC4_USCI20_RBUF1 (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF1_OFFSET)
#define XMC4_USCI20_RBUF01SR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET)
#define XMC4_USCI20_FMR (XMC4_USCI2_CH0_BASE+XMC4_USIC_FMR_OFFSET)
#define XMC4_USCI20_TBUF (XMC4_USCI2_CH0_BASE+XMC4_USIC_TBUF_OFFSET)
/* USCI2 Channel 0 FIFO Registers */
#define XMC4_USCI20_BYP (XMC4_USCI2_CH0_BASE+XMC4_USIC_BYP_OFFSET)
#define XMC4_USCI20_BYPCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_BYPCR_OFFSET)
#define XMC4_USCI20_TBCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TBCTR_OFFSET)
#define XMC4_USCI20_RBCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBCTR_OFFSET)
#define XMC4_USCI20_TRBPTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET)
#define XMC4_USCI20_TRBSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBSR_OFFSET)
#define XMC4_USCI20_TRBSCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET)
#define XMC4_USCI20_OUTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_OUTR_OFFSET)
#define XMC4_USCI20_OUTDR (XMC4_USCI2_CH0_BASE+XMC4_USIC_OUTDR_OFFSET)
#define XMC4_USCI20_IN (XMC4_USCI2_CH0_BASE+XMC4_USIC_IN_OFFSET)
/* USCI2 Channel 1 Registers */
#define XMC4_USCI21_CCFG (XMC4_USCI2_CH1_BASE+XMC4_USIC_CCFG_OFFSET)
#define XMC4_USCI21_KSCFG (XMC4_USCI2_CH1_BASE+XMC4_USIC_KSCFG_OFFSET)
#define XMC4_USCI21_FDR (XMC4_USCI2_CH1_BASE+XMC4_USIC_FDR_OFFSET)
#define XMC4_USCI21_BRG (XMC4_USCI2_CH1_BASE+XMC4_USIC_BRG_OFFSET)
#define XMC4_USCI21_INPR (XMC4_USCI2_CH1_BASE+XMC4_USIC_INPR_OFFSET)
#define XMC4_USCI21_DX0CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX0CR_OFFSET)
#define XMC4_USCI21_DX1CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX1CR_OFFSET)
#define XMC4_USCI21_DX2CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX2CR_OFFSET)
#define XMC4_USCI21_DX3CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX3CR_OFFSET)
#define XMC4_USCI21_DX4CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX4CR_OFFSET)
#define XMC4_USCI21_DX5CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX5CR_OFFSET)
#define XMC4_USCI21_SCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_SCTR_OFFSET)
#define XMC4_USCI21_TCSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TCSR_OFFSET)
#define XMC4_USCI21_PCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PCR_OFFSET)
#define XMC4_USCI21_CCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_CCR_OFFSET)
#define XMC4_USCI21_CMTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_CMTR_OFFSET)
#define XMC4_USCI21_PSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PSR_OFFSET)
#define XMC4_USCI21_PSCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PSCR_OFFSET)
#define XMC4_USCI21_RBUFSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET)
#define XMC4_USCI21_RBUF (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF_OFFSET)
#define XMC4_USCI21_RBUFD (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUFD_OFFSET)
#define XMC4_USCI21_RBUF0 (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF0_OFFSET)
#define XMC4_USCI21_RBUF1 (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF1_OFFSET)
#define XMC4_USCI21_RBUF01SR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET)
#define XMC4_USCI21_FMR (XMC4_USCI2_CH1_BASE+XMC4_USIC_FMR_OFFSET)
#define XMC4_USCI21_TBUF (XMC4_USCI2_CH1_BASE+XMC4_USIC_TBUF_OFFSET)
/* USCI2 Channel 1 FIFO Registers */
#define XMC4_USCI21_BYP (XMC4_USCI2_CH1_BASE+XMC4_USIC_BYP_OFFSET)
#define XMC4_USCI21_BYPCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_BYPCR_OFFSET)
#define XMC4_USCI21_TBCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TBCTR_OFFSET)
#define XMC4_USCI21_RBCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBCTR_OFFSET)
#define XMC4_USCI21_TRBPTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET)
#define XMC4_USCI21_TRBSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBSR_OFFSET)
#define XMC4_USCI21_TRBSCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET)
#define XMC4_USCI21_OUTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_OUTR_OFFSET)
#define XMC4_USCI21_OUTDR (XMC4_USCI2_CH1_BASE+XMC4_USIC_OUTDR_OFFSET)
#define XMC4_USCI21_IN (XMC4_USCI2_CH1_BASE+XMC4_USIC_IN_OFFSET)
/* Register Bit-Field Definitions **************************************************/
/* Kernal Registers */
/* Kernel State Configuration Register */
#define USIC_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */
#define USIC_ID_MOD_REV_MASK (0xff << USIC_ID_MOD_REV_SHIFT)
#define USIC_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */
#define USIC_ID_MOD_TYPE_MASK (0xff << USIC_ID_MOD_REV_SHIFT)
#define USIC_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */
#define USIC_ID_MOD_NUMBER_MASK (0xffff << USIC_ID_MOD_NUMBER_SHIFT)
/* USIC Channel Registers */
/* Channel Configuration Register */
#define USIC_CCFG_
/* Kernel State Configuration Register */
#define USIC_KSCFG_
/* Fractional Divider Register */
#define USIC_FDR_
/* Baud Rate Generator Register */
#define USIC_BRG_
/* Interrupt Node Pointer Register */
#define USIC_INPR_
/* Input Control Register 0 */
#define USIC_DX0CR_
/* Input Control Register 1 */
#define USIC_DX1CR_
/* Input Control Register 2 */
#define USIC_DX2CR_
/* Input Control Register 3 */
#define USIC_DX3CR_
/* Input Control Register 4 */
#define USIC_DX4CR_
/* Input Control Register 5 */
#define USIC_DX5CR_
/* Shift Control Register */
#define USIC_SCTR_
/* Transmit Control/Status Register */
#define USIC_TCSR_
/* Protocol Control Register */
#define USIC_PCR_
/* Channel Control Register */
#define USIC_CCR_
/* Capture Mode Timer Register */
#define USIC_CMTR_
/* Protocol Status Register */
#define USIC_PSR_
/* Protocol Status Clear Register */
#define USIC_PSCR_
/* Receiver Buffer Status Register */
#define USIC_RBUFSR_
/* Receiver Buffer Register */
#define USIC_RBUF_
/* Receiver Buffer Register for Debugger */
#define USIC_RBUFD_
/* Receiver Buffer Register 0 */
#define USIC_RBUF0_
/* Receiver Buffer Register 1 */
#define USIC_RBUF1_
/* Receiver Buffer 01 Status Register */
#define USIC_RBUF01SR_
/* Flag Modification Register */
#define USIC_FMR_
/* Transmit Buffer (32 x 4-bytes) */
#define USIC_TBUF_
/* USIC FIFO Registers */
/* Bypass Data Register */
#define USIC_BYP_
/* Bypass Control Register */
#define USIC_BYPCR_
/* Transmitter Buffer Control Register */
#define USIC_TBCTR_
/* Receiver Buffer Control Register */
#define USIC_RBCTR_
/* Transmit/Receive Buffer Pointer Register */
#define USIC_TRBPTR_
/* Transmit/Receive Buffer Status Register */
#define USIC_TRBSR_
/* Transmit/Receive Buffer Status Clear Register */
#define USIC_TRBSCR_
/* Receiver Buffer Output Register */
#define USIC_OUTR_
/* Receiver Buffer Output Register L for Debugger */
#define USIC_OUTDR_
/* Transmit FIFO Buffer (32 x 4-bytes) */
#define USIC_IN_
#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H */

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_allocateheap.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/userspace.h>
#include <arch/board/board.h>
#include "mpu.h"
#include "up_arch.h"
#include "up_internal.h"
#include "xmc4_mpuinit.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
* User heap. Extends to the end of SRAM.
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = CONFIG_RAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the CONFIG_RAM_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = CONFIG_RAM_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
/* Allow user-mode access to the user heap memory */
xmc4_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* (and protects) the kernel-space heap.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = CONFIG_RAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the CONFIG_RAM_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = CONFIG_RAM_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_clockconfig.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "chip/xmc4_scu.h"
#include "xmc4_clockconfig.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Oscilator reference frequency */
#define FOSCREF (2500000U)
/* Loop delays at different CPU frequencies */
#define DELAY_CNT_50US_50MHZ (2500)
#define DELAY_CNT_150US_50MHZ (7500)
#define DELAY_CNT_50US_48MHZ (2400)
#define DELAY_CNT_50US_72MHZ (3600)
#define DELAY_CNT_50US_96MHZ (4800)
#define DELAY_CNT_50US_120MHZ (6000)
#define DELAY_CNT_50US_144MHZ (7200)
/* PLL settings */
#define SCU_PLLSTAT_OSC_USABLE \
(SCU_PLLSTAT_PLLHV | SCU_PLLSTAT_PLLLV | SCU_PLLSTAT_PLLSP)
#ifdef BOARD_PLL_CLOCKSRC_XTAL
# define VCO ((BOARD_XTAL_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV)
#else /* BOARD_PLL_CLOCKSRC_XTAL */
# define BOARD_PLL_PDIV 2
# define BOARD_PLL_NDIV 24
# define BOARD_PLL_K2DIV 1
# define VCO ((OFI_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV)
#endif /* !BOARD_PLL_CLOCKSRC_XTAL */
#define PLL_K2DIV_24MHZ (VCO / OFI_FREQUENCY)
#define PLL_K2DIV_48MHZ (VCO / 48000000)
#define PLL_K2DIV_72MHZ (VCO / 72000000)
#define PLL_K2DIV_96MHZ (VCO / 96000000)
#define PLL_K2DIV_120MHZ (VCO / 120000000)
#define CLKSET_VALUE (0x00000000)
#define SYSCLKCR_VALUE (0x00010001)
#define CPUCLKCR_VALUE (0x00000000)
#define PBCLKCR_VALUE (0x00000000)
#define CCUCLKCR_VALUE (0x00000000)
#define WDTCLKCR_VALUE (0x00000000)
#define EBUCLKCR_VALUE (0x00000003)
#define USBCLKCR_VALUE (0x00010000)
#define EXTCLKCR_VALUE (0x01200003)
#if ((USBCLKCR_VALUE & SCU_USBCLKCR_USBSEL) == SCU_USBCLKCR_USBSEL_USBPLL)
# define USB_DIV 3
#else
# define USB_DIV 5
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: delay
****************************************************************************/
static void delay(uint32_t cycles)
{
volatile uint32_t i;
for (i = 0; i < cycles ;++i)
{
__asm__ __volatile__ ("nop");
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_clock_configure
*
* Description:
* Called to initialize the XMC4xxx chip. This does whatever setup is
* needed to put the MCU in a usable state. This includes the
* initialization of clocking using the settings in board.h.
*
****************************************************************************/
void xmc4_clock_configure(void)
{
uint32_t regval;
uint32_t bitset;
/* Disable and clear OSC_HP Oscillator Watchdog, System VCO Lock, USB VCO
* Lock, and OSC_ULP Oscillator Watchdog traps.
*/
bitset = SCU_TRAP_SOSCWDGT | SCU_TRAP_SVCOLCKT | SCU_TRAP_UVCOLCKT |
SCU_TRAP_ULPWDGT;
regval = getreg32(XMC4_SCU_TRAPDIS);
regval |= bitset;
putreg32(regval, XMC4_SCU_TRAPDIS);
putreg32(bitset, XMC4_SCU_TRAPCLR);
#ifdef BOARD_FOFI_CALIBRATION
/* Enable factory calibration */
regval = getreg32(XMC4_SCU_PLLCON0);
regval |= SCU_PLLCON0_FOTR;
putreg32(regval, XMC4_SCU_PLLCON0);
#else
/* Automatic calibration uses the fSTDBY */
/* Enable HIB domain */
/* Power up HIB domain if and only if it is currently powered down */
regval = getreg32(XMC4_SCU_PWRSTAT);
if ((regval & SCU_PWR_HIBEN) == 0)
{
regval = getreg32(XMC4_SCU_PWRSET);
regval |= SCU_PWR_HIBEN;
putreg32(regval, XMC4_SCU_PWRSTAT);
/* Wait until HIB domain is enabled */
while((getreg32(XMC4_SCU_PWRSTAT) & SCU_PWR_HIBEN) == 0)
{
}
}
/* Remove the reset only if HIB domain were in a state of reset */
regval = getreg32(XMC4_SCU_RSTSTAT);
if ((regval & SCU_RSTSTAT_HIBRS) != 0)
{
regval = putreg32(SCU_RSTCLR_HIBRS, XMC4_SCU_RSTCLR);
delay(DELAY_CNT_150US_50MHZ);
}
#ifdef BOARD_STDBY_CLOCKSRC_OSCULP
/* Enable OSC_ULP */
regval = getreg32(XMC4_SCU_OSCULCTRL);
if ((regval & SCU_OSCULCTRL_MODE_MASK) != 0)
{
/* Check SCU_MIRRSTS to ensure that no transfer over serial interface
* is pending.
*/
while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_OSCULCTRL) != 0)
{
}
/* Enable OSC_ULP */
regval &= ~SCU_OSCULCTRL_MODE_MASK;
putreg32(regval, XMC4_SCU_OSCULCTRL);
/* Check if the clock is OK using OSCULP Oscillator Watchdog */
while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCR) != 0)
{
}
regval = getreg32(XMC4_SCU_HDCR);
regval |= SCU_HDCR_ULPWDGEN;
putreg32(regval, XMC4_SCU_HDCR)
/* Wait till clock is stable */
do
{
/* Check SCU_MIRRSTS to ensure that no transfer over serial interface
* is pending.
*/
while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCLR) != 0)
{
}
putreg32(SCU_HDCLR_ULPWDG, XMC4_SCU_HDCLR)
delay(DELAY_CNT_50US_50MHZ);
}
while ((getreg32(XMC4_SCU_HDSTAT) & SCU_HDSTAT_ULPWDG) != 0);
}
/* Now OSC_ULP is running and can be used */
while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCR) != 0)
{
}
/* Select OSC_ULP as the clock source for RTC and STDBY */
regval = getreg32(XMC4_SCU_HDCR);
regval |= (SCU_HDCR_RCS_ULP | SCU_HDCR_STDBYSEL_ULP);
putreg32(regval, XMC4_SCU_HDCR)
regval = getreg32(XMC4_SCU_TRAPDIS);
regval &= ~SCU_TRAP_ULPWDGT;
putreg32(regval, XMC4_SCU_TRAPDIS);
#endif /* BOARD_STDBY_CLOCKSRC_OSCULP */
/* Enable automatic calibration of internal fast oscillator */
regval = getreg32(XMC4_SCU_PLLCON0);
regval |= SCU_PLLCON0_AOTREN;
putreg32(regval, XMC4_SCU_PLLCON0);
#endif /* BOARD_FOFI_CALIBRATION */
delay(DELAY_CNT_50US_50MHZ);
#ifdef BOARD_ENABLE_PLL
/* Enable PLL */
regval = getreg32(XMC4_SCU_PLLCON0);
regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD);
putreg32(regval, XMC4_SCU_PLLCON0);
#ifdef BOARD_PLL_CLOCKSRC_XTAL
/* Enable OSC_HP */
if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U)
{
regval = getreg32(XMC4_SCU_OSCHPCTRL);
regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK);
regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT;
putreg32(regval, XMC4_SCU_OSCHPCTRL);
/* Select OSC_HP clock as PLL input */
regval = getreg32(XMC4_SCU_PLLCON2);
regval &= ~SCU_PLLCON2_PINSEL;
putreg32(regval, XMC4_SCU_PLLCON2);
/* Restart OSC Watchdog */
regval = getreg32(XMC4_SCU_PLLCON0);
regval &= ~SCU_PLLCON0_OSCRES;
putreg32(regval, XMC4_SCU_PLLCON0);
/* Wait till OSC_HP output frequency is usable */
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE)
{
}
regval = getreg32(SCU_TRAP_SOSCWDGT);
regval &= ~bitset;
putreg32(regval, SCU_TRAP_SOSCWDGT);
}
#else /* BOARD_PLL_CLOCKSRC_XTAL */
/* Select backup clock as PLL input */
regval = getreg32(XMC4_SCU_PLLCON2);
regval |= SCU_PLLCON2_PINSEL;
putreg32(regval, XMC4_SCU_PLLCON2);
#endif
/* Go to bypass the Main PLL */
regval = getreg32(XMC4_SCU_PLLCON0);
regval |= SCU_PLLCON0_VCOBYP;
putreg32(regval, XMC4_SCU_PLLCON0);
/* Disconnect Oscillator from PLL */
regval |= SCU_PLLCON0_FINDIS;
putreg32(regval, XMC4_SCU_PLLCON0);
/* Setup divider settings for main PLL */
regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) |
SCU_PLLCON1_K2DIV(PLL_K2DIV_24MHZ) |
SCU_PLLCON1_PDIV(BOARD_PLL_PDIV));
putreg32(regval, XMC4_SCU_PLLCON1);
/* Set OSCDISCDIS */
regval = getreg32(XMC4_SCU_PLLCON0);
regval |= SCU_PLLCON0_OSCDISCDIS;
putreg32(regval, XMC4_SCU_PLLCON0);
/* Connect Oscillator to PLL */
regval = getreg32(XMC4_SCU_PLLCON0);
regval &= ~SCU_PLLCON0_FINDIS;
putreg32(regval, XMC4_SCU_PLLCON0);
/* Restart PLL Lock detection */
regval |= SCU_PLLCON0_RESLD;
putreg32(regval, XMC4_SCU_PLLCON0);
/* wait for PLL Lock at 24MHz*/
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOLOCK) == 0)
{
}
/* Disable bypass- put PLL clock back */
regval = getreg32(XMC4_SCU_PLLCON0);
regval &= ~SCU_PLLCON0_VCOBYP;
putreg32(regval, XMC4_SCU_PLLCON0);
/* Wait for normal mode */
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOBYST) != 0)
{
}
regval = getreg32(XMC4_SCU_TRAPDIS);
regval &= ~SCU_TRAP_UVCOLCKT;
putreg32(regval, XMC4_SCU_TRAPDIS);
#endif /* BOARD_ENABLE_PLL */
/* Before scaling to final frequency we need to setup the clock dividers */
putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR);
putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR);
putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR);
putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR);
putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR);
putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR);
putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR);
putreg32(EXTCLKCR_VALUE, XMC4_SCU_EXTCLKCR);
#if BOARD_ENABLE_PLL
/* PLL frequency stepping...*/
/* Reset OSCDISCDIS */
regval = getreg32(XMC4_SCU_PLLCON0);
regval &= ~SCU_PLLCON0_OSCDISCDIS;
putreg32(regval, XMC4_SCU_PLLCON0);
regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) |
SCU_PLLCON1_K2DIV(PLL_K2DIV_48MHZ) |
SCU_PLLCON1_PDIV(BOARD_PLL_PDIV));
putreg32(regval, XMC4_SCU_PLLCON1);
delay(DELAY_CNT_50US_48MHZ);
regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) |
SCU_PLLCON1_K2DIV(PLL_K2DIV_72MHZ) |
SCU_PLLCON1_PDIV(BOARD_PLL_PDIV));
putreg32(regval, XMC4_SCU_PLLCON1);
delay(DELAY_CNT_50US_72MHZ);
regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) |
SCU_PLLCON1_K2DIV(PLL_K2DIV_96MHZ) |
SCU_PLLCON1_PDIV(BOARD_PLL_PDIV));
putreg32(regval, XMC4_SCU_PLLCON1);
delay(DELAY_CNT_50US_96MHZ);
regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) |
SCU_PLLCON1_K2DIV(PLL_K2DIV_120MHZ) |
SCU_PLLCON1_PDIV(BOARD_PLL_PDIV));
putreg32(regval, XMC4_SCU_PLLCON1);
delay(DELAY_CNT_50US_120MHZ);
regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) |
SCU_PLLCON1_K2DIV(BOARD_PLL_K2DIV) |
SCU_PLLCON1_PDIV(BOARD_PLL_PDIV));
putreg32(regval, XMC4_SCU_PLLCON1);
delay(DELAY_CNT_50US_144MHZ);
#endif /* BOARD_ENABLE_PLL */
#ifdef BOARD_ENABLE_USBPLL
/* Enable USB PLL first */
regval = getreg32(XMC4_SCU_USBPLLCON);
regval &= ~(SCU_USBPLLCON_VCOPWD | SCU_USBPLLCON_PLLPWD);
getreg32(regval, XMC4_SCU_USBPLLCON);
/* USB PLL uses as clock input the OSC_HP */
/* check and if not already running enable OSC_HP */
if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U)
{
/* Check if Main PLL is switched on for OSC WDG */
regval = getreg32(XMC4_SCU_PLLCON0);
if ((regval & (SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD)) != 0)
{
/* Enable PLL first */
regval = getreg32(XMC4_SCU_PLLCON0);
regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD);
putreg32(regval, XMC4_SCU_PLLCON0);
}
regval = getreg32(XMC4_SCU_OSCHPCTRL);
regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK);
regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT;
putreg32(regval, XMC4_SCU_OSCHPCTRL);
/* Restart OSC Watchdog */
regval = getreg32(XMC4_SCU_PLLCON0);
regval &= ~SCU_PLLCON0_OSCRES;
putreg32(regval, XMC4_SCU_PLLCON0);
/* Wait till OSC_HP output frequency is usable */
while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE)
{
}
}
/* Setup USB PLL */
/* Go to bypass the USB PLL */
regval = getreg32(XMC4_SCU_USBPLLCON);
regval |= SCU_USBPLLCON_VCOBYP;
putreg32(regval, XMC4_SCU_USBPLLCON);
/* Disconnect Oscillator from USB PLL */
regval |= SCU_USBPLLCON_FINDIS;
putreg32(regval, XMC4_SCU_USBPLLCON);
/* Setup Divider settings for USB PLL */
regval = (SCU_USBPLLCON_NDIV(BOARD_USB_NDIV) | SCU_USBPLLCON_PDIV(BOARD_USB_PDIV));
putreg32(regval, XMC4_SCU_USBPLLCON);
/* Set OSCDISCDIS */
regval |= SCU_USBPLLCON_OSCDISCDIS;
putreg32(regval, XMC4_SCU_USBPLLCON);
/* Connect Oscillator to USB PLL */
regval &= ~SCU_USBPLLCON_FINDIS;
putreg32(regval, XMC4_SCU_USBPLLCON);
/* Restart PLL Lock detection */
regval |= SCU_USBPLLCON_RESLD;
putreg32(regval, XMC4_SCU_USBPLLCON);
/* Wait for PLL Lock */
while ((getreg32(XMC4_SCU_USBPLLSTAT) & SCU_USBPLLSTAT_VCOLOCK) == 0)
{
}
regval = getreg32(XMC4_SCU_TRAPDIS);
regval &= ~SCU_TRAP_UVCOLCKT;
putreg32(regval, XMC4_SCU_TRAPDIS);
#endif
/* Enable selected clocks */
putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET);
}

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/************************************************************************************
* arch/arm/src/xmc4/xmc4_clockconfig.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/************************************************************************************
* Preprocessor Definitions
************************************************************************************/
#define OFI_FREQUENCY 24000000 /* Frequency of internal Backup Clock Source */
#define OSI_FREQUENCY 32768 /* Frequency of internal Slow Clock Source */
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: xmc4_clock_configure
*
* Description:
* Called to initialize the XMC4xxx chip. This does whatever setup is
* needed to put the MCU in a usable state. This includes the
* initialization of clocking using the settings in board.h.
*
****************************************************************************/
void xmc4_clock_configure(void);
/****************************************************************************
* Name: xmc4_get_coreclock
*
* Description:
* Return the current core clock frequency.
*
****************************************************************************/
uint32_t xmc4_get_coreclock(void);
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_clockutils.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "chip/xmc4_scu.h"
#include "xmc4_clockconfig.h"
#include <arch/board/board.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_get_coreclock
*
* Description:
* Return the current core clock frequency (fCPU).
*
****************************************************************************/
uint32_t xmc4_get_coreclock(void)
{
uint32_t pdiv;
uint32_t ndiv;
uint32_t kdiv;
uint32_t sysdiv;
uint32_t regval;
uint32_t temp;
if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0)
{
/* fPLL is clock source for fSYS */
if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0)
{
/* PLL input clock is the backup clock (fOFI) */
temp = OFI_FREQUENCY;
}
else
{
/* PLL input clock is the high performance oscillator (fOSCHP);
* Only board specific logic knows this value.
*/
temp = BOARD_XTAL_FREQUENCY;
}
/* Check if PLL is locked */
regval = getreg32(XMC4_SCU_PLLSTAT);
if ((regval & SCU_PLLSTAT_VCOLOCK) != 0)
{
/* PLL normal mode */
regval = getreg32(XMC4_SCU_PLLCON1);
pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1;
ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1;
kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1;
temp = (temp / (pdiv * kdiv)) * ndiv;
}
else
{
/* PLL prescalar mode */
regval = getreg32(XMC4_SCU_PLLCON1);
kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1;
temp = (temp / kdiv);
}
}
else
{
/* fOFI is clock source for fSYS */
temp = OFI_FREQUENCY;
}
/* Divide by SYSDIV to get fSYS */
regval = getreg32(XMC4_SCU_SYSCLKCR);
sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1;
temp = temp / sysdiv;
/* Check if the fSYS clock is divided by two to produce fCPU clock. */
regval = getreg32(XMC4_SCU_CPUCLKCR);
if ((regval & SCU_CPUCLKCR_CPUDIV) != 0)
{
temp = temp >> 1;
}
return temp;
}

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_clrpend.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
#include "nvic.h"
#include "up_arch.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_clrpend
*
* Description:
* Clear a pending interrupt at the NVIC. This does not seem to be required
* for most interrupts. Don't know why...
*
* I keep it in a separate file so that it will not increase the footprint
* on Kinetis platforms that do not need this function.
*
****************************************************************************/
void xmc4_clrpend(int irq)
{
/* Check for external interrupt */
if (irq >= XMC4_IRQ_FIRST)
{
if (irq < (XMC4_IRQ_FIRST+32))
{
putreg32(1 << (irq - XMC4_IRQ_FIRST), NVIC_IRQ0_31_CLRPEND);
}
else if (irq < (XMC4_IRQ_FIRST+64))
{
putreg32(1 << (irq - XMC4_IRQ_FIRST - 32), NVIC_IRQ32_63_CLRPEND);
}
else if (irq < (XMC4_IRQ_FIRST+96))
{
putreg32(1 << (irq - XMC4_IRQ_FIRST - 64), NVIC_IRQ64_95_CLRPEND);
}
else if (irq < NR_IRQS)
{
putreg32(1 << (irq - XMC4_IRQ_FIRST - 96), NVIC_IRQ96_127_CLRPEND);
}
}
}

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/************************************************************************************
* arch/arm/src/xmc4/xmc4_config.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H
#define __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration *********************************************************************/
/* Make sure that no unsupported UARTs are enabled */
#ifndef CONFIG_XMC4_USIC0
# undef CONFIG_XMC4_USIC0_ISUART
#endif
#ifndef CONFIG_XMC4_USIC1
# undef CONFIG_XMC4_USIC1_ISUART
#endif
#ifndef CONFIG_XMC4_USIC2
# undef CONFIG_XMC4_USIC2_ISUART
#endif
#ifndef CONFIG_XMC4_USIC3
# undef CONFIG_XMC4_USIC3_ISUART
#endif
#ifndef CONFIG_XMC4_USIC4
# undef CONFIG_XMC4_USIC4_ISUART
#endif
#ifndef CONFIG_XMC4_USIC5
# undef CONFIG_XMC4_USIC5_ISUART
#endif
/* Are any UARTs enabled? */
#undef HAVE_UART_DEVICE
#if defined(CONFIG_XMC4_USIC0_ISUART) || defined(CONFIG_XMC4_USIC1_ISUART) || \
defined(CONFIG_XMC4_USIC2_ISUART) || defined(CONFIG_XMC4_USIC3_ISUART) || \
defined(CONFIG_XMC4_USIC3_ISUART) || defined(CONFIG_XMC4_USIC4_ISUART)
# define HAVE_UART_DEVICE 1
#endif
/* Is there a serial console? There should be at most one defined. It could be on
* any UARTn, n=0,1,2,3,4,5
*/
#undef HAVE_UART_CONSOLE
#if defined(CONFIG_CONSOLE_SYSLOG)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
#else
# if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC0_ISUART)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC1_ISUART)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC2_ISUART)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC3_ISUART)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC4_ISUART)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC5_ISUART)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# else
# ifdef CONFIG_DEV_CONSOLE
# warning "No valid CONFIG_[LP]UART[n]_SERIAL_CONSOLE Setting"
# endif
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# endif
#endif
/* Check UART flow control (Not yet supported) */
# undef CONFIG_UART0_FLOWCONTROL
# undef CONFIG_UART1_FLOWCONTROL
# undef CONFIG_UART2_FLOWCONTROL
# undef CONFIG_UART3_FLOWCONTROL
# undef CONFIG_UART4_FLOWCONTROL
# undef CONFIG_UART5_FLOWCONTROL
/* UART Default Interrupt Priorities */
#ifndef CONFIG_XMC4_UART0PRIO
# define CONFIG_XMC4_UART0PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_XMC4_UART1PRIO
# define CONFIG_XMC4_UART1PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_XMC4_UART2PRIO
# define CONFIG_XMC4_UART2PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_XMC4_UART3PRIO
# define CONFIG_XMC4_UART3PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_XMC4_UART4PRIO
# define CONFIG_XMC4_UART4PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_XMC4_UART5PRIO
# define CONFIG_XMC4_UART5PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H */

0
arch/arm/src/xmc4/xmc4_dma.c Normal file
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218
arch/arm/src/xmc4/xmc4_dma.h Normal file
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/****************************************************************************
* arch/arm/src/xmc4/xmc4_dma.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_DMA_H
#define __ARCH_ARM_SRC_XMC4_XMC4_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "chip/xmc4_dma.h"
/****************************************************************************
* Pre-processor Declarations
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
typedef FAR void *DMA_HANDLE;
typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
#ifdef CONFIG_DEBUG_DMA
struct xmc4_dmaglobalregs_s
{
#warning "Missing logic"
/* Global Registers */
};
struct xmc4_dmachanregs_s
{
#warning "Missing logic"
/* Channel Registers */
};
struct xmc4_dmaregs_s
{
/* Global Registers */
struct xmc4_dmaglobalregs_s gbl;
/* Channel Registers */
struct xmc4_dmachanregs_s ch;
};
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: xmc4_dmainitialize
*
* Description:
* Initialize the GPDMA subsystem.
*
* Returned Value:
* None
*
****************************************************************************/
void xmc4_dmainitilaize(void);
/****************************************************************************
* Name: xmc4_dmachannel
*
* Description:
* Allocate a DMA channel. This function sets aside a DMA channel and
* gives the caller exclusive access to the DMA channel.
*
* Returned Value:
* One success, this function returns a non-NULL, void* DMA channel
* handle. NULL is returned on any failure. This function can fail only
* if no DMA channel is available.
*
****************************************************************************/
DMA_HANDLE xmc4_dmachannel(void);
/****************************************************************************
* Name: xmc4_dmafree
*
* Description:
* Release a DMA channel. NOTE: The 'handle' used in this argument must
* NEVER be used again until xmc4_dmachannel() is called again to re-gain
* a valid handle.
*
* Returned Value:
* None
*
****************************************************************************/
void xmc4_dmafree(DMA_HANDLE handle);
/****************************************************************************
* Name: xmc4_dmasetup
*
* Description:
* Configure DMA for one transfer.
*
****************************************************************************/
int xmc4_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
uint32_t srcaddr, uint32_t destaddr, size_t nbytes);
/****************************************************************************
* Name: xmc4_dmastart
*
* Description:
* Start the DMA transfer
*
****************************************************************************/
int xmc4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
/****************************************************************************
* Name: xmc4_dmastop
*
* Description:
* Cancel the DMA. After xmc4_dmastop() is called, the DMA channel is
* reset and xmc4_dmasetup() must be called before xmc4_dmastart() can be
* called again
*
****************************************************************************/
void xmc4_dmastop(DMA_HANDLE handle);
/****************************************************************************
* Name: xmc4_dmasample
*
* Description:
* Sample DMA register contents
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void xmc4_dmasample(DMA_HANDLE handle, struct xmc4_dmaregs_s *regs);
#else
# define xmc4_dmasample(handle,regs)
#endif
/****************************************************************************
* Name: xmc4_dmadump
*
* Description:
* Dump previously sampled DMA register contents
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void xmc4_dmadump(DMA_HANDLE handle, const struct xmc4_dmaregs_s *regs,
const char *msg);
#else
# define xmc4_dmadump(handle,regs,msg)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_DMA_H */

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_gpio.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_arch.h"
#include "up_internal.h"
#include "chip/xmc4_ports.h"
#include "xmc4_gpio.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_gpio_getreg
*
* Description:
* Return the pin number for this pin configuration
*
****************************************************************************/
static inline uint32_t xmc4_gpio_getreg(uintptr_t portbase,
unsigned int offset)
{
return getreg32(portbase + offset);
}
/****************************************************************************
* Name: xmc4_gpio_putreg
*
* Description:
* Return the pin number for this pin configuration
*
****************************************************************************/
static inline void xmc4_gpio_putreg(uintptr_t portbase, unsigned int offset,
uint32_t regval)
{
putreg32(regval, portbase + offset);
}
/****************************************************************************
* Name: xmc4_gpio_port
*
* Description:
* Return the port number for this pin configuration
*
****************************************************************************/
static inline int xmc4_gpio_port(gpioconfig_t pinconfig)
{
return ((pinconfig & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
}
/****************************************************************************
* Name: xmc4_gpio_portbase
*
* Description:
* Return the base address of the port register for this pin configuration.
*
****************************************************************************/
static uintptr_t xmc4_gpio_portbase(gpioconfig_t pinconfig)
{
return XMC4_PORT_BASE(xmc4_gpio_port(pinconfig));
}
/****************************************************************************
* Name: xmc4_gpio_pin
*
* Description:
* Return the pin number for this pin configuration
*
****************************************************************************/
static unsigned int xmc4_gpio_pin(gpioconfig_t pinconfig)
{
return ((pinconfig & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
/****************************************************************************
* Name: xmc4_gpio_pintype
*
* Description:
* Return the pintype for this pin configuration
*
****************************************************************************/
static inline unsigned int xmc4_gpio_pintype(gpioconfig_t pinconfig)
{
return ((pinconfig & GPIO_PINTYPE_MASK) >> GPIO_PINTYPE_SHIFT);
}
/****************************************************************************
* Name: xmc4_gpio_pinctrl
*
* Description:
* Return the pintype for this pin configuration
*
****************************************************************************/
static inline unsigned int xmc4_gpio_pinctrl(gpioconfig_t pinconfig)
{
return ((pinconfig & GPIO_PINCTRL_MASK) >> GPIO_PINCTRL_SHIFT);
}
/****************************************************************************
* Name: xmc4_gpio_padtype
*
* Description:
* Return the padtype for this pin configuration
*
****************************************************************************/
static inline unsigned int xmc4_gpio_padtype(gpioconfig_t pinconfig)
{
return ((pinconfig & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT);
}
/****************************************************************************
* Name: xmc4_gpio_iocr
*
* Description:
* Update the IOCR register
*
****************************************************************************/
static void xmc4_gpio_iocr(uintptr_t portbase, unsigned int pin,
unsigned int value)
{
uint32_t regval;
uint32_t mask;
unsigned int offset;
unsigned int shift;
/* Read the IOCR register */
offset = XMC4_PORT_IOCR_OFFSET(pin);
regval = xmc4_gpio_getreg(portbase, offset);
/* Set the new value for this field */
pin &= 3;
shift = PORT_IOCR0_PC_SHIFT(pin);
mask = PORT_IOCR0_PC_MASK(pin);
regval &= ~mask;
regval |= (uint32_t)value << shift;
xmc4_gpio_putreg(portbase, offset, regval);
}
/****************************************************************************
* Name: xmc4_gpio_hwsel
*
* Description:
* Update the HWSEL register
*
****************************************************************************/
static inline void xmc4_gpio_hwsel(uintptr_t portbase, unsigned int pin,
unsigned int value)
{
uint32_t regval;
uint32_t mask;
unsigned int shift;
/* Read the HWSEL register */
regval = xmc4_gpio_getreg(portbase, XMC4_PORT_HWSEL_OFFSET);
/* Set the new value for this field */
shift = PORT_HWSEL_HW_SHIFT(pin);
mask = PORT_HWSEL_HW_MASK(pin);
regval &= ~mask;
regval |= (uint32_t)value << shift;
xmc4_gpio_putreg(portbase, XMC4_PORT_HWSEL_OFFSET, regval);
}
/****************************************************************************
* Name: xmc4_gpio_pdisc
*
* Description:
* Update the PDISC register
*
****************************************************************************/
static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
bool value)
{
uint32_t regval;
uint32_t mask;
/* Read the PDISC register */
regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PDISC_OFFSET);
/* Set/clear the enable/disable (or analg) value for this field */
mask = PORT_PIN(pin);
if (value)
{
regval |= mask;
}
else
{
regval &= ~mask;
}
xmc4_gpio_putreg(portbase, XMC4_PORT_PDISC_OFFSET, regval);
}
/****************************************************************************
* Name: xmc4_gpio_pps
*
* Description:
* Update the PPS register
*
****************************************************************************/
static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin,
bool value)
{
uint32_t regval;
uint32_t mask;
/* Read the PPS register */
regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PPS_OFFSET);
/* Set/clear the enable/disable (or analg) value for this field */
mask = PORT_PIN(pin);
if (value)
{
regval |= mask;
}
else
{
regval &= ~mask;
}
xmc4_gpio_putreg(portbase, XMC4_PORT_PPS_OFFSET, regval);
}
/****************************************************************************
* Name: xmc4_gpio_pdr
*
* Description:
* Update the IOCR register
*
****************************************************************************/
static void xmc4_gpio_pdr(uintptr_t portbase, unsigned int pin,
unsigned int value)
{
uint32_t regval;
uint32_t mask;
unsigned int offset;
unsigned int shift;
/* Read the PDRregister */
offset = XMC4_PORT_PDR_OFFSET(pin);
regval = xmc4_gpio_getreg(portbase, offset);
/* Set the new value for this field */
pin &= 7;
shift = PORT_PDR0_PD_SHIFT(pin);
mask = PORT_PDR0_PD_MASK(pin);
regval &= ~mask;
regval |= (uint32_t)value << shift;
xmc4_gpio_putreg(portbase, offset, regval);
}
/****************************************************************************
* Name: xmc4_gpio_inverted
*
* Description:
* Check if the input is inverted
*
****************************************************************************/
static inline bool xmc4_gpio_inverted(gpioconfig_t pinconfig)
{
return ((pinconfig & GPIO_INPUT_INVERT) != 0);
}
/****************************************************************************
* Name: xmc4_gpio_opendrain
*
* Description:
* Check if the output is opendram
*
****************************************************************************/
#define xmc4_gpio_opendrain(p) xmc4_gpio_inverted(p)
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_gpio_config
*
* Description:
* Configure a PIN based on bit-encoded description of the pin,
* 'pincconfig'.
*
****************************************************************************/
int xmc4_gpio_config(gpioconfig_t pinconfig)
{
uintptr_t portbase = xmc4_gpio_portbase(pinconfig);
unsigned int pin = xmc4_gpio_pin(pinconfig);
unsigned int value;
irqstate_t flags;
flags = enter_critical_section();
if (GPIO_ISINPUT(pinconfig))
{
/* Get input pin type (IOCR) */
value = xmc4_gpio_pintype(pinconfig);
/* Check if the input is inverted */
if (xmc4_gpio_inverted(pinconfig))
{
value |= IOCR_INPUT_INVERT;
}
}
else
{
/* Force input while we configure */
xmc4_gpio_iocr(portbase, pin, IOCR_INPUT_NOPULL);
/* Set output value before enabling output */
xmc4_gpio_write(pinconfig, ((pinconfig & GPIO_OUTPUT_SET) != 0));
/* Get output pin type (IOCR) */
value = xmc4_gpio_pintype(pinconfig);
/* Get if the output is opendrain */
if (xmc4_gpio_opendrain(pinconfig))
{
value |= IOCR_OUTPUT_OPENDRAIN;
}
}
/* Update the IOCR register to instantiate the pin type */
xmc4_gpio_iocr(portbase, pin, value);
/* Select pin control (HWSEL) */
value = xmc4_gpio_pinctrl(pinconfig);
xmc4_gpio_hwsel(portbase, pin, value);
/* Select drive strength */
value = xmc4_gpio_padtype(pinconfig);
xmc4_gpio_pdr(portbase, pin, value);
/* Enable/enable pad or Analog only (PDISC) */
xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) != 0));
/* Make sure pin is not in power save mode (PDR) */
xmc4_gpio_pdisc(portbase, pin, false);
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: xmc4_gpio_write
*
* Description:
* Write one or zero to the PORT pin selected by 'pinconfig'
*
****************************************************************************/
void xmc4_gpio_write(gpioconfig_t pinconfig, bool value)
{
uintptr_t portbase = xmc4_gpio_portbase(pinconfig);
unsigned int pin = xmc4_gpio_pin(pinconfig);
uint32_t regval;
/* Setup OMR value for this pin:
*
* PRx PSx Function
* 0 0 Bit Pn_OUT.Px is not changed.
* 0 1 Bit Pn_OUT.Px is set.
* 1 0 Bit Pn_OUT.Px is reset.
* 1 1 Bit Pn_OUT.Px is toggled.
*/
if (value)
{
/* PRx==0; PSx==1 -> Set output */
regval = OMR_PS(pin);
}
else
{
/* PRx==1; PSx==0 -> Reset output */
regval = OMR_PR(pin);
}
/* Set/clear the OUTPUT. This is an atomoc operation so no critical
* section is needed.
*/
xmc4_gpio_putreg(portbase, XMC4_PORT_OMR_OFFSET, regval);
}
/****************************************************************************
* Name: xmc4_gpio_read
*
* Description:
* Read one or zero from the PORT pin selected by 'pinconfig'
*
****************************************************************************/
bool xmc4_gpio_read(gpioconfig_t pinconfig)
{
uintptr_t portbase = xmc4_gpio_portbase(pinconfig);
unsigned int pin = xmc4_gpio_pin(pinconfig);
uint32_t regval;
/* Read the OUT register. This is an atomoc operation so no critical
* section is needed.
*/
regval = xmc4_gpio_getreg(portbase, XMC4_PORT_IN_OFFSET);
/* Return in the input state for this pin at the time is was read */
return ((regval & PORT_PIN(pin)) != 0);
}

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_gpio.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip/xmc4_ports.h"
/****************************************************************************
* Preprocessor Definitions
****************************************************************************/
/* 32-bit GIO encoding:
*
* TTTT TMPD DDCC V.... .... .... PPPP BBBB
*/
/* This identifies the GPIO pint type:
*
* TTTT T... .... .... .... .... .... ....
*/
#define GPIO_PINTYPE_SHIFT (27) /* Bits 27-31: Pin type */
#define GPIO_PINTYPE_MASK (31 << GPIO_PINTYPE_SHIFT)
/* See chip/xmc4_ports.h for the IOCR definitions */
/* Direct input */
# define GPIO_INPUT_NOPULL (IOCR_INPUT_NOPULL << GPIO_PINTYPE_SHIFT)
# define GPIO_INPUT_PULLDOWN (IOCR_INPUT_PULLDOWN << GPIO_PINTYPE_SHIFT)
# define GPIO_INPUT_PULLUP (IOCR_INPUT_PULLUP << GPIO_PINTYPE_SHIFT)
# define GPIO_INPUT_CONT (IOCR_INPUT_CONT << GPIO_PINTYPE_SHIFT)
/* Push-pull Output (direct input) */
# define GPIO_OUTPUT (IOCR_OUTPUT << GPIO_PINTYPE_SHIFT)
# define GPIO_OUTPUT_ALT1 (IOCR_OUTPUT_ALT1 << GPIO_PINTYPE_SHIFT)
# define GPIO_OUTPUT_ALT2 (IOCR_OUTPUT_ALT2 << GPIO_PINTYPE_SHIFT)
# define GPIO_OUTPUT_ALT3 (IOCR_OUTPUT_ALT3 << GPIO_PINTYPE_SHIFT)
# define GPIO_OUTPUT_ALT4 (IOCR_OUTPUT_ALT4 << GPIO_PINTYPE_SHIFT)
# define _GPIO_OUTPUT_BIT (16 << GPIO_PINTYPE_SHIFT)
# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0)
# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0)
/* Pin type modifier:
*
* .... .M.. .... .... .... .... .... ....
*/
#define GPIO_INPUT_INVERT (1 << 26) /* Bit 26: Inverted direct input modifier */
#define GPIO_OUTPUT_OPENDRAIN (1 << 26) /* Bit 26: Output drain output modifier */
#define GPIO_OUTPUT_PUSHPULL (0) /* Push-pull output is the default */
/* Disable PAD:
*
* .... ..P. .... ..... .... .... .... ....
*
* For P0-P6, the PDISC register is ready only.
* For P14-P15, the bit setting also selects Analog+Digital or Analog only
*/
#define GPIO_PAD_DISABLE (1 << 25) /* Bit 25: Disable Pad (P7-P9) */
#define GPIO_PAD_ANALOG (1 << 25) /* Bit 25: Analog only (P14-P15) */
/* Pad driver strength:
*
* .... ...D DD.. ..... .... ......... ....
*/
#define GPIO_PADTYPE_SHIFT (22) /* Bits 22-24: Pad driver strength */
#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
/* See chip/xmc4_ports.h for the PDR definitions */
/* Pad class A1: */
# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT)
# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT)
/* Pad class A1+: */
# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT)
# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT)
# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT)
# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT)
/* Pad class A2: */
# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT)
# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT)
# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT)
# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT)
# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT)
/* Pin control:
*
* .... .... ..CC ..... .... .... .... ....
*/
#define GPIO_PINCTRL_SHIFT (20) /* Bits 20-21: Pad driver strength */
#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT)
/* See chip/xmc4_ports.h for the PDR definitions */
# define GPIO_PINCTRL_SOFTWARE (HWSEL_SW << GPIO_PINCTRL_SHIFT)
# define GPIO_PINCTRL_HW0 (HWSEL_HW0 << GPIO_PINCTRL_SHIFT)
# define GPIO_PINCTRL_HW1 (HWSEL_HW1 << GPIO_PINCTRL_SHIFT)
/* If the pin is an GPIO output, then this identifies the initial output value:
*
* .... .... .... V.... .... .... PPPP BBBB
*/
#define GPIO_OUTPUT_SET (1 << 19) /* Bit 19: Initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* This identifies the GPIO port:
*
* .... .... .... .... .... .... PPPP ....
*/
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT)
# define GPIO_PORT6 (6 << GPIO_PORT_SHIFT)
# define GPIO_PORT7 (7 << GPIO_PORT_SHIFT)
# define GPIO_PORT8 (8 << GPIO_PORT_SHIFT)
# define GPIO_PORT9 (9 << GPIO_PORT_SHIFT)
# define GPIO_PORT14 (14 << GPIO_PORT_SHIFT)
# define GPIO_PORT15 (15 << GPIO_PORT_SHIFT)
/* This identifies the bit in the port:
*
* ... ..... .... .... .... .... .... BBBB
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO pin: 0-15 */
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/* This is a type large enought to hold all pin configuration bits. */
typedef uint32_t gpioconfig_t;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_gpio_config
*
* Description:
* Configure a PIN based on bit-encoded description of the pin,
* 'pincconfig'.
*
****************************************************************************/
int xmc4_gpio_config(gpioconfig_t pinconfig);
/****************************************************************************
* Name: xmc4_gpio_write
*
* Description:
* Write one or zero to the PORT pin selected by 'pinconfig'
*
****************************************************************************/
void xmc4_gpio_write(gpioconfig_t pinconfig, bool value);
/****************************************************************************
* Name: xmc4_gpio_read
*
* Description:
* Read one or zero from the PORT pin selected by 'pinconfig'
*
****************************************************************************/
bool xmc4_gpio_read(gpioconfig_t pinconfig);

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arch/arm/src/xmc4/xmc4_i2c.c Normal file
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/****************************************************************************
* arch/arm/src/xmc4/xmc4_i2c.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_I2C_H
#define __ARCH_ARM_SRC_XMC4_XMC4_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "chip/xmc4_i2c.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: xmc4_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameter:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on succcess; a NULL on failure
*
****************************************************************************/
FAR struct i2c_master_s *xmc4_i2cbus_initialize(int port);
/****************************************************************************
* Name: xmc4_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameter:
* Device structure as returned by the lpc43_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int xmc4_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_I2C_H */

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_idle.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Sleep until an interrupt occurs to save power */
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
}

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_irq.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/xmc4/chip.h>
#include "nvic.h"
#include "ram_vectors.h"
#include "up_arch.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
* the corresponding CLEAR ENABLE register.
*/
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_dump_nvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void xmc4_dump_nvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#if NR_VECTORS > 111
irqinfo(" %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
#endif
leave_critical_section(flags);
}
#else
# define xmc4_dump_nvic(msg, irq)
#endif
/****************************************************************************
* Name: xmc4_nmi, xmc4_busfault, xmc4_usagefault, xmc4_pendsv,
* xmc4_dbgmonitor, xmc4_pendsv, xmc4_reserved
*
* Description:
* Handlers for various execptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int xmc4_nmi(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int xmc4_busfault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Bus fault recived\n");
PANIC();
return 0;
}
static int xmc4_usagefault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
}
static int xmc4_pendsv(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int xmc4_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
static int xmc4_reserved(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: xmc4_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_USEBASEPRI
static inline void xmc4_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
#endif
/****************************************************************************
* Name: xmc4_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int xmc4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
DEBUGASSERT(irq >= XMC4_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= XMC4_IRQ_FIRST)
{
if (irq < (XMC4_IRQ_FIRST+32))
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << (irq - XMC4_IRQ_FIRST);
}
else if (irq < (XMC4_IRQ_FIRST+64))
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (irq - XMC4_IRQ_FIRST - 32);
}
else if (irq < (XMC4_IRQ_FIRST+96))
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (irq - XMC4_IRQ_FIRST - 64);
}
else if (irq < NR_IRQS)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (irq - XMC4_IRQ_FIRST - 96);
}
else
{
return ERROR; /* Invalid irq */
}
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == XMC4_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == XMC4_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == XMC4_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == XMC4_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
uintptr_t regaddr;
int nintlines;
int i;
/* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
* lines that the NVIC supports, defined in groups of 32. That is,
* the total number of interrupt lines is up to (32*(INTLINESNUM+1)).
*
* 0 -> 32 interrupt lines, 1 enable register, 8 priority registers
* 1 -> 64 " " " ", 2 enable registers, 16 priority registers
* 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers
* ...
*/
nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1;
/* Disable all interrupts. There are nintlines interrupt enable
* registers.
*/
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE;
i > 0;
i--, regaddr += 4)
{
putreg32(0, regaddr);
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
up_ramvec_initialize();
#endif
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* Now set all of the interrupt lines to the default priority. There are
* nintlines * 8 priority registers.
*/
for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY;
i > 0;
i--, regaddr += 4)
{
putreg32(DEFPRIORITY32, regaddr);
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(XMC4_IRQ_SVCALL, up_svcall, NULL);
irq_attach(XMC4_IRQ_HARDFAULT, up_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(XMC4_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
xmc4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_ARM_MPU
irq_attach(XMC4_IRQ_MEMFAULT, up_memfault, NULL);
up_enable_irq(XMC4_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(XMC4_IRQ_NMI, xmc4_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(XMC4_IRQ_MEMFAULT, up_memfault, NULL);
#endif
irq_attach(XMC4_IRQ_BUSFAULT, xmc4_busfault, NULL);
irq_attach(XMC4_IRQ_USAGEFAULT, xmc4_usagefault, NULL);
irq_attach(XMC4_IRQ_PENDSV, xmc4_pendsv, NULL);
irq_attach(XMC4_IRQ_DBGMONITOR, xmc4_dbgmonitor, NULL);
irq_attach(XMC4_IRQ_RESERVED, xmc4_reserved, NULL);
#endif
xmc4_dump_nvic("initial", NR_IRQS);
/* Initialize logic to support a second level of interrupt decoding for
* configured pin interrupts.
*/
#ifdef CONFIG_XMC4_GPIOIRQ
xmc4_gpioirq_initialize();
#endif
/* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (xmc4_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= XMC4_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
xmc4_dump_nvic("disable", irq);
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (xmc4_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= XMC4_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
xmc4_dump_nvic("enable", irq);
}
/****************************************************************************
* Name: up_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void up_ack_irq(int irq)
{
#if 0 /* Does not appear to be necessary in most cases */
xmc4_clrpend(irq);
#endif
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= XMC4_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < XMC4_IRQ_FIRST)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= XMC4_IRQ_FIRST;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
xmc4_dump_nvic("prioritize", irq);
return OK;
}
#endif

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_lowputc.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "up_internal.h"
#include "up_arch.h"
#include "xmc4_config.h"
#include "chip/xmc4_usic.h"
#include "chip/xmc4_pinmux.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select UART parameters for the selected console */
#if defined(HAVE_UART_CONSOLE)
# if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define CONSOLE_BASE XMC4_UART0_BASE
# define CONSOLE_FREQ BOARD_CORECLK_FREQ
# define CONSOLE_BAUD CONFIG_UART0_BAUD
# define CONSOLE_BITS CONFIG_UART0_BITS
# define CONSOLE_2STOP CONFIG_UART0_2STOP
# define CONSOLE_PARITY CONFIG_UART0_PARITY
# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define CONSOLE_BASE XMC4_UART1_BASE
# define CONSOLE_FREQ BOARD_CORECLK_FREQ
# define CONSOLE_BAUD CONFIG_UART1_BAUD
# define CONSOLE_BITS CONFIG_UART1_BITS
# define CONSOLE_2STOP CONFIG_UART1_2STOP
# define CONSOLE_PARITY CONFIG_UART1_PARITY
# elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define CONSOLE_BASE XMC4_UART2_BASE
# define CONSOLE_FREQ BOARD_BUS_FREQ
# define CONSOLE_BAUD CONFIG_UART2_BAUD
# define CONSOLE_BITS CONFIG_UART2_BITS
# define CONSOLE_2STOP CONFIG_UART2_2STOP
# define CONSOLE_PARITY CONFIG_UART2_PARITY
# elif defined(CONFIG_UART3_SERIAL_CONSOLE)
# define CONSOLE_BASE XMC4_UART3_BASE
# define CONSOLE_FREQ BOARD_BUS_FREQ
# define CONSOLE_BAUD CONFIG_UART3_BAUD
# define CONSOLE_BITS CONFIG_UART3_BITS
# define CONSOLE_2STOP CONFIG_UART3_2STOP
# define CONSOLE_PARITY CONFIG_UART3_PARITY
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define CONSOLE_BASE XMC4_UART4_BASE
# define CONSOLE_FREQ BOARD_BUS_FREQ
# define CONSOLE_BAUD CONFIG_UART4_BAUD
# define CONSOLE_BITS CONFIG_UART4_BITS
# define CONSOLE_2STOP CONFIG_UART4_2STOP
# define CONSOLE_PARITY CONFIG_UART4_PARITY
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define CONSOLE_BASE XMC4_UART5_BASE
# define CONSOLE_FREQ BOARD_BUS_FREQ
# define CONSOLE_BAUD CONFIG_UART5_BAUD
# define CONSOLE_BITS CONFIG_UART5_BITS
# define CONSOLE_2STOP CONFIG_UART5_2STOP
# define CONSOLE_PARITY CONFIG_UART5_PARITY
# elif defined(HAVE_UART_CONSOLE)
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
# endif
#endif /* HAVE_UART_CONSOLE */
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void up_lowputc(char ch)
{
#ifdef HAVE_UART_CONSOLE
/* Wait until the transmit data register is "empty" (TDRE). This state
* depends on the TX watermark setting and may not mean that the transmit
* buffer is truly empty. It just means that we can now add another
* character to the transmit buffer without exceeding the watermark.
*
* NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs
* (1-deep). There appears to be no way to know when the FIFO is not
* full (other than reading the FIFO length and comparing the FIFO count).
* Hence, the FIFOs are not used in this implementation and, as a result
* TDRE indeed mean that the single output buffer is available.
*
* Performance on UART0 could be improved by enabling the FIFO and by
* redesigning all of the FIFO status logic.
*/
#warning Missing logic
/* Then write the character to the UART data register */
#warning Missing logic
}
/****************************************************************************
* Name: xmc4_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void xmc4_lowsetup(void)
{
uint32_t regval;
/* Enable peripheral clocking for all enabled UARTs. */
#wanring Missing logic
/* Configure UART pins for the all enabled UARTs */
/* Configure the console (only) now. Other UARTs will be configured
* when the serial driver is opened.
*/
xmc4_uart_configure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, \
CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP);
#endif /* HAVE_UART_DEVICE */
}
/****************************************************************************
* Name: xmc4_uart_reset
*
* Description:
* Reset a UART.
*
****************************************************************************/
#ifdef HAVE_UART_DEVICE
void xmc4_uart_reset(uintptr_t uart_base)
{
uint8_t regval;
/* Just disable the transmitter and receiver */
#warning Missing logic
}
#endif
/****************************************************************************
* Name: xmc4_uart_configure
*
* Description:
* Configure a UART as a RS-232 UART.
*
****************************************************************************/
#ifdef HAVE_UART_DEVICE
void xmc4_uart_configure(uintptr_t uart_base, uint32_t baud,
uint32_t clock, unsigned int parity,
unsigned int nbits, unsigned int stop2)
{
/* Disable the transmitter and receiver throughout the reconfiguration */
#warning Missing logic
/* Configure number of bits, stop bits and parity */
#warning Missing logic
/* Check for odd parity */
#warning Missing logic
/* Check for even parity */
#warning Missing logic
/* Check for 9-bit operation */
#warning Missing logic
/* Calculate baud settings (truncating) */
#warning Missing logic
/* Configure FIFOs */
#warning Missing logic
/* Enable RX and TX FIFOs */
#warning Missing logic
/* Now we can (re-)enable the transmitter and receiver */
#warning Missing logic
}
#endif

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_mpuinit.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "xmc4_mpuinit.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MAX
# define MAX(a,b) a > b ? a : b
#endif
#ifndef MIN
# define MIN(a,b) a < b ? a : b
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
* resources.
*
****************************************************************************/
void xmc4_mpuinitialize(void)
{
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
dataend >= datastart);
/* Show MPU information */
mpu_showtype();
/* Configure user flash and SRAM space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
mpu_control(true, false, true);
}
/****************************************************************************
* Name: xmc4_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
void xmc4_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */

78
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/************************************************************************************
* arch/arm/src/xmc4/xmc4_mpuinit.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H
#define __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: xmc4_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted MCU
* resources.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void xmc4_mpuinitialize(void);
#else
# define xmc4_mpuinitialize()
#endif
/****************************************************************************
* Name: xmc4_mpu_uheap
*
* Description:
* Map the user heap region.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void xmc4_mpu_uheap(uintptr_t start, size_t size);
#else
# define xmc4_mpu_uheap(start,size)
#endif
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H */

0
arch/arm/src/xmc4/xmc4_pwm.c Normal file
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arch/arm/src/xmc4/xmc4_pwm.h Normal file
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/************************************************************************************
* arch/arm/src/xmc4/xmc4_pwm.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_PWM_H
#define __ARCH_ARM_SRC_XMC4_XMC4_PWM_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: xmc4_pwm_initialize
*
* Description:
* Initialize one timer for use with the upper_level PWM driver.
*
* Input Parameters:
* timer - A number identifying the timer use.
*
* Returned Value:
* On success, a pointer to the kinetis lower half PWM driver is returned.
* NULL is returned on any failure.
*
************************************************************************************/
FAR struct pwm_lowerhalf_s *xmc4_pwm_initialize(int timer);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_XMC4_FTMx_PWM */
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_PWM_H */

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_spi.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_SPI_H
#define __ARCH_ARM_SRC_XMC4_XMC4_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip/xmc4_spi.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Data
************************************************************************************/
struct spi_dev_s;
enum spi_dev_e;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/************************************************************************************
* Name: xmc4_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
*
* Input Parameter:
* bus number (for hardware that has mutiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on succcess; a NULL on failure
*
************************************************************************************/
FAR struct spi_dev_s *xmc4_spibus_initialize(int bus);
/************************************************************************************
* Name: xmc4_spi[n]select, xmc4_spi[n]status, and xmc4_spi[n]cmddata
*
* Description:
* These external functions must be provided by board-specific logic. They are
* implementations of the select, status, and cmddata methods of the SPI interface
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
* including xmc4_spibus_initialize()) are provided by common Kinetis logic. To use
* this common SPI logic on your board:
*
* 1. Provide logic in xmc4_board_initialize() to configure SPI chip select
* pins.
* 2. Provide xmc4_spi[n]select() and xmc4_spi[n]status() functions
* in your board-specific logic. These functions will perform chip selection
* and status operations using GPIOs in the way your board is configured.
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
* xmc4_spi[n]cmddata() functions in your board-specific logic. These
* functions will perform cmd/data selection operations using GPIOs in the way
* your board is configured.
* 3. Add a call to xmc4_spibus_initialize() in your low level application
* initialization logic
* 4. The handle returned by xmc4_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
************************************************************************************/
#ifdef CONFIG_XMC4_SPI0
void xmc4_spi0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t xmc4_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int xmc4_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
#ifdef CONFIG_XMC4_SPI1
void xmc4_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t xmc4_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int xmc4_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
#ifdef CONFIG_XMC4_SPI2
void xmc4_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t xmc4_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int xmc4_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif
/****************************************************************************
* Name: ssp_flush
*
* Description:
* Flush and discard any words left in the RX fifo. This can be called
* from spi[n]select after a device is deselected (if you worry about such
* things).
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* None
*
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#if defined(CONFIG_XMC4_SPI0) || defined(CONFIG_XMC4_SPI1) || defined(CONFIG_XMC4_SPI2)
struct spi_dev_s;
void spi_flush(FAR struct spi_dev_s *dev);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_SPI_H */

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_start.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "up_arch.h"
#include "up_internal.h"
#include "chip/xmc4_flash.h"
#include "xmc4_userspace.h"
#include "xmc4_start.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
#endif
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void xmc4_fpu_config(void);
#endif
static inline void xmc4_unaligned(void);
static inline void xmc4_flash_waitstates(void);
#ifdef CONFIG_STACK_COLORATION
static void go_os_start(void *pv, unsigned int nbytes)
__attribute__ ((naked, no_instrument_function, noreturn));
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Memory Map ***************************************************************/
/*
* 0x0000:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x07ff:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x1fff:0000 - Start of internal SRAM and start of .data (_sdata)
* - End of .data (_edata) and start of .bss (_sbss)
* - End of .bss (_ebss) and bottom of idle stack
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
* start of heap. NOTE that the ARM uses a decrement before
* store stack so that the correct initial value is the end of
* the stack + 4;
* 0x2002:ffff - End of internal SRAM and end of heap (a
*/
#define IDLE_STACK ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
#define HEAP_BASE ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
#if defined(CONFIG_ARMV7M_CMNVECTOR)
const uintptr_t g_idle_topstack = HEAP_BASE;
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
#ifdef CONFIG_ARMV7M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
void __start(void) __attribute__ ((no_instrument_function));
#endif
/****************************************************************************
* Name: xmc4_fpu_config
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU)
static inline void xmc4_fpu_config(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= (1 << 2);
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
putreg32(regval, NVIC_CPACR);
}
#else
static inline void xmc4_fpu_config(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~(1 << 2);
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~((1 << 31) | (1 << 30));
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2*10)) | (3 << (2*11)));
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define xmc4_fpu_config()
#endif
/****************************************************************************
* Name: xmc4_unaligned
*
* Description:
* Enable unaligned memory access by setting SCB_CCR.UNALIGN_TRP = 0
*
****************************************************************************/
static inline void xmc4_unaligned(void)
{
uint32_t regval;
regval = getreg32(NVIC_CFGCON);
regval &= ~NVIC_CFGCON_UNALIGNTRP;
putreg32(regval, NVIC_CFGCON);
}
/****************************************************************************
* Name: xmc4_flash_waitstates
*
* Description:
* Enable unaligned memory access by setting SCB_CCR.UNALIGN_TRP = 0
*
****************************************************************************/
static inline void xmc4_flash_waitstates(void)
{
uint32_t regval;
regval = getreg32(XMC4_FLASH_FCON);
regval &= ~FLASH_FCON_WSPFLASH_MASK;
regval |= FLASH_FCON_WSPFLASH(BOARD_FLASH_WS);
putreg32(regval, XMC4_FLASH_FCON);
}
/****************************************************************************
* Name: go_os_start
*
* Description:
* Set the IDLE stack to the
*
****************************************************************************/
#ifdef CONFIG_STACK_COLORATION
static void go_os_start(void *pv, unsigned int nbytes)
{
/* Set the IDLE stack to the stack coloration value then jump to
* os_start(). We take extreme care here because were currently
* executing on this stack.
*
* We want to avoid sneak stack access generated by the compiler.
*/
__asm__ __volatile__
(
"\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */
"\tbeq 2f\n" /* (should not happen) */
"\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */
"\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */
"\tmovt r2, #0xdead\n"
"1:\n" /* Top of the loop */
"\tsub r1, r1, #1\n" /* R1 nwords-- */
"\tcmp r1, #0\n" /* Check (nwords == 0) */
"\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */
"\tbne 1b\n" /* Bottom of the loop */
"2:\n"
"\tmov r14, #0\n" /* LR = return address (none) */
"\tb os_start\n" /* Branch to os_start */
);
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: _start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
const uint32_t *src;
uint32_t *dest;
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
#endif
/* Disable the watchdog timer */
xmc4_wddisable();
/* Enable unaligned memory access */
xmc4_unaligned();
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = &_sbss; dest < &_ebss; )
{
*dest++ = 0;
}
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
{
*dest++ = *src++;
}
/* Copy any necessary code sections from FLASH to RAM. The correct
* destination in SRAM is given by _sramfuncs and _eramfuncs. The
* temporary location is in flash after the data initialization code
* at _framfuncs
*/
#ifdef CONFIG_ARCH_RAMFUNCS
for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; )
{
*dest++ = *src++;
}
#endif
/* Set FLASH wait states prior to the configuration of clocking */
xmc4_flash_waitstates();
/* Perform clock and Kinetis module initialization (This depends on
* RAM functions having been copied to RAM).
*/
xmc4_clock_configure();
/* Configure the uart and perform early serial initialization so that we
* can get debug output as soon as possible (This depends on clock
* configuration).
*/
xmc4_fpu_config();
xmc4_lowsetup();
#ifdef USE_EARLYSERIALINIT
xmc4_earlyserialinit();
#endif
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
xmc4_userspace();
#endif
/* Initialize other on-board resources */
xmc4_board_initialize();
/* Then start NuttX */
os_start();
/* Shouldn't get here */
for (; ; );
}

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/************************************************************************************
* arch/arm/src/xmc4/xmc4_start.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: xmc4_board_initialize
*
* Description:
* All XMC4xxx architectures must provide the following entry point. This entry
* point is called early in the initialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
void xmc4_board_initialize(void);
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */

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/****************************************************************************
* arch/arm/src/xmc4/xmc4_timerisr.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "up_internal.h"
#include "up_arch.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* The Clock Source: The System Tick Timer's clock source is always the core
* clock
*/
#define SYSTICK_RELOAD ((BOARD_CORECLK_FREQ / CLK_TCK) - 1)
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
#if SYSTICK_RELOAD > 0x00ffffff
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: xmc4_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int xmc4_timerisr(int irq, uint32_t *regs, FAR void *arg)
{
/* Process timer interrupt */
sched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: arm_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void arm_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Note that is should not be neccesary to set the SYSTICK clock source:
* "The CLKSOURCE bit in SysTick Control and Status register is always set
* to select the core clock."
*/
#if 0
regval = getreg32(NVIC_SYSTICK_CTRL);
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
putreg32(regval, NVIC_SYSTICK_CTRL);
#endif
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
(void)irq_attach(XMC4_IRQ_SYSTICK, (xcpt_t)xmc4_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE),
NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(XMC4_IRQ_SYSTICK);
}

107
arch/arm/src/xmc4/xmc4_userspace.c Normal file
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@ -0,0 +1,107 @@
/****************************************************************************
* arch/arm/src/xmc4/xmc4_userspace.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "xmc4_mpuinit.h"
#include "xmc4_userspace.h"
#ifdef CONFIG_BUILD_PROTECTED
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
****************************************************************************/
void xmc4_userspace(void)
{
uint8_t *src;
uint8_t *dest;
uint8_t *end;
/* Clear all of user-space .bss */
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
dest = (uint8_t *)USERSPACE->us_bssstart;
end = (uint8_t *)USERSPACE->us_bssend;
while (dest != end)
{
*dest++ = 0;
}
/* Initialize all of user-space .data */
DEBUGASSERT(USERSPACE->us_datasource != 0 &&
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
USERSPACE->us_datastart <= USERSPACE->us_dataend);
src = (uint8_t *)USERSPACE->us_datasource;
dest = (uint8_t *)USERSPACE->us_datastart;
end = (uint8_t *)USERSPACE->us_dataend;
while (dest != end)
{
*dest++ = *src++;
}
/* Configure the MPU to permit user-space access to its FLASH and RAM */
xmc4_mpuinitialize();
}
#endif /* CONFIG_BUILD_PROTECTED */

64
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@ -0,0 +1,64 @@
/************************************************************************************
* arch/arm/src/xmc4/xmc4_userspace.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H
#define __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: xmc4_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void xmc4_userspace(void);
#endif
#endif /* __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H */

13
configs/Kconfig
View File

@ -1270,6 +1270,15 @@ config ARCH_BOARD_VIEWTOOL_STM32F107
board may be fitted with either: (1) STM32F107VCT6 or (2) STM32F103VCT6.
See http://www.viewtool.com/ for further information.
config ARCH_BOARD_XMC4500RELAX
bool "Infineon XMC4500 Relax"
depends on ARCH_CHIP_XMC4500
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
Infineon XMC4000 Relax Lite v1
config ARCH_BOARD_XTRS
bool "XTRS TRS80 Model 3 emulation"
depends on ARCH_CHIP_Z80
@ -1531,6 +1540,7 @@ config ARCH_BOARD
default "ubw32" if ARCH_BOARD_UBW32
default "us7032evb1" if ARCH_BOARD_US7032EVB1
default "viewtool-stm32f107" if ARCH_BOARD_VIEWTOOL_STM32F107
default "xmc4500-relax" if ARCH_BOARD_XMC4500RELAX
default "xtrs" if ARCH_BOARD_XTRS
default "z16f2800100zcog" if ARCH_BOARD_Z16F2800100ZCOG
default "z80sim" if ARCH_BOARD_Z80SIM
@ -1936,6 +1946,9 @@ endif
if ARCH_BOARD_VIEWTOOL_STM32F107
source "configs/viewtool-stm32f107/Kconfig"
endif
if ARCH_BOARD_XMC4500RELAX
source "configs/xmc4500-relax/Kconfig"
endif
if ARCH_BOARD_XTRS
source "configs/xtrs/Kconfig"
endif

3
configs/README.txt
View File

@ -763,6 +763,9 @@ configs/viewtool-stm32f107
board may be fitted with either: (1) STM32F107VCT6 or (2) STM32F103VCT6.
See http://www.viewtool.com/ for further information.
config/xmc4500-relax
Infineon XMC4000 Relax Lite v1
configs/xtrs
TRS80 Model 3. This port uses a vintage computer based on the Z80.
An emulator for this computer is available to run TRS80 programs on a

4
configs/xmc4500-relax/Kconfig Normal file
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@ -0,0 +1,4 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

220
configs/xmc4500-relax/include/board.h Normal file
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@ -0,0 +1,220 @@
/************************************************************************************
* configs/xmc4500-relax/include/board.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H
#define __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Clocking *************************************************************************/
/* Default clock initialization
* fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz
* => fPB = 144MHz
* => fCCU = 144MHz
* => fETH = 72MHz
* => fUSB = 48MHz
* => fEBU = 72MHz
*
* fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected
*
* fOFI = 24MHz => fWDT = 24MHz
*/
#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */
/* On-board crystals
*
* NOTE: Only the XMC4500 Relax Kit-V1 provides the 32.768KHz RTC crystal. It
* is not available on XMC4500 Relax Lite Kit-V1.
*/
#define BOARD_XTAL_FREQUENCY 12000000 /* 12MHz XTAL */
#undef BOARD_RTC_XTAL_FRQUENCY /* 32.768KHz RTC XTAL not available */
/* Select the external crystal as the PLL clock source */
#define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */
#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */
/* PLL Configuration:
*
* fPLL = (fPLLSRC / (pdiv * k2div) * ndiv
*
* fPLL = (12000000 / (2 * 1)) * 48
* = 288MHz
*/
#define BOARD_ENABLE_PLL 1
#define BOARD_PLL_PDIV 2
#define BOARD_PLL_NDIV 48
#define BOARD_PLL_K2DIV 1
#define BOARD_PLL_FREQUENCY 288000000
/* System frequency is divided down from PLL output */
#define BOARD_SYSDIV 1 /* PLL Output divider to get fSYS */
#define BOARD_SYS_FREQUENCY 288000000
/* CPU frequency may be divided down from system frequency */
#define BOARD_CPUDIV_ENABLE 1 /* Enable PLL dive by 2 for fCPU */
#define BOARD_CPU_FREQUENCY 144000000
/* Standby clock source selection
*
* BOARD_STDBY_CLOCKSRC_OSI - Internal slow oscillator (32768Hz)
* BOARD_STDBY_CLOCKSRC_OSCULP - External 32.768KHz crystal
*/
#define BOARD_STDBY_CLOCKSRC_OSI 1
#undef BOARD_STDBY_CLOCKSRC_OSCULP
/* USB PLL settings.
*
* fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz
*
* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and
* fUSBPLLVCO <= 520 MHz
*/
#undef BOARD_ENABLE_USBPLL
#define BOARD_USB_PDIV 2
#define BOARD_USB_NDIV 64
/* FLASH wait states */
#define BOARD_FLASH_WS 5
/* LED definitions ******************************************************************/
/* The XMC4500 Relax Lite v1 board has two LEDs:
*
* LED1 P1.1 High output illuminates
* LED2 P1.0 High output illuminates
*
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
* way. The following definitions are used to access individual LEDs.
*/
/* LED index values for use with board_userled() */
#define BOARD_LED0 0
#define BOARD_LED1 1
#define BOARD_NLEDS 2
/* LED bits for use with board_userled_all() */
#define BOARD_LED0_BIT (1 << BOARD_LED0)
#define BOARD_LED1_BIT (1 << BOARD_LED1)
/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
* defined. In that case, the usage by the board port is defined in
* include/board.h and src/sam_autoleds.c. The LEDs are used to encode
* OS-related events as follows:
*
* SYMBOL Meaning LED state
* LED2 LED1
* --------------------- -------------------------- ------ ------ */
#define LED_STARTED 0 /* NuttX has been started OFF OFF */
#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */
#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */
#define LED_STACKCREATED 1 /* Idle stack created ON OFF */
#define LED_INIRQ 2 /* In an interrupt No change */
#define LED_SIGNAL 2 /* In a signal handler No change */
#define LED_ASSERTION 2 /* An assertion failed No change */
#define LED_PANIC 3 /* The system has crashed N/C Blinking */
#undef LED_IDLE /* MCU is is sleep mode Not used */
/* Thus if LED0 is statically on, NuttX has successfully booted and is,
* apparently, running normally. If LED1 is flashing at approximately
* 2Hz, then a fatal error has been detected and the system has halted.
*
* NOTE: That LED0 is not used after completion of booting and may
* be used by other board-specific logic.
*/
/* Button definitions ***************************************************************/
/* The XMC4500 Relax Lite v1 board has two buttons:
*
* BUTTON1 P1.14 Low input sensed when button pressed
* BUTTON2 P1.15 Low input sensed when button pressed
*/
#define BUTTON_0 0
#define BUTTON_1 1
#define NUM_BUTTONS 2
#define BUTTON_0_BIT (1 << BUTTON_0)
#define BUTTON_1_BIT (1 << BUTTON_1)
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H */

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@ -0,0 +1,128 @@
############################################################################
# configs/xmc4500-relax/nsh/Make.defs
#
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
ifeq ($(CONFIG_ARMV7M_DTCM),y)
LDSCRIPT = flash-dtcm.ld
else
LDSCRIPT = flash-sram.ld
endif
ifeq ($(WINTOOL),y)
# Windows-native toolchains
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
else
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
endif
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
AR = $(CROSSDEV)ar rcs
NM = $(CROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION)
endif
ARCHCFLAGS = -fno-builtin
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -fno-strict-aliasing
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHDEFINES =
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
# Loadable module definitions
CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
LDMODULEFLAGS = -r -e module_initialize
ifeq ($(WINTOOL),y)
LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libc/modlib/gnu-elf.ld}"
else
LDMODULEFLAGS += -T $(TOPDIR)/libc/modlib/gnu-elf.ld
endif
ASMEXT = .S
OBJEXT = .o
LIBEXT = .a
EXEEXT =
ifneq ($(CROSSDEV),arm-nuttx-elf-)
LDFLAGS += -nostartfiles -nodefaultlibs
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =

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77
configs/xmc4500-relax/nsh/setenv.sh Normal file
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@ -0,0 +1,77 @@
#!/bin/bash
# configs/xmc4500-relax/nsh/Make.defs
#
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
if [ "$_" = "$0" ] ; then
echo "You must source this script, not run it!" 1>&2
exit 1
fi
WD=`pwd`
if [ ! -x "setenv.sh" ]; then
echo "This script must be executed from the top-level NuttX build directory"
exit 1
fi
if [ -z "${PATH_ORIG}" ]; then
export PATH_ORIG="${PATH}"
fi
# This is the Cygwin path to the location where I installed the Atmel GCC
# toolchain under Windows. You will also have to edit this if you install
# this toolchain in any other location
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
# This is the Cygwin path to the location where I installed the CodeSourcery
# toolchain under windows. You will also have to edit this if you install
# the CodeSourcery toolchain in any other location
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin"
# This is the path to the location where I installed the devkitARM toolchain
# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
# This is the Cygwin path to the location where I build the buildroot
# toolchain.
# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
# Add the path to the toolchain to the PATH varialble
export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
echo "PATH : ${PATH}"

55
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@ -0,0 +1,55 @@
############################################################################
# configs/xmc4500-relax/src/Makefile
#
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ASRCS =
CSRCS = xmc4_boot.c xmc4_bringup.c
ifeq ($(CONFIG_BUTTONS),y)
CSRCS += xmc4_buttons.c
endif
ifeq ($(CONFIG_USERLED),y)
CSRCS += xmc4_autoleds.c
else
CSRCS += xmc4_userleds.c
endif
ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += xmc4_appinit.c
endif
include $(TOPDIR)/configs/Board.mk

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/****************************************************************************
* configs/xmc4500-relax/src/xmc4500-relax.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H
#define __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LEDs
*
* The XMC4500 Relax Lite v1 board has two LEDs:
*
* LED1 P1.1 High output illuminates
* LED2 P1.0 High output illuminates
*/
/* BUTTONS
*
* The XMC4500 Relax Lite v1 board has two buttons:
*
* BUTTON1 P1.14 Low input sensed when button pressed
* BUTTON2 P1.15 Low input sensed when button pressed
*/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_bringup
*
* Description:
* Bring up board features
*
****************************************************************************/
int xmc4_bringup(void);
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H */

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/****************************************************************************
* config/xmc4500-relax/src/xmc4_appinit.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initalization logic and the the
* matching application logic. The value cold be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifndef CONFIG_BOARD_INITIALIZE
/* Perform board initialization */
return xmc4_bringup();
#else
return OK;
#endif /* CONFIG_BOARD_INITIALIZE */
}

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/****************************************************************************
* configs/xmc4500-relax/include/xmc4_autoleds.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "xmc4500-relax.h"
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_autoled_initialize
****************************************************************************/
void board_autoled_initialize(void)
{
#warning Missing logic
}
/****************************************************************************
* Name: board_autoled_on
****************************************************************************/
void board_autoled_on(int led)
{
#warning Missing logic
}
/****************************************************************************
* Name: board_autoled_off
****************************************************************************/
void board_autoled_off(int led)
{
#warning Missing logic
}
#endif /* CONFIG_ARCH_LEDS */

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/************************************************************************************
* configs/xmc4500-relax/src/xmc4_boot.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "xmc4500-relax.h"
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: xmc4_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
* is called early in the initialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
*
************************************************************************************/
void xmc4_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */
board_autoled_initialize();
#endif
}
/****************************************************************************
* Name: board_initialize
*
* Description:
* If CONFIG_BOARD_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_initialize(). board_initialize() will be
* called immediately after up_intitialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_INITIALIZE
void board_initialize(void)
{
/* Perform board initialization */
(void)xmc4_bringup();
}
#endif /* CONFIG_BOARD_INITIALIZE */

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/****************************************************************************
* config/samv71-xult/src/xmc4_bringup.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_bringup
*
* Description:
* Bring up board features
*
****************************************************************************/
int xmc4_bringup(void)
{
return OK;
}

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/****************************************************************************
* configs/xmc4500-relax/src/xmc4_buttons.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "xmc4500-relax.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_button_initialize
****************************************************************************/
void board_button_initialize(void)
{
#warning Missing logic
}
/****************************************************************************
* Name: board_buttons
****************************************************************************/
uint8_t board_buttons(void)
{
#warning Missing logic
return 0;
}
/****************************************************************************
* Name: board_button_irq
****************************************************************************/
#ifdef CONFIG_ARCH_IRQBUTTONS
int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
{
#warning Missing logic
return -ENOSYS;
}
#endif /* CONFIG_ARCH_IRQBUTTONS */

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/****************************************************************************
* configs/xmc4500-relax/src/xmc4_userleds.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <arch/board/board.h>
#include "xmc4500-relax.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_userled_initialize
****************************************************************************/
void board_userled_initialize(void)
{
#warning Missing logic
}
/****************************************************************************
* Name: board_userled
****************************************************************************/
void board_userled(int led, bool ledon)
{
#warning Missing logic
}
/****************************************************************************
* Name: board_userled_all
****************************************************************************/
void board_userled_all(uint8_t ledset)
{
#warning Missing logic
}