Add RCC support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2101 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
a66667c99d
commit
b5d5a26350
@ -45,5 +45,6 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
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CHIP_ASRCS =
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CHIP_CSRCS = stm32_start.c stm32_irq.c stm32_timerisr.c stm32_lowputc.c stm32_serial.c
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# stm32_gpio.c stm32_spi.c stm32_dumpgpio.c
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CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_irq.c stm32_timerisr.c \
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stm32_lowputc.c stm32_serial.c
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@ -146,13 +146,11 @@ EXTERN void up_lowsetup(void);
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* Name: stm32_clockconfig
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*
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* Description:
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* Called to change to new clock based on desired rcc and rcc2 settings.
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* This is use to set up the initial clocking but can be used later to
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* support slow clocked, low power consumption modes.
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* Called to change to new clock based on settings in board.h
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*
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****************************************************************************/
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EXTERN void stm32_clockconfig(uint32 newrcc, uint32 newrcc2);
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EXTERN void stm32_clockconfig(void);
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/****************************************************************************
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* Name: up_clockconfig
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419
arch/arm/src/stm32/stm32_rcc.c
Executable file
419
arch/arm/src/stm32/stm32_rcc.c
Executable file
@ -0,0 +1,419 @@
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/****************************************************************************
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* arch/arm/src/stm32/stm32_rcc.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "stm32_rcc.h"
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#include "stm32_internal.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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#define HSERDY_TIMEOUT 256
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Put all RCC registers in reset state */
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static inline void rcc_reset(void)
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{
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uint32 regval;
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putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
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putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
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putreg32(RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
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putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
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putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
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regval = getreg32(STM32_RCC_CR); /* Set the HSION bit */
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regval |= RCC_CR_HSION;
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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regval &= ~(RCC_CFGR_SW_MASK|RCC_CFGR_HPRE_MASK|RCC_CFGR_PPRE1_MASK|RCC_CFGR_PPRE2_MASK|RCC_CFGR_ADCPRE_MASK|RCC_CFGR_MCO_MASK);
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putreg32(regval, STM32_RCC_CFGR);
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regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */
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regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */
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regval &= ~RCC_CR_HSEBYP;
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
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regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK|RCC_CFGR_USBPRE);
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putreg32(regval, STM32_RCC_CFGR);
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putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */
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}
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static inline void rcc_enableapb1(void)
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{
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uint32 regval;
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regval = getreg32(STM32_RCC_APB1ENR);
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#if CONFIG_STM32_TIM2
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/* Timer 2 clock enable */
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regval |= RCC_APB1ENR_TIM2EN;
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#endif
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#if CONFIG_STM32_TIM3
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/* Timer 3 clock enable */
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regval |= RCC_APB1ENR_TIM3EN;
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#endif
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#if CONFIG_STM32_TIM4
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/* Timer 4 clock enable */
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regval |= RCC_APB1ENR_TIM4EN;
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#endif
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#if CONFIG_STM32_TIM5
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/* Timer 5 clock enable */
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regval |= RCC_APB1ENR_TIM5EN;
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#endif
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#if CONFIG_STM32_TIM6
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/* Timer 6 clock enable */
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regval |= RCC_APB1ENR_TIM6EN;
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#endif
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#if CONFIG_STM32_TIM7
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/* Timer 7 clock enable */
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regval |= RCC_APB1ENR_TIM7EN;
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#endif
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#if CONFIG_STM32_WWDG
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/* Window Watchdog clock enable */
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regval |= RCC_APB1ENR_WWDGEN;
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#endif
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#if CONFIG_STM32_SPI2
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/* SPI 2 clock enable */
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regval |= RCC_APB1ENR_SPI2EN;
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#endif
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#if CONFIG_STM32_SPI4
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/* SPI 3 clock enable */
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regval |= RCC_APB1ENR_SPI3EN;
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#endif
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#if CONFIG_STM32_USART2
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/* USART 2 clock enable */
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regval |= RCC_APB1ENR_USART2EN;
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#endif
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#if CONFIG_STM32_USART3
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/* USART 3 clock enable */
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regval |= RCC_APB1ENR_USART3EN;
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#endif
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#if CONFIG_STM32_UART4
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/* UART 4 clock enable */
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regval |= RCC_APB1ENR_UART4EN;
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#endif
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#if CONFIG_STM32_UART5
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/* UART 5 clock enable */
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regval |= RCC_APB1ENR_UART5EN;
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#endif
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#if CONFIG_STM32_I2C1
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/* I2C 1 clock enable */
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regval |= RCC_APB1ENR_I2C1EN;
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#endif
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#if CONFIG_STM32_I2C2
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/* I2C 2 clock enable */
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regval |= RCC_APB1ENR_I2C2EN;
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#endif
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#if CONFIG_STM32_USB
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/* USB clock enable */
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regval |= RCC_APB1ENR_USBEN;
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#endif
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#if CONFIG_STM32_CAN
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/* CAN clock enable */
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regval |= RCC_APB1ENR_CANEN;
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#endif
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#if CONFIG_STM32_BKP
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/* Backup interface clock enable */
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regval |= RCC_APB1ENR_BKPEN;
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#endif
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#if CONFIG_STM32_PWR
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/* Power interface clock enable */
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regval |= RCC_APB1ENR_PWREN;
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#endif
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#if CONFIG_STM32_DAC
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/* DAC interface clock enable */
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regval |= RCC_APB1ENR_DACEN;
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#endif
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putreg32(regval, STM32_RCC_APB2ENR);
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#if CONFIG_STM32_USB
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/* USB clock divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_USBPRE;
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regval |= STM32_CFGR_USBPRE;
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putreg32(regval, STM32_RCC_CFGR);
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#endif
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}
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static inline void rcc_enableapb2(void)
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{
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uint32 regval;
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/* Enable GPIOA, GPIOB, ... and AFIO clocks */
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regval = getreg32(STM32_RCC_APB2ENR);
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regval |= (RCC_APB2ENR_AFIOEN
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#if STM32_NGPIO > 0
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|RCC_APB2ENR_IOPAEN
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#endif
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#if STM32_NGPIO > 1
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|RCC_APB2ENR_IOPBEN
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#endif
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#if STM32_NGPIO > 2
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|RCC_APB2ENR_IOPCEN
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#endif
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#if STM32_NGPIO > 3
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|RCC_APB2ENR_IOPDEN
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#endif
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#if STM32_NGPIO > 4
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|RCC_APB2ENR_IOPEEN
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#endif
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#if STM32_NGPIO > 5
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|RCC_APB2ENR_IOPFEN
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#endif
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#if STM32_NGPIO > 6
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|RCC_APB2ENR_IOPEEN
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#endif
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);
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#if CONFIG_STM32_ADC1
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/* ADC 1 interface clock enable */
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regval |= RCC_APB2ENR_ADC1EN;
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#endif
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#if CONFIG_STM32_ADC2
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/* ADC 2 interface clock enable */
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regval |= RCC_APB2ENR_ADC2EN;
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#endif
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#if CONFIG_STM32_TIM1
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/* TIM1 Timer clock enable */
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regval |= RCC_APB2ENR_TIM1EN;
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#endif
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#if CONFIG_STM32_SPI1
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/* SPI 1 clock enable */
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regval |= RCC_APB2ENR_SPI1EN;
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#endif
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#if CONFIG_STM32_TIM8
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/* TIM8 Timer clock enable */
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regval |= RCC_APB2ENR_TIM8EN;
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#endif
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#if CONFIG_STM32_USART1
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/* USART1 clock enable */
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regval |= RCC_APB2ENR_USART1EN;
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#endif
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#if CONFIG_STM32_ADC3
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/*ADC3 interface clock enable */
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regval |= RCC_APB2ENR_ADC3EN;
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#endif
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putreg32(regval, STM32_RCC_APB2ENR);
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}
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/****************************************************************************
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* Global Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_clockconfig
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*
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* Description:
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* Called to change to new clock based on settings in board.h.
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* NOTE: This logic needs to be extended so that we can selected low-power
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* clocking modes as well!
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*
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****************************************************************************/
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void stm32_clockconfig(void)
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{
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uint32 regval;
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sint32 timeout;
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/* Make sure that we are starting in the reset state */
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rcc_reset();
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/* Enable External High-Speed Clock (HSE) */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSE is ready (or until a timeout elapsed) */
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for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
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{
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/* Check if the HSERDY flag is the set in the CR */
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
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{
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/* If so, then break-out with timeout > 0 */
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break;
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}
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}
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if( timeout > 0)
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{
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#if 0
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/* Enable Prefetch Buffer */
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/* Flash 2 wait state */
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#endif
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/* Set the HCLK source/divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_HPRE_MASK;
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regval |= STM32_RCC_CFGR_HPRE;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK2 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE2_MASK;
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regval |= STM32_RCC_CFGR_PPRE2;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK1 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE1_MASK;
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regval |= STM32_RCC_CFGR_PPRE1;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PLL divider and multipler */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
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regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
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putreg32(regval, STM32_RCC_CFGR);
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/* Enable the PLL */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLLON;
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the PLL is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
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/* Select the system clock source (probably the PLL) */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= STM32_SYSCLK_SW;
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putreg32(regval, STM32_RCC_CFGR);
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/* Wait until the selected source is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
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}
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/* Enable periperal clocking */
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rcc_enableapb2();
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rcc_enableapb1();
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}
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@ -63,16 +63,16 @@
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/* Register Addresses ***************************************************************/
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#define STM32_RCC_CR (STM32_RCC_OFFSET+STM32_RCC_CR_OFFSET)
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#define STM32_RCC_CFGR (STM32_RCC_OFFSET+STM32_RCC_CFGR_OFFSET)
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#define STM32_RCC_CIR (STM32_RCC_OFFSET+STM32_RCC_CIR_OFFSET)
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#define STM32_RCC_APB2RSTR (STM32_RCC_OFFSET+STM32_RCC_APB2RSTR_OFFSET)
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#define STM32_RCC_APB1RSTR (STM32_RCC_OFFSET+STM32_RCC_APB1RSTR_OFFSET)
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#define STM32_RCC_AHBENR (STM32_RCC_OFFSET+STM32_RCC_AHBENR_OFFSET)
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#define STM32_RCC_APB2ENR (STM32_RCC_OFFSET+STM32_RCC_APB2ENR_OFFSET)
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#define STM32_RCC_APB1ENR (STM32_RCC_OFFSET+STM32_RCC_APB1ENR_OFFSET)
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#define STM32_RCC_BDCR (STM32_RCC_OFFSET+STM32_RCC_BDCR_OFFSET)
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#define STM32_RCC_CSR (STM32_RCC_OFFSET+STM32_RCC_CSR_OFFSET)
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#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
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#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
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#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET)
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#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
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#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
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#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
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#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
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#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
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||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
|
||||
@ -61,11 +61,13 @@
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h
|
||||
* header file.
|
||||
* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
|
||||
* divided by 8. The SysTick can work either with this clock or with the
|
||||
* Cortex clock (HCLK), configurable in the SysTick Control and Status
|
||||
* register.
|
||||
*/
|
||||
|
||||
#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1)
|
||||
#define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify taht the reload value
|
||||
* will fit in the reload register.
|
||||
|
||||
@ -44,6 +44,7 @@
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <sys/types.h>
|
||||
#endif
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_internal.h"
|
||||
|
||||
/************************************************************************************
|
||||
@ -52,10 +53,41 @@
|
||||
|
||||
/* Clocking *************************************************************************/
|
||||
|
||||
# warning "These frequencies are still needed"
|
||||
#define SYSCLK_FREQUENCY 1
|
||||
#define STM32_PCLK1_FREQUENCY 1
|
||||
#define STM32_PCLK2_FREQUENCY 1
|
||||
/* On-board crystal frequency is 8MHz (HSE) */
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
|
||||
/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
|
||||
|
||||
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
|
||||
#define STM32_CFGR_PLLXTPRE 0
|
||||
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
|
||||
#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
|
||||
|
||||
/* Use the PLL and set the SYSCLK source to be the PLL */
|
||||
|
||||
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
|
||||
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
|
||||
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (72MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (72MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
|
||||
#define STM32_PCLK_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
|
||||
/* USB divider */
|
||||
|
||||
#define STM32_CFGR_USBPRE 0
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user