diff --git a/arch/arm/src/stm32f0/chip/stm32f0_flash.h b/arch/arm/src/stm32f0/chip/stm32f0_flash.h new file mode 100644 index 0000000000..9a6e668346 --- /dev/null +++ b/arch/arm/src/stm32f0/chip/stm32f0_flash.h @@ -0,0 +1,115 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32fo_flash.h + * + * Copyright (C) 20017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H +#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_KEYR_OFFSET 0x0004 +#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 +#define STM32_FLASH_SR_OFFSET 0x000c +#define STM32_FLASH_CR_OFFSET 0x0010 +#define STM32_FLASH_AR_OFFSET 0x0014 +#define STM32_FLASH_OBR_OFFSET 0x001c +#define STM32_FLASH_WRPR_OFFSET 0x0020 + +/* Register Addresses ***************************************************************/ + +#define STM32_FLASH_ACR (STM32F0_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32F0_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32F0_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32F0_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32F0_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_AR (STM32F0_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) +#define STM32_FLASH_OBR (STM32F0_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) +#define STM32_FLASH_WRPR (STM32F0_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ +/* Flash Access Control Register (ACR) */ + +#define FLASH_ACR_LATENCY_SHIFT (0) +#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ +#define FLASH_ACR_PRTFBE (1 << 4) /* Bit 4: FLASH prefetch enable */ +#define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH Prefetch buffer status */ + +/* Flash Status Register (SR) */ + +#define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */ +#define FLASH_SR_PGERR (1 << 2) /* Bit 2: Programming Error */ +#define FLASH_SR_WRPRT_ERR (1 << 4) /* Bit 3: Write Protection Error */ +#define FLASH_SR_EOP (1 << 5) /* Bit 4: End of Operation */ + +/* Flash Control Register (CR) */ + +#define FLASH_CR_PG (1 << 0) /* Bit 0: Program Page */ +#define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */ +#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */ +#define FLASH_CR_OPTPG (1 << 4) /* Bit 4: Option Byte Programming */ +#define FLASH_CR_OPTER (1 << 5) /* Bit 5: Option Byte Erase */ +#define FLASH_CR_STRT (1 << 6) /* Bit 6: Start Erase */ +#define FLASH_CR_LOCK (1 << 7) /* Bit 7: Page Locked or Lock Page */ +#define FLASH_CR_OPTWRE (1 << 9) /* Bit 8: Option Bytes Write Enable */ +#define FLASH_CR_ERRIE (1 << 10) /* Bit 10: Error Interrupt Enable */ +#define FLASH_CR_EOPIE (1 << 12) /* Bit 12: End of Program Interrupt Enable */ +#define FLASH_CR_OBLLAUNCH (1 << 13) /* Bit 13: Force option byte loading */ + +/* Flash Option byte register */ +#define FLASH_OBR_ /* To be provided */ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +void stm32_flash_lock(void); +void stm32_flash_unlock(void); + +#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_FLASH_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_rcc.h b/arch/arm/src/stm32f0/chip/stm32f0_rcc.h index 89464aa682..f499071d05 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/chip/stm32f0_rcc.h @@ -124,15 +124,17 @@ # define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ - /* Bits 13-11: Reserve. Keep the reset value */ + /* Bits 13-11: Reserve. Keep the reset value */ #define RCC_CFGR_ADCPRE (1 << 14) /* Bit 14: ADC prescaler, Obsolete use ADC_CFGR2 */ -#define RCC_CFGR_PLLSRC_SHIFT (15) /* Bit 15: PLL input clock source */ +#define RCC_CFGR_PLLSRC_SHIFT (15) /* Bit 15: PLL input clock source */ #define RCC_CFGR_PLLSRC_MASK (3 << RCC_CFGR_PLLSRC_SHIFT) # define RCC_CFGR_PLLSRC_HSId2 (0 << RCC_CFGR_PLLSRC_SHIFT) /* 00: HSI/2 as PLL input clock */ # define RCC_CFGR_PLLSRC_HS1_PREDIV (1 << RCC_CFGR_PLLSRC_SHIFT) /* 01: HSE/PREDIV as PLL input clock */ # define RCC_CFGR_PLLSRC_HSE_PREDIV (2 << RCC_CFGR_PLLSRC_SHIFT) /* 10: HSE/PREDIV as PLL input clock */ # define RCC_CFGR_PLLSRC_HSI48_PREDIV (3 << RCC_CFGR_PLLSRC_SHIFT) /* 11: HSI48/PREDIV as PLL input clock */ -#define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */ +#define RCC_CFGR_PLLXTPRE_MASK (1 << 17) /* Bit 17: HSE divider for PLL entry */ +# define RCC_CFGR_PLLXTPRE_DIV1 (0 << 17) /* 0=No divistion */ +# define RCC_CFGR_PLLXTPRE_DIV2 (1 << 17) /* 1=Divide by two */ #define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */ #define RCC_CFGR_PLLMUL_MASK (0x0f << RCC_CFGR_PLLMUL_SHIFT) # define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */ diff --git a/arch/arm/src/stm32f0/stm32f0_clockconfig.c b/arch/arm/src/stm32f0/stm32f0_clockconfig.c index ca8736bb23..7d57c98b9f 100644 --- a/arch/arm/src/stm32f0/stm32f0_clockconfig.c +++ b/arch/arm/src/stm32f0/stm32f0_clockconfig.c @@ -51,6 +51,7 @@ #include "stm32f0_rcc.h" #include "stm32f0_clockconfig.h" #include "chip/stm32f0_syscfg.h" +#include "chip/stm32f0_flash.h" #include "chip/stm32f0_gpio.h" /**************************************************************************** @@ -91,11 +92,35 @@ void stm32f0_clockconfig(void) putreg32(regval, STM32F0_RCC_CR); while ((getreg32(STM32F0_RCC_CR) & RCC_CR_PLLRDY) != 0); - /* Configure the PLL. Multiply the HSI to get System Clock */ + /* Enable FLASH prefetch buffer and set flash latency */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_1 | FLASH_ACR_PRTFBE); + putreg32(regval, STM32_FLASH_ACR); + + /* Set HCLK = SYSCLK */ regval = getreg32(STM32F0_RCC_CFGR); - regval &= ~RCC_CFGR_PLLMUL_MASK; - regval |= STM32F0_CFGR_PLLMUL; + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= RCC_CFGR_HPRE_SYSCLK; + putreg32(regval, STM32F0_RCC_CFGR); + + /* Set PCLK = HCLK */ + + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= RCC_CFGR_PPRE1_HCLK; + putreg32(regval, STM32F0_RCC_CFGR); + + /* Configure the PLL to generate the system clock + * + * 1. Use source = HSI/2 + * 2. Use PREDIV = 1 + * 3. Use multiplier from board.h + */ + + regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK | RCC_CFGR_PLLMUL_MASK); + regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32F0_CFGR_PLLMUL); putreg32(regval, STM32F0_RCC_CFGR); /* Enable the PLL */ diff --git a/arch/arm/src/stm32f0/stm32f0_serial.c b/arch/arm/src/stm32f0/stm32f0_serial.c index fb5fe2230c..f0975fad2c 100644 --- a/arch/arm/src/stm32f0/stm32f0_serial.c +++ b/arch/arm/src/stm32f0/stm32f0_serial.c @@ -552,7 +552,7 @@ static struct stm32f0_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32F0_IRQ_USART3, + .irq = STM32F0_IRQ_USART345678, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, @@ -613,7 +613,7 @@ static struct stm32f0_serial_s g_usart4priv = .priv = &g_usart4priv, }, - .irq = STM32F0_IRQ_USART4, + .irq = STM32F0_IRQ_USART345678, .parity = CONFIG_USART4_PARITY, .bits = CONFIG_USART4_BITS, .stopbits2 = CONFIG_USART4_2STOP, @@ -678,7 +678,7 @@ static struct stm32f0_serial_s g_usart5priv = .priv = &g_usart5priv, }, - .irq = STM32F0_IRQ_USART5, + .irq = STM32F0_IRQ_USART345678, .parity = CONFIG_USART5_PARITY, .bits = CONFIG_USART5_BITS, .stopbits2 = CONFIG_USART5_2STOP,