SAML21: Partial USB header file
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Gregory Nutt
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156
arch/arm/src/samdl/chip/saml_usb.h
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156
arch/arm/src/samdl/chip/saml_usb.h
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_usb.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_USB_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_USB_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* USB register offsets ********************************************************************/
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/* Common USB Device/Host Register Offsets */
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#define SAM_USB_CTRLA_OFFSET 0x0000 /* Control A Register */
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#define SAM_USB_SYNCBUSY_OFFSET 0x0002 /* Synchronization Busy Register */
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#define SAM_USB_QOSCTRL_OFFSET 0x0003 /* QOS Control Register */
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#define SAM_USB_FSMSTATUS_OFFSET 0x000d /* Finite State Machine Register */
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#define SAM_USB_DESCADD_OFFSET 0x0024 /* Descriptor Address Register */
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#define SAM_USB_PADCAL_OFFSET 0x0028 /* Pad Calibration Register */
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/* USB Device Register Offsets */
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/* USB Host Register Offsets */
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/* USB register addresses ******************************************************************/
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/* Common USB Device/Host Register Addresses */
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#define SAM_USB_CTRLA (SAM_USB_BASE+SAM_USB_CTRLA_OFFSET)
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#define SAM_USB_SYNCBUSY (SAM_USB_BASE+SAM_USB_SYNCBUSY_OFFSET)
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#define SAM_USB_QOSCTRL (SAM_USB_BASE+SAM_USB_QOSCTRL_OFFSET)
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#define SAM_USB_FSMSTATUS (SAM_USB_BASE+SAM_USB_FSMSTATUS_OFFSET)
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#define SAM_USB_DESCADD (SAM_USB_BASE+SAM_USB_DESCADD_OFFSET)
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#define SAM_USB_PADCAL (SAM_USB_BASE+SAM_USB_PADCAL_OFFSET)
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/* USB Device Register Addresses */
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/* USB Host Register Addresses */
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/* USB register bit definitions ************************************************************/
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/* Common USB Device/Host Register Offsets */
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/* Control A Register */
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#define USB_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define USB_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define USB_CTRLA_RUNSTBY (1 << 2) /* Bit 2: Run in standby */
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#define USB_CTRLA_MODE (1 << 7) /* Bit 7: Operating mode */
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# define USB_CTRLA_MODE_DEVICE (0) /* 0 = USB device mode */
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# define USB_CTRLA_MODE (1 << 7) /* 1 = USB hose mode */
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/* Synchronization Busy Register */
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#define USB_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset status */
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#define USB_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable status */
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/* QOS Control Register */
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#define USB_QOSCTRL_CQOS_SHIFT (0) /* Bit 0-1: Data quality of service */
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#define USB_QOSCTRL_CQOS_MASK (3 << USB_QOSCTRL_CQOS_SHIFT)
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# define USB_QOSCTRL_CQOS(n) ((uint8_t)(n) << USB_QOSCTRL_CQOS_SHIFT)
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#define USB_QOSCTRL_DQOS_SHIFT (2) /* Bit 2-3: Configuration qualilty of service */
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#define USB_QOSCTRL_DQOS_MASK (3 << USB_QOSCTRL_DQOS_SHIFT)
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# define USB_QOSCTRL_DQOS(n) ((uint8_t)(n) << USB_QOSCTRL_DQOS_SHIFT)
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/* Finite State Machine Register */
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#define USB_FSMSTATUS_SHIFT (0) /* Bits 0-6: Finite state machine status */
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#define USB_FSMSTATUS_MASK (0x7f << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_OFF (0x01 << USB_FSMSTATUS_SHIFT) /* Powered-off, disconnect, disabled state */
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# define USB_FSMSTATUS_ON (0x02 << USB_FSMSTATUS_SHIFT) /* Idle and Active states */
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# define USB_FSMSTATUS_SUSPEND (0x04 << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_SLEEP (0x08 << USB_FSMSTATUS_SHIFT)
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# define USB_FSMSTATUS_DNRESUME (0x10 << USB_FSMSTATUS_SHIFT) /* Down stream resume */
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# define USB_FSMSTATUS_UPRESUME (0x20 << USB_FSMSTATUS_SHIFT) /* Up stream resume */
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# define USB_FSMSTATUS_RESET (0x40 << USB_FSMSTATUS_SHIFT) /* USB lines reset */
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/* Descriptor Address Register (32-bit address) */
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/* Pad Calibration Register */
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#define USB_PADCAL_TRANSP_SHIFT (0) /* Bit 0-4: Trimmable output driver impedance P */
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#define USB_PADCAL_TRANSP_MASK (31 << USB_PADCAL_TRANSP_SHIFT)
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# define USB_PADCAL_TRANSP(n) ((uint16_t)(n) << USB_PADCAL_TRANSP_SHIFT)
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#define USB_PADCAL_TRANSN_SHIFT (6) /* Bit 7-9: Trimmable output driver impedance N */
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#define USB_PADCAL_TRANSN_MASK (31 << USB_PADCAL_TRANSN_SHIFT)
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# define USB_PADCAL_TRANSN(n) ((uint16_t)(n) << USB_PADCAL_TRANSN_SHIFT)
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#define USB_PADCAL_TRIM_SHIFT (12) /* Bit 12-14: Trim bits for DP/DM */
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#define USB_PADCAL_TRIM_MASK (7 << USB_PADCAL_TRIM_SHIFT)
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# define USB_PADCAL_TRIM(n) ((uint16_t)(n) << USB_PADCAL_TRIM_SHIFT)
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/* USB Device Register Offsets */
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/* USB Host Register Offsets */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAML21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_USB_H */
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