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Merged in david_s5/nuttx/upstream_to_greg (pull request #176)

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Upstream to greg
This commit is contained in:
Gregory Nutt 2016-12-06 12:22:42 +00:00
commit b6a21edb42
5 changed files with 162 additions and 1085 deletions
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11
arch/arm/src/stm32/Kconfig
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@ -1580,6 +1580,10 @@ config STM32_STM32F446
select STM32_HAVE_UART5
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM2
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
@ -1613,6 +1617,10 @@ config STM32_STM32F469
select STM32_HAVE_UART7
select STM32_HAVE_UART8
select STM32_HAVE_TIM1
select STM32_HAVE_TIM2
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
@ -1632,6 +1640,9 @@ config STM32_STM32F469
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_SPI6
select STM32_HAVE_SAIPLL
select STM32_HAVE_I2SPLL
config STM32_DFU
bool "DFU bootloader"

1018
arch/arm/src/stm32/chip/stm32_otgfs.h
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File diff suppressed because it is too large Load Diff

11
arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
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@ -494,11 +494,20 @@
#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */
#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1Incomplete isochronous IN transfer */
#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer */
#define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
# define OTGFS_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */
# define OTGFS_GINT_RSTDET (1 << 23) /* Bits 23: asserted when a reset is detected on the USB in partial */
#else
# define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */
#endif
#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: ro Host port interrupt */
#define OTGFS_GINT_HC (1 << 25) /* Bit 25: ro Host channels interrupt */
#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: ro Periodic TxFIFO empty */
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
#define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27 LPM interrupt */
#else
#define OTGFS_GINT_RES27 (1 << 27) /* Bit 27 Reserved, must be kept at reset value */
#endif
#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: rc_w1 Connector ID status change */
#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: rc_w1 Disconnect detected interrupt */
#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: rc_w1 Session request/new session detected interrupt */

75
arch/arm/src/stm32/stm32_otgfsdev.c
View File

@ -153,25 +153,50 @@
# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range"
#endif
#define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \
(OTGFS_GINT_RES16 | OTGFS_GINTMSK_EPMISM) \
|OTGFS_GINT_RES2223 | \
OTGFS_GINT_RES27)
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
# define OTGFS_GINT_RESETS (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET)
# define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \
(OTGFS_GINT_RES16 | OTGFS_GINTMSK_EPMISM) \
|OTGFS_GINT_RES22)
#define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \
OTGFS_GINT_SOF | \
OTGFS_GINT_ESUSP | \
OTGFS_GINT_USBSUSP | \
OTGFS_GINT_USBRST | \
OTGFS_GINT_ENUMDNE | \
OTGFS_GINT_ISOODRP | \
OTGFS_GINT_EOPF | \
OTGFS_GINT_IISOIXFR | \
OTGFS_GINT_IISOOXFR | \
OTGFS_GINT_CIDSCHG | \
OTGFS_GINT_DISC | \
OTGFS_GINT_SRQ | \
OTGFS_GINT_WKUP)
# define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \
OTGFS_GINT_SOF | \
OTGFS_GINT_ESUSP | \
OTGFS_GINT_USBSUSP | \
OTGFS_GINT_USBRST | \
OTGFS_GINT_ENUMDNE | \
OTGFS_GINT_ISOODRP | \
OTGFS_GINT_EOPF | \
OTGFS_GINT_IISOIXFR | \
OTGFS_GINT_IISOOXFR | \
OTGFS_GINT_RSTDET | \
OTGFS_GINT_LPMINT | \
OTGFS_GINT_CIDSCHG | \
OTGFS_GINT_DISC | \
OTGFS_GINT_SRQ | \
OTGFS_GINT_WKUP)
#else
# define OTGFS_GINT_RESETS OTGFS_GINT_USBRST
# define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \
(OTGFS_GINT_RES16 | OTGFS_GINTMSK_EPMISM) \
|OTGFS_GINT_RES2223 | \
OTGFS_GINT_RES27)
# define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \
OTGFS_GINT_SOF | \
OTGFS_GINT_ESUSP | \
OTGFS_GINT_USBSUSP | \
OTGFS_GINT_USBRST | \
OTGFS_GINT_ENUMDNE | \
OTGFS_GINT_ISOODRP | \
OTGFS_GINT_EOPF | \
OTGFS_GINT_IISOIXFR | \
OTGFS_GINT_IISOOXFR | \
OTGFS_GINT_CIDSCHG | \
OTGFS_GINT_DISC | \
OTGFS_GINT_SRQ | \
OTGFS_GINT_WKUP)
#endif
/* Debug ***********************************************************************/
/* Trace error codes */
@ -3517,7 +3542,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv)
/* Clear OTG interrupt */
stm32_putreg(retval, STM32_OTGFS_GOTGINT);
stm32_putreg(regval, STM32_OTGFS_GOTGINT);
}
#endif
@ -3642,7 +3667,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
/* USB reset interrupt */
if ((regval & OTGFS_GINT_USBRST) != 0)
if ((regval & OTGFS_GINT_RESETS) != 0)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval);
@ -5201,9 +5226,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* Deactivate the power down */
#if defined(CONFIG_STM32_STM32F446)
/* In the case of the STM32F446 the meaning of the bit has changed to VBUS
* Detection Enable when set
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
/* In the case of the STM32F446 or STM32F469 the meaning of the bit
* has changed to VBUS Detection Enable when set
*/
regval = OTGFS_GCCFG_PWRDWN;
@ -5228,11 +5253,11 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
stm32_putreg(regval, STM32_OTGFS_GCCFG);
up_mdelay(20);
/* For the new OTG controller in the F446 when VBUS sensing is not used we
/* For the new OTG controller in the F446, F469 when VBUS sensing is not used we
* need to force the B session valid
*/
#if defined(CONFIG_STM32_STM32F446)
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
# ifndef CONFIG_USBDEV_VBUSSENSING
regval = stm32_getreg(STM32_OTGFS_GOTGCTL);
regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL);

132
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@ -725,7 +725,7 @@ static void stm32_stdclockconfig(void)
#else /* if STM32_BOARD_USEHSE */
| RCC_PLLCFG_PLLSRC_HSE
#endif
#if defined(CONFIG_STM32_STM32F446)
#if defined(STM32_PLLCFG_PLLR)
| STM32_PLLCFG_PLLR
#endif
);
@ -743,7 +743,8 @@ static void stm32_stdclockconfig(void)
{
}
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446)
#if defined(PWR_CSR_ODRDY)
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
regval = getreg32(STM32_PWR_CR);
@ -783,12 +784,12 @@ static void stm32_stdclockconfig(void)
{
}
#if defined(CONFIG_STM32_LTDC) || \
(defined(CONFIG_STM32_STM32F446) && defined(CONFIG_STM32_SAIPLL))
#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_SAIPLL)
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
#if defined(CONFIG_STM32_STM32F446)
# if defined(CONFIG_STM32_STM32F446)
regval &= ~(RCC_PLLSAICFGR_PLLSAIM_MASK
| RCC_PLLSAICFGR_PLLSAIN_MASK
| RCC_PLLSAICFGR_PLLSAIP_MASK
@ -797,35 +798,64 @@ static void stm32_stdclockconfig(void)
| STM32_RCC_PLLSAICFGR_PLLSAIN
| STM32_RCC_PLLSAICFGR_PLLSAIP
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
#else
# elif defined(CONFIG_STM32_STM32F469)
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
| RCC_PLLSAICFGR_PLLSAIR_MASK
| RCC_PLLSAICFGR_PLLSAIQ_MASK);
| RCC_PLLSAICFGR_PLLSAIP_MASK
| RCC_PLLSAICFGR_PLLSAIQ_MASK
| RCC_PLLSAICFGR_PLLSAIR_MASK);
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
| STM32_RCC_PLLSAICFGR_PLLSAIR
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
#endif
| STM32_RCC_PLLSAICFGR_PLLSAIP
| STM32_RCC_PLLSAICFGR_PLLSAIQ
| STM32_RCC_PLLSAICFGR_PLLSAIR);
# else
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
| RCC_PLLSAICFGR_PLLSAIQ_MASK
| RCC_PLLSAICFGR_PLLSAIR_MASK);
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
| STM32_RCC_PLLSAICFGR_PLLSAIQ
| STM32_RCC_PLLSAICFGR_PLLSAIR);
# endif
putreg32(regval, STM32_RCC_PLLSAICFGR);
regval = getreg32(STM32_RCC_DCKCFGR);
#if defined(CONFIG_STM32_STM32F446)
# if defined(CONFIG_STM32_STM32F446)
regval &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MASK
| RCC_DCKCFGR_PLLSAIDIVQ_MASK
| RCC_DCKCFGR_SAI1SRC_MASK
| RCC_DCKCFGR_SAI2SRC_MASK
| RCC_DCKCFGR_I2S1SRC_MASK
| RCC_DCKCFGR_I2S2SRC_MASK);
| RCC_DCKCFGR_PLLSAIDIVQ_MASK
| RCC_DCKCFGR_SAI1SRC_MASK
| RCC_DCKCFGR_SAI2SRC_MASK
| RCC_DCKCFGR_TIMPRE
| RCC_DCKCFGR_I2S1SRC_MASK
| RCC_DCKCFGR_I2S2SRC_MASK);
regval |= (STM32_RCC_DCKCFGR_PLLI2SDIVQ
| STM32_RCC_DCKCFGR_PLLSAIDIVQ
| STM32_RCC_DCKCFGR_SAI1SRC
| STM32_RCC_DCKCFGR_SAI2SRC
| STM32_RCC_DCKCFGR_TIMPRE
| STM32_RCC_DCKCFGR_I2S1SRC
| STM32_RCC_DCKCFGR_I2S2SRC);
#else
| STM32_RCC_DCKCFGR_PLLSAIDIVQ
| STM32_RCC_DCKCFGR_SAI1SRC
| STM32_RCC_DCKCFGR_SAI2SRC
| STM32_RCC_DCKCFGR_TIMPRE
| STM32_RCC_DCKCFGR_I2S1SRC
| STM32_RCC_DCKCFGR_I2S2SRC);
# elif defined(CONFIG_STM32_STM32F469)
regval &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MASK
| RCC_DCKCFGR_PLLSAIDIVQ_MASK
| RCC_DCKCFGR_PLLSAIDIVR_MASK
| RCC_DCKCFGR_SAI1ASRC_MASK
| RCC_DCKCFGR_SAI1BSRC_MASK
| RCC_DCKCFGR_TIMPRE
| RCC_DCKCFGR_48MSEL_MASK
| RCC_DCKCFGR_SDMMCSEL_MASK
| RCC_DCKCFGR_DSISEL_MASK);
regval |= (STM32_RCC_DCKCFGR_PLLI2SDIVQ
| STM32_RCC_DCKCFGR_PLLSAIDIVQ
| STM32_RCC_DCKCFGR_PLLSAIDIVR
| STM32_RCC_DCKCFGR_SAI1ASRC
| STM32_RCC_DCKCFGR_SAI1BSRC
| STM32_RCC_DCKCFGR_TIMPRE
| STM32_RCC_DCKCFGR_48MSEL
| STM32_RCC_DCKCFGR_SDMMCSEL
| STM32_RCC_DCKCFGR_DSISEL);
# else
regval &= ~RCC_DCKCFGR_PLLSAIDIVR_MASK;
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
#endif
# endif
putreg32(regval, STM32_RCC_DCKCFGR);
/* Enable PLLSAI */
@ -841,34 +871,54 @@ static void stm32_stdclockconfig(void)
}
#endif
#if defined(CONFIG_STM32_STM32F446) && defined(CONFIG_STM32_I2SPLL)
#if defined(CONFIG_STM32_I2SPLL)
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
# if defined(CONFIG_STM32_STM32F446)
regval &= ~(RCC_PLLI2SCFGR_PLLI2SM_MASK
| RCC_PLLI2SCFGR_PLLI2SN_MASK
| RCC_PLLI2SCFGR_PLLI2SP_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK);
| RCC_PLLI2SCFGR_PLLI2SN_MASK
| RCC_PLLI2SCFGR_PLLI2SP_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SM
| STM32_RCC_PLLI2SCFGR_PLLI2SN
| STM32_RCC_PLLI2SCFGR_PLLI2SP
| STM32_RCC_PLLI2SCFGR_PLLI2SQ
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
| STM32_RCC_PLLI2SCFGR_PLLI2SN
| STM32_RCC_PLLI2SCFGR_PLLI2SP
| STM32_RCC_PLLI2SCFGR_PLLI2SQ
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
# elif defined(CONFIG_STM32_STM32F469)
regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN
| STM32_RCC_PLLI2SCFGR_PLLI2SQ
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
# endif
putreg32(regval, STM32_RCC_PLLI2SCFGR);
# if defined(STM32_RCC_DCKCFGR2)
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~(RCC_DCKCFGR2_FMPI2C1SEL_MASK
| RCC_DCKCFGR2_CECSEL_MASK
| RCC_DCKCFGR2_CK48MSEL_MASK
| RCC_DCKCFGR2_SDIOSEL_MASK
| RCC_DCKCFGR2_SPDIFRXSEL_MASK);
| RCC_DCKCFGR2_CECSEL_MASK
| RCC_DCKCFGR2_CK48MSEL_MASK
| RCC_DCKCFGR2_SDIOSEL_MASK
| RCC_DCKCFGR2_SPDIFRXSEL_MASK);
regval |= (STM32_RCC_DCKCFGR2_FMPI2C1SEL
| STM32_RCC_DCKCFGR2_CECSEL
| STM32_RCC_DCKCFGR2_CK48MSEL
| STM32_RCC_DCKCFGR2_SDIOSEL
| STM32_RCC_DCKCFGR2_SPDIFRXSEL);
| STM32_RCC_DCKCFGR2_CECSEL
| STM32_RCC_DCKCFGR2_CK48MSEL
| STM32_RCC_DCKCFGR2_SDIOSEL
| STM32_RCC_DCKCFGR2_SPDIFRXSEL);
putreg32(regval, STM32_RCC_DCKCFGR2);
# endif
/* Enable PLLI2S */