EFM32: Logic to unconditionally enable LE clocking. Even you don't use core clock LE as source for LFA or LFB, to read are write any register not clocked by HFPERCLK or HFCORECLK, HFCORECLKLE should be enabled. From Pierre-noel Bouteville.
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Gregory Nutt
parent
68418c241e
commit
b6d51ef26d
@ -212,6 +212,14 @@ config EFM32_GPIO_IRQ
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---help---
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Enable support for interrupting GPIO pins
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config EFM32_LECLOCK
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bool "Enable LE clocking (unconditionally)
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default n
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---help---
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Even you don't use core clock LE as source for LFA or LFB, to read
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are write any register not clocked by HFPERCLK or HFCORECLK,
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HFCORECLKLE should be enabled.
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if EFM32_DMA
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config EFM32_DMA_ALTDSEC
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@ -85,6 +85,17 @@
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# define BOARD_LFB_ULFCO_ENABLE false
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#endif
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#ifndef CONFIG_EFM32_LECLOCK
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# if ( ( BOARD_LFACLKSEL != _CMU_LFCLKSEL_LFA_DISABLED ) || \
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( BOARD_LFBCLKSEL != _CMU_LFCLKSEL_LFB_DISABLED ) || \
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( defined ( CONFIG_EFM32_RTC_BURTC ) ) || \
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( defined ( CONFIG_EFM32_LEUART0 ) ) || \
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( defined ( CONFIG_EFM32_LEUART1 ) ) \
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)
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# define CONFIG_EFM32_LECLOCK
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# endif
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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@ -211,40 +222,6 @@ static void efm32_enable_leclocking(void)
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putreg32(regval, EFM32_CMU_HFCORECLKEN0);
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}
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/****************************************************************************
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* Name: efm32_enable_leclocking
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*
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* Description:
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* If the core frequency is higher than CMU_MAX_FREQ_HFLE on
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* Giant/Leopard/Wonder, enable HFLE and DIV4.
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*
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****************************************************************************/
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#ifdef CMU_CTRL_HFLE
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static void efm32_enable_hfle(uint32_t frequency)
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{
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uint32_t regval;
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/* Check if the core frequency is higher than CMU_MAX_FREQ_HFLE */
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if (frequency > CMU_MAX_FREQ_HFLE)
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{
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/* Enable HFLE */
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regval = getreg32(EFM32_CMU_CTRL);
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regval |= CMU_CTRL_HFLE;
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putreg32(regval, EFM32_CMU_CTRL);
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/* Enable DIV4 factor for peripheral clock */
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regval = getreg32(EFM32_CMU_HFCORECLKDIV);
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regval |= CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4;
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putreg32(regval, EFM32_CMU_HFCORECLKDIV);
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}
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}
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#else
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# define efm32_enable_hfle(f)
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#endif
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/****************************************************************************
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* Name: efm32_maxwaitstates
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@ -495,6 +472,72 @@ static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
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return frequency;
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}
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/****************************************************************************
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* Name: efm32_hfcoreclk_config
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*
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* Description:
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* Configure the High Frequency Core Clock, HFCORECLK.
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*
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* HFCORECLK is a prescaled version of HFCLK. This clock drives the Core
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* Modules, which consists of the CPU and modules that are tightly coupled
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* to the CPU, e.g. MSC, DMA etc. This also includes the interface to the
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* Low Energy Peripherals. Some of the modules that are driven by this
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* clock can be clock gated completely when not in use. This is done by
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* clearing the clock enable bit for the specific module in
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* CMU_HFCORECLKEN0. The frequency of HFCORECLK is set using the
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* CMU_HFCORECLKDIV register. The setting can be changed dynamically and
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* the new setting takes effect immediately.
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*
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* The USB Core clock (USBC) is always undivided regardless of the
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* HFCLKDIV setting. When the USB Core is active this clock must be
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* switched to a 32 kHz clock (LFRCO or LFXO) when entering EM2. The USB
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* Core uses this clock for monitoring the USB bus. The switch is done by
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* writing USBCCLKSEL in CMU_CMD. The currently active clock can be
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* checked by reading CMU_STATUS. The clock switch can take up to 1.5 32
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* kHz cycle (45 us). To avoid polling the clock selection status when
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* switching switching from 32 kHz to HFCLK when coming up from EM2 the
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* USBCHFCLKSEL interrupt can be used. EM3 is not supported when the USB
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* is active.
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*
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****************************************************************************/
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#ifdef CONFIG_EFM32_LECLOCK
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uint32_t efm32_coreleclk_config( int frequency )
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{
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uint32_t regval;
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#ifdef CMU_CTRL_HFLE
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/* Check if the core frequency is higher than CMU_MAX_FREQ_HFLE */
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if (frequency > CMU_MAX_FREQ_HFLE)
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{
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/* Enable HFLE */
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regval = getreg32(EFM32_CMU_CTRL);
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regval |= CMU_CTRL_HFLE;
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putreg32(regval, EFM32_CMU_CTRL);
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/* Enable DIV4 factor for peripheral clock */
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regval = getreg32(EFM32_CMU_HFCORECLKDIV);
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regval |= CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4;
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putreg32(regval, EFM32_CMU_HFCORECLKDIV);
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frequency /= 4;
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}
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#else
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frequency /= 2;
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#endif
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/* Enable core clocking to the LE */
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efm32_enable_leclocking();
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return frequency;
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}
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#else
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# define efm32_coreleclk_config 0
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#endif
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/****************************************************************************
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* Name: efm32_hfcoreclk_config
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*
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@ -638,17 +681,6 @@ static inline uint32_t efm32_lfaclk_config(uint32_t lfaclksel, bool ulfrco,
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case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
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{
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/* Enable core clocking to the LE */
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efm32_enable_leclocking();
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/* Enable HFLE, if appropriate */
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efm32_enable_hfle(hfcoreclk);
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/* And, finally, enable the HFXO */
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efm32_enable_hfxo();
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lfaclk = hfcoreclk >> 1;
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}
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break;
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@ -739,17 +771,6 @@ static inline uint32_t efm32_lfbclk_config(uint32_t lfbclksel, bool ulfrco,
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case _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
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{
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/* Enable core clocking to the LE */
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efm32_enable_leclocking();
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/* Enable HFLE, if appropriate */
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efm32_enable_hfle(hfcoreclk);
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/* And, finally, enable the HFXO */
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efm32_enable_hfxo();
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lfbclk = hfcoreclk >> 1;
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}
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break;
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@ -915,6 +936,7 @@ void efm32_clockconfig(void)
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uint32_t hfclk;
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uint32_t hfcoreclk;
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uint32_t hfperclk;
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uint32_t coreleclk;
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uint32_t lfaclk;
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uint32_t lfbclk;
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@ -923,6 +945,7 @@ void efm32_clockconfig(void)
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hfclk = efm32_hfclk_config(BOARD_HFCLKSEL, BOARD_HFCLKDIV);
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hfcoreclk = efm32_hfcoreclk_config(BOARD_HFCORECLKDIV, hfclk);
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hfperclk = efm32_hfperclk_config(BOARD_HFPERCLKDIV, hfclk);
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coreleclk = efm32_coreleclk_config(hfclk);
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lfaclk = efm32_lfaclk_config(BOARD_LFACLKSEL, BOARD_LFA_ULFCO_ENABLE, hfcoreclk);
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lfbclk = efm32_lfbclk_config(BOARD_LFBCLKSEL, BOARD_LFB_ULFCO_ENABLE, hfcoreclk);
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@ -931,6 +954,7 @@ void efm32_clockconfig(void)
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efm32_auxclk_config();
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UNUSED(hfperclk);
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UNUSED(coreleclk);
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UNUSED(lfaclk);
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UNUSED(lfbclk);
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