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Xtensa: In this model, co-processor state restore must enable co-processors in CPENABLE.

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This commit is contained in:
Gregory Nutt 2016-11-08 08:23:52 -06:00
parent 6d2a10571f
commit b6d6b774e9
1 changed files with 27 additions and 23 deletions
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10
arch/xtensa/src/common/xtensa_coproc.S
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@ -283,11 +283,10 @@ xtensa_coproc_savestate:
* Entry Conditions:
* - A2 holds the address of the co-processor state save area
* - The incoming thread is set as the current thread.
* - CPENABLE is set up correctly for all required coprocessors.
*
* Exit conditions:
* - All necessary CP callee-saved state has been restored.
* - CPENABLE - unchanged.
* - CPENABLE - Set up correctly for the current thread.
* - Registers a2-a7, a13-a15 have been trashed.
*
* Must be called from assembly code only, using CALL0.
@ -306,7 +305,10 @@ _xtensa_coproc_restorestate:
/* Move the address of the thread state save area to R15 */
mov a15, a2 /* A15 is now the address of the save area */
l16ui a2, a15, XTENSA_CPSTORED /* a2 = which CPs have been saved */
l16ui a2, a15, XTENSA_CPENABLE /* a2 = Which CPs have been enable for this thread? */
wsr a2, CPENABLE /* Set CPENABLE correctly for this thread */
l16ui a2, a15, XTENSA_CPSTORED /* a2 = Which CPs have been saved for this thread? */
movi a3, 0 /* Clear the ones being restored (all of them) */
s16i a3, a15, XTENSA_CPSTORED /* Clear saved CP mask */
@ -376,7 +378,9 @@ _xtensa_coproc_restorestate:
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
/* Ensure wsr.CPENABLE has completed. */
rsync
ret
.size _xtensa_coproc_restorestate, . - _xtensa_coproc_restorestate