From b70ae9ae82db41fb24a822c53d57f2c938e45d90 Mon Sep 17 00:00:00 2001 From: Juha Niskanen Date: Thu, 2 Sep 2021 18:16:39 +0300 Subject: [PATCH] arch/arm/src/stm32l4/stm32l4_flash.c: fix FLASH_CONFIG_I to use dual-bank access This is currently only used on STM32L4+ devices. Page erase in flash_erase() function supports only dual-bank mode so it makes little sense to configure this for unsupported single-bank mode. Signed-off-by: Juha Niskanen --- arch/arm/src/stm32l4/hardware/stm32l4_flash.h | 41 +++++++++++++++---- arch/arm/src/stm32l4/stm32l4_flash.c | 8 +++- 2 files changed, 39 insertions(+), 10 deletions(-) diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h index 8b6e7ee1dc..22973a5003 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h @@ -34,14 +34,35 @@ /* Flash size is known from the chip selection: * * When CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based on the - * chip part number. This value can be overridden with - * CONFIG_STM32L4_FLASH_OVERRIDE_x + * CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based + * on the chip part number. This value can be overridden with + * CONFIG_STM32L4_FLASH_OVERRIDE_x. For example: * * Parts STM32L4xxE have 512Kb of FLASH * Parts STM32L4xxG have 1024Kb of FLASH + * Parts STM32L4xxI have 2048Kb of FLASH * - * N.B. Only Single bank mode is supported + * The STM32L4x5/STM32L4x6 devices have two banks, but on 512 and 256 Kb + * devices an option byte is available to map all pages to the first bank. + * + * The STM32L43x/44x/45x/46x chips (CONFIG_STM32L4_STM32L4X3) have a + * single bank only. + * + * STM32L4+ devices (CONFIG_STM32L4_STM32L4XR) have single and dual bank + * operating modes. + * + * The STM32L4R/Sxx devices have 1 Mb or 2 Mb of flash + * The STM32L4P/Q5x devices have 512 Kb or 1 Mb of flash + * + * STM32L4+ flash page size is 4 Kb (dual mode) or 8 Kb (single mode). + * Dual bank mode is the default and this flash driver does not support + * single bank mode on these devices. + * + * For STM32L+ bank mode is controlled by two different bits + * in option bytes: + * + * In 2 Mb devices bit 22 (DBANK) controls dual bank mode. + * In 1 Mb devices bit 21 (DB1M) controls dual bank mode. */ #define _K(x) ((x)*1024) @@ -104,9 +125,9 @@ #elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */ # define STM32L4_FLASH_NPAGES 512 # define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB */ -# define STM32L4_FLASH_NPAGES 256 -# define STM32L4_FLASH_PAGESIZE 8192 +#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ +# define STM32L4_FLASH_NPAGES 512 +# define STM32L4_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif @@ -257,10 +278,14 @@ # define FLASH_OPTCR_BFB2 (1 << 20) /* Bit 20: Dual bank boot */ # define FLASH_OPTCR_DUALBANK (1 << 21) /* Bit 21: Dual bank enable */ #endif +#if defined(CONFIG_STM32L4_STM32L4XR) +# define FLASH_OPTCR_DBANK (1 << 22) /* Bit 22: Dual bank mode for 2MB devices */ +#endif #define FLASH_OPTCR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */ #define FLASH_OPTCR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */ #define FLASH_OPTCR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || \ + defined(CONFIG_STM32L4_STM32L4XR) # define FLASH_OPTCR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */ # define FLASH_OPTCR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */ #endif diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index 041ad5f5c2..834175488a 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -89,8 +89,8 @@ #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 # define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */ -#elif FLASH_PAGE_SIZE == 8192 -# define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */ +#elif FLASH_PAGE_SIZE == 4096 +# define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ #else # error Unsupported STM32L4_FLASH_PAGESIZE #endif @@ -186,10 +186,14 @@ static inline void flash_erase(size_t page) defined(CONFIG_STM32L4_STM32L4XR) if (page <= 0xff) { + /* Select bank 1 */ + modifyreg32(STM32L4_FLASH_CR, FLASH_CR_BKER, 0); } else { + /* Select bank 2 */ + modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_BKER); } #endif