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SAMV7: Add SMC register definition header file; SAMV71-Xult: Add an LCD driver. The initial commit is simply the SAVM4E-EK ILI9375 driver will bogus name changes to ILI9488.

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This commit is contained in:
Gregory Nutt 2015-04-03 10:28:32 -06:00
parent bf7b5746a5
commit b72cf3366c
8 changed files with 1705 additions and 80 deletions
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213
arch/arm/src/samv7/chip/sam_smc.h Normal file
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@ -0,0 +1,213 @@
/****************************************************************************************
* arch/arm/src/ssamv7/chip/sam_smc.h
* Static Memory Controller (SMC) definitions for the SAMV71
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H
#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/samv7/chip.h>
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SMC register offsets *****************************************************************/
#define SAM_SMCCS_OFFSET(n) ((n) << 4)
# define SAM_SMCCS0_OFFSET 0x0000 /* SMC CS0 offset */
# define SAM_SMCCS1_OFFSET 0x0010 /* SMC CS1 offset */
# define SAM_SMCCS2_OFFSET 0x0020 /* SMC CS2 offset */
# define SAM_SMCCS3_OFFSET 0x0030 /* SMC CS3 offset */
#define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup Register */
#define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */
#define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */
#define SAM_SMCCS_MODE_OFFSET 0x000c /* SMC Mode Register */
#define SAM_SMC_OCMS_OFFSET 0x0080 /* SMC OCMS Mode Register */
#define SAM_SMC_KEY1_OFFSET 0x0084 /* SMC KEY1 Register */
#define SAM_SMC_KEY2_OFFSET 0x0088 /* SMC KEY2 Register */
#define SAM_SMC_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
#define SAM_SMC_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
/* SMC register addresses ***************************************************************/
#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n))
# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS0_OFFSET)
# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS1_OFFSET)
# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS2_OFFSET)
# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS3_OFFSET)
#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET)
#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET)
#define SAM_SMCCS0_SETUP (SAM_SMC_CS0_BASE+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS0_PULSE (SAM_SMC_CS0_BASE+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS0_CYCLE (SAM_SMC_CS0_BASE+SAM_SMCCS_CYCLE_OFFSET)
#define SAM_SMCCS0_MODE (SAM_SMC_CS0_BASE+SAM_SMCCS_MODE_OFFSET)
#define SAM_SMCCS1_SETUP (SAM_SMC_CS1_BASE+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS1_PULSE (SAM_SMC_CS1_BASE+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS1_CYCLE (SAM_SMC_CS1_BASE+SAM_SMCCS_CYCLE_OFFSET)
#define SAM_SMCCS1_MODE (SAM_SMC_CS1_BASE+SAM_SMCCS_MODE_OFFSET)
#define SAM_SMCCS2_SETUP (SAM_SMC_CS2_BASE+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS2_PULSE (SAM_SMC_CS2_BASE+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS2_CYCLE (SAM_SMC_CS2_BASE+SAM_SMCCS_CYCLE_OFFSET)
#define SAM_SMCCS2_MODE (SAM_SMC_CS2_BASE+SAM_SMCCS_MODE_OFFSET)
#define SAM_SMCCS3_SETUP (SAM_SMC_CS3_BASE+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS3_PULSE (SAM_SMC_CS3_BASE+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS3_CYCLE (SAM_SMC_CS3_BASE+SAM_SMCCS_CYCLE_OFFSET)
#define SAM_SMCCS3_MODE (SAM_SMC_CS3_BASE+SAM_SMCCS_MODE_OFFSET)
#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET)
#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET)
#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET)
#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET)
#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET)
/* SMC register bit definitions *********************************************************/
/* SMC Setup Register */
#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */
#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT)
# define SMCCS_SETUP_NWESETUP(n) ((n) << SMCCS_SETUP_NWESETUP_SHIFT)
#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */
#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT)
# define SMCCS_SETUP_NCSWRSETUP(n) ((n) << SMCCS_SETUP_NCSWRSETUP_SHIFT)
#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */
#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT)
# define SMCCS_SETUP_NRDSETUP(n) ((n) << SMCCS_SETUP_NRDSETUP_SHIFT)
#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */
#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT)
# define SMCCS_SETUP_NCSRDSETUP(n) ((n) << SMCCS_SETUP_NCSRDSETUP_SHIFT)
/* SMC Pulse Register */
#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-6: NWE Pulse Length */
#define SMCCS_PULSE_NWEPULSE_MASK (127 << SMCCS_PULSE_NWEPULSE_SHIFT)
# define SMCCS_PULSE_NWEPULSE(n) ((n) << SMCCS_PULSE_NWEPULSE_SHIFT)
#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-14: NCS Pulse Length in WRITE Access */
#define SMCCS_PULSE_NCSWRPULSE_MASK (127 << SMCCS_PULSE_NCSWRPULSE_SHIFT)
# define SMCCS_PULSE_NCSWRPULSE(n) ((n) << SMCCS_PULSE_NCSWRPULSE_SHIFT)
#define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-22: NRD Pulse Length */
#define SMCCS_PULSE_NRDPULSE_MASK (127 << SMCCS_PULSE_NRDPULSE_SHIFT)
# define SMCCS_PULSE_NRDPULSE(n) ((n) << SMCCS_PULSE_NRDPULSE_SHIFT)
#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-30: NCS Pulse Length in READ Access */
#define SMCCS_PULSE_NCSRDPULSE_MASK (127 << SMCCS_PULSE_NCSRDPULSE_SHIFT)
# define SMCCS_PULSE_NCSRDPULSE(n) ((n) << SMCCS_PULSE_NCSRDPULSE_SHIFT)
/* SMC Cycle Register */
#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */
#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT)
# define SMCCS_CYCLE_NWECYCLE(n) ((n) << SMCCS_CYCLE_NWECYCLE_SHIFT)
#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */
#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT)
# define SMCCS_CYCLE_NRDCYCLE(n) ((n) << SMCCS_CYCLE_NRDCYCLE_SHIFT)
/* SMC Mode Register */
#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */
#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */
#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */
#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT)
#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */
#define SMCCS_MODE_DBW_MASK (1 << 12) /* Bit 12: Data Bus Width */
# define SMCCS_MODE_DBW_8BIT (0 << 12) /* 0=8-bit data bus */
# define SMCCS_MODE_DBW_16BIT (1 << 12) /* 1=16-bit data bus */
#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */
#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT)
# define SMCCS_MODE_TDFCYCLES(n) ((uint32_t)(n) << SMCCS_MODE_TDFCYCLES_SHIFT)
#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */
#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */
# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */
/* SMC OCMS Mode Register */
#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */
#define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */
# define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */
# define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */
# define SMC_OCMS_CS2SE (1 << 18) /* Bit 18: Chip Select 2 Scrambling Enable */
# define SMC_OCMS_CS3SE (1 << 19) /* Bit 19: Chip Select 3 Scrambling Enable */
/* SMC KEY1/2 Registers (32-bit data) */
/* SMC Write Protect Mode Register */
#define SMC_WPCR_WPPEN (1 << 0) /* Bit 0: Write Protection Enable */
#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */
#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT)
# define SMC_WPCR_WPKEY (0x00534d43 << SMC_WPCR_WPKEY_SHIFT)
/* SMC Write Protection Status */
#define SMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Source */
#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H */

28
configs/samv71-xult/Kconfig
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@ -17,9 +17,11 @@ choice
config SAMV71XULT_MXTXPLND_EXT1
bool "Connected on EXT1 (2x10 pin)"
depends on EXPERIMENTAL
config SAMV71XULT_MXTXPLND_EXT2
bool "Connected on EXT2 (2x10 pin)"
depends on EXPERIMENTAL
config SAMV71XULT_MXTXPLND_LCD
bool "Connected on LCD (50-pin)"
@ -37,6 +39,32 @@ config SAMV71XULT_MXT_DEVMINOR
default 0
endif # INPUT_MXT
if LCD
choice
prompt "LCD Color Configuration"
default SAMV71XULT_LCD_RGB565
config SAMV71XULT_LCD_RGB565
bool "RGB565"
config SAMV71XULT_LCD_RGB24
bool "RGB24 / RGB888"
depends on EXPERIMENTAL
config SAMV71XULT_LCD_RGB32
bool "RGB32"
depends on EXPERIMENTAL
endchoice # LCD Color Configuration
config SAMV71XULT_LCD_BGCOLOR
hex "Initial background color"
default 0x00
endif # LCD
endif # SAMV71XULT_MXTXPLND
config SAMV71XULT_HSMCI0_AUTOMOUNT

151
configs/samv71-xult/include/board.h
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@ -354,18 +354,16 @@
#define GPIO_SSC0_TD GPIO_SSC0_TD_1
/* maXTouch Xplained Pro LCD
*
* maXTouch Xplained Pro Standard Extension Header
/* maXTouch Xplained Pro Standard Extension Header **********************************
* -----------------------------------------------
* This LCD could be connected either via EXT1 or EXT2 using the 2x10
* 20-pin cable and the maXTouch Xplained Pro standard extension
* header. Access is then performed in SPI mode.
*
* ---- -------- ---- ----------- ---- ----------- ------------------------------------------
* ---- -------- ---- ----------- ---- ----------- ----------------------------------
* SAMV71-XULT maxTouch Xplained Pro
* PIN FUNCTION EXT1 FUNC EXT2 FUNC Description
* ---- -------- ---- ----------- ---- ----------- ------------------------------------------
* ---- -------- ---- ----------- ---- ----------- ----------------------------------
* 1 ID - - - - Communication line to ID chip
* 2 GND - - - - Ground
* 3 N/C PC31 - PD30 -
@ -375,9 +373,9 @@
* 7 PWM PA0 PWMC0_PWMH0 PC19 PWMC0_PMWH2 Backlight control
* 8 N/C PC30 - PD26 -
* 9 GPIO/IRQ PD28 GPIO PA2 GPIO IRQ from maXTouch controller
* 10 GPIO PA5 GPIO PA24 GPIO RESET signal for maXTouch and LCD controller
* 11 I2C SDA PA3 TWID0 PA3 TWID0 I2C Data line for maXTouch controller
* 12 I2C SCL PA4 TWICK0 PA4 TWICK0 I2C Clock line for maXTouch controller
* 10 GPIO PA5 GPIO PA24 GPIO RESET signal
* 11 I2C SDA PA3 TWID0 PA3 TWID0 maXTouch I2C Data line
* 12 I2C SCL PA4 TWICK0 PA4 TWICK0 maXTouch I2C Clock line
* 13 N/C PB0 - PA21 -
* 14 N/C PB1 - PB4 -
* 15 CS PD25 GPIO PD27 GPIO CS line for LCD controller
@ -386,7 +384,7 @@
* 18 SPI SCK PD22 SPI0_SPCK PD22 SPI0_SPCK SPI Clock line
* 19 GND - - - - Ground
* 20 VCC - - - - Target supply voltage
* ---- -------- ---- ----------- ---- ----------- ------------------------------------------
* ---- -------- ---- ----------- ---- ----------- ----------------------------------
*
* There are no alternatives for SPI0 and TWI0 pins. Only the PWM pins require any
* disambiguration.
@ -404,80 +402,79 @@
# define GPIO_PWMC0_H2 GPIO_PWMC0_H2_5
# define GPIO_MXTXLND_PWM GPIO_PWMC0_H2_5
/* maXTouch Xplained Pro Xplained Pro LCD Connector
* ------------------------------------------------
* It is also possible to connect the LCD via the flat cable to the EXT4 LCD
* connector. In this case, you would use the SMC/EBI to communicate with the
* LCD.
/* maXTouch Xplained Pro Xplained Pro LCD Connector *********************************
*
* ---- ------------ ---- -------- -----------------------------------------------------------
* LCD SAMV71 Description
* Pin Function Pin Function
* ---- ------------ ---- -------- -----------------------------------------------------------
* 1 ID - - Communication line to ID chip on extension board
* 2 GND - GND Ground
* 3 D0 PC0 D0 Data line
* 4 D1 PC1 D1 Data line
* 5 D2 PC2 D2 Data line
* 6 D3 PC3 D3 Data line
* 7 GND - GND Ground
* 8 D4 PC4 D4 Data line
* 9 D5 PC5 D5 Data line
* 10 D6 PC6 D6 Data line
* 11 D7 PC7 D7 Data line
* 12 GND - GND Ground
* 13 D8 PE0 D8 Data line
* 14 D9 PE1 D9 Data line
* 15 D10 PE2 D10 Data line
* 16 D11 PE3 D11 Data line
* 17 GND - GND Ground
* 18 D12 PE4 D12 Data line
* 19 D12 PE5 D13 Data line
* 20 D14 PA15 D14 Data line
* 21 D15 PA16 D15 Data line
* 22 GND - GND Ground
* 23 D16 - - Data line
* 24 D17 - - Data line
* 25 N/C - -
* 26 N/C - -
* 27 GND - GND Ground
* 28 N/C - -
* 29 N/C - -
* 30 N/C - -
* 31 N/C - -
* 32 GND - GND Ground
* 33 PCLK/ PC30 GPIO RGB: Pixel clock Display RAM select.
* CMD_DATA_SEL MCU: One address line of the MCU for displays where it
* is possible to select either the register or the
* data interface
* 34 VSYNC/CS PD19 NCS3 RGB: Vertical synchronization
* MCU: Chip select
* 35 HSYNC/WE PC8 NWE RGB: Horizontal synchronization
* MCU: Write enable signal
* 36 DATA ENABLE/ PC11 NRD RGB: Data enable signal
* RE MCU: Read enable signal
* 37 SPI SCK - - MCU: Clock for SPI
* 38 SPI MOSI - - MCU: Master out slave in line of SPI
* 39 SPI MISO - - MCU: Master in slave out line of SPI
* 40 SPI SS - - MCU: Slave select for SPI
* 41 N/C - -
* 42 TWI SDA PA3 TWD0 I2C data line (maXTouch®)
* 43 TWI SCL PA4 TWCK0 I2C clock line (maXTouch)
* 44 IRQ1 PD28 WKUP5 maXTouch interrupt line
* 45 N/C PA2 WKUP2
* 46 PWM PC9 TIOB7 Backlight control
* 47 RESET PC13 GPIO Reset for both display and maxTouch
* 48 VCC - - 3.3V power supply for extension board
* 49 VCC - - 3.3V power supply for extension board
* 50 GND - - Ground
* ---- ------------ ---- -------- -----------------------------------------------------------
* Only the RGB is supported by this BSP (via SMC/EBI). The switch mode
* selector on the back of the maXtouch should be set in the OFF-ON-OFF
* positions to select 16-bit color mode.
*
* There are no alternatives for SMC/EBI, TWI0, or TIOB pins. No pin disambiguration
* is necessary.
* ----------------- ------------- -------------------------------------------------
* LCD SAMV71 Description
* Pin Function Pin Function
* ---- ------------ ---- -------- -------------------------------------------------
* 1 ID - - Chip ID communication line
* 2 GND - GND Ground
* 3 D0 PC0 D0 Data line
* 4 D1 PC1 D1 Data line
* 5 D2 PC2 D2 Data line
* 6 D3 PC3 D3 Data line
* 7 GND - GND Ground
* 8 D4 PC4 D4 Data line
* 9 D5 PC5 D5 Data line
* 10 D6 PC6 D6 Data line
* 11 D7 PC7 D7 Data line
* 12 GND - GND Ground
* 13 D8 PE0 D8 Data line
* 14 D9 PE1 D9 Data line
* 15 D10 PE2 D10 Data line
* 16 D11 PE3 D11 Data line
* 17 GND - GND Ground
* 18 D12 PE4 D12 Data line
* 19 D13 PE5 D13 Data line
* 20 D14 PA15 D14 Data line
* 21 D15 PA16 D15 Data line
* 22 GND - GND Ground
* 23 D16 - - Data line
* 24 D17 - - Data line
* 25 N/C - -
* 26 N/C - -
* 27 GND - GND Ground
* 28 N/C - -
* 29 N/C - -
* 30 N/C - -
* 31 N/C - -
* 32 GND - GND Ground
* 33 PCLK/ PC30 GPIO RGB: Pixel clock Display RAM select.
* CMD_DATA_SEL MCU: One address line of the MCU for displays where
* it is possible to select either the register
* or the data interface
* 34 VSYNC/CS PD19 NCS3 RGB: Vertical synchronization.
* MCU: Chip select
* 35 HSYNC/WE PC8 NWE RGB: Horizontal synchronization
* MCU: Write enable signal
* 36 DATA ENABLE/ PC11 NRD RGB: Data enable signal
* RE MCU: Read enable signal
* 37 SPI SCK - - MCU: Clock for SPI
* 38 SPI MOSI - - MCU: Master out slave in line of SPI
* 39 SPI MISO - - MCU: Master in slave out line of SPI
* 40 SPI SS - - MCU: Slave select for SPI
* 41 N/C - -
* 42 TWI SDA PA3 TWD0 I2C data line (maXTouch®)
* 43 TWI SCL PA4 TWCK0 I2C clock line (maXTouch)
* 44 IRQ1 PD28 WKUP5 maXTouch interrupt line
* 45 N/C PA2 WKUP2
* 46 PWM PC9 TIOB7 Backlight control
* 47 RESET PC13 GPIO Reset for both display and maxTouch
* 48 VCC - - 3.3V power supply for extension board
* 49 VCC - - 3.3V power supply for extension board
* 50 GND - - Ground
* ---- ------------ ---- -------- --------------------------------------------------
*/
# elif defined(CONFIG_SAMV71XULT_MXTXLND_LCD)
# define GPIO_SMC_NCS3 GPIO_SMC_NCS3_2
# endif
#endif /* CONFIG_SAMV71XULT_MXTXLND */

5
configs/samv71-xult/src/Makefile
View File

@ -106,9 +106,14 @@ endif
endif
endif
ifeq ($(SAMV71XULT_MXTXPLND),y)
ifeq ($(CONFIG_LCD),y)
CSRCS += sam_ili9488.c
endif
ifeq ($(CONFIG_INPUT_MXT),y)
CSRCS += sam_maxtouch.c
endif
endif
COBJS = $(CSRCS:.c=$(OBJEXT))

1300
configs/samv71-xult/src/sam_ili9488.c Normal file
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File diff suppressed because it is too large Load Diff

6
configs/samv71-xult/src/sam_wm8904.c
View File

@ -70,13 +70,13 @@
* Private Types
****************************************************************************/
struct samv7xult_mwinfo_s
struct samv71xult_mwinfo_s
{
/* Standard MW8904 interface */
struct wm8904_lower_s lower;
/* Extensions for the samv7xult board */
/* Extensions for the samv71xult board */
wm8904_handler_t handler;
FAR void *arg;
@ -113,7 +113,7 @@ static bool wm8904_enable(FAR const struct wm8904_lower_s *lower,
* by the driver and is presumed to persist while the driver is active.
*/
static struct samv7xult_mwinfo_s g_wm8904info =
static struct samv71xult_mwinfo_s g_wm8904info =
{
.lower =
{

75
configs/samv71-xult/src/samv71-xult.h
View File

@ -398,6 +398,81 @@
#define WM8904_SSC_BUS 0
/* maXTouch Xplained Pro Xplained Pro LCD Connector *********************************/
/*
* Only the RGB is supported by this BSP (via SMC/EBI). The switch mode
* selector on the back of the maXtouch should be set in the OFF-ON-OFF
* positions to select 16-bit color mode.
*
* ----------------- ------------- --------------------------------------------------
* LCD SAMV71 Description
* Pin Function Pin Function
* ---- ------------ ---- -------- --------------------------------------------------
* 1 ID - - Chip ID communication line
* 2 GND - GND Ground
* 3 D0 PC0 D0 Data line
* 4 D1 PC1 D1 Data line
* 5 D2 PC2 D2 Data line
* 6 D3 PC3 D3 Data line
* 7 GND - GND Ground
* 8 D4 PC4 D4 Data line
* 9 D5 PC5 D5 Data line
* 10 D6 PC6 D6 Data line
* 11 D7 PC7 D7 Data line
* 12 GND - GND Ground
* 13 D8 PE0 D8 Data line
* 14 D9 PE1 D9 Data line
* 15 D10 PE2 D10 Data line
* 16 D11 PE3 D11 Data line
* 17 GND - GND Ground
* 18 D12 PE4 D12 Data line
* 19 D13 PE5 D13 Data line
* 20 D14 PA15 D14 Data line
* 21 D15 PA16 D15 Data line
* 22 GND - GND Ground
* 23 D16 - - Data line
* 24 D17 - - Data line
* 25 N/C - -
* 26 N/C - -
* 27 GND - GND Ground
* 28 N/C - -
* 29 N/C - -
* 30 N/C - -
* 31 N/C - -
* 32 GND - GND Ground
* 33 PCLK/ PC30 GPIO RGB: Pixel clock Display RAM select.
* CMD_DATA_SEL MCU: One address line of the MCU for displays where it
* is possible to select either the register or the
* data interface
* 34 VSYNC/CS PD19 NCS3 RGB: Vertical synchronization.
* MCU: Chip select
* 35 HSYNC/WE PC8 NWE RGB: Horizontal synchronization
* MCU: Write enable signal
* 36 DATA ENABLE/ PC11 NRD RGB: Data enable signal
* RE MCU: Read enable signal
* 37 SPI SCK - - MCU: Clock for SPI
* 38 SPI MOSI - - MCU: Master out slave in line of SPI
* 39 SPI MISO - - MCU: Master in slave out line of SPI
* 40 SPI SS - - MCU: Slave select for SPI
* 41 N/C - -
* 42 TWI SDA PA3 TWD0 I2C data line (maXTouch®)
* 43 TWI SCL PA4 TWCK0 I2C clock line (maXTouch)
* 44 IRQ1 PD28 WKUP5 maXTouch interrupt line
* 45 N/C PA2 WKUP2
* 46 PWM PC9 TIOB7 Backlight control
* 47 RESET PC13 GPIO Reset for both display and maxTouch
* 48 VCC - - 3.3V power supply for extension board
* 49 VCC - - 3.3V power supply for extension board
* 50 GND - - Ground
* ---- ------------ ---- -------- --------------------------------------------------
*/
#define GPIO_ILI9488_CDS (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \
GPIO_PORT_PIOC | GPIO_PIN30)
#define GPIO_ILI9488_RST (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \
GPIO_PORT_PIOC | GPIO_PIN13)
#define GPIO_ILI9488_BKL GPIO_TC7_TIOB
/************************************************************************************
* Public Types
************************************************************************************/

7
include/nuttx/lcd/ili9488.h
View File

@ -34,6 +34,13 @@
* Pre-processor Definitions
****************************************************************************/
/* ILI9488 ID code */
#define ILI9488_DEVICE_CODE 0x9488
#define ILI9488_LCD_WIDTH 320
#define ILI9488_LCD_HEIGHT 480
#define ILI9488_SELF_TEST_OK 0xc0
/* Level 1 Commands (from the display Datasheet) */
#define ILI9488_CMD_NOP 0x00