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Add clock configuration logic for the STM32F40

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4123 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-11-23 18:18:26 +00:00
parent b5f05cbbc5
commit b761b5d0e8
3 changed files with 70 additions and 30 deletions
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1
configs/stm3240g-eval/README.txt
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@ -287,7 +287,6 @@ STM3240G-EVAL-specific Configuration Options
CONFIG_STM32_I2C3 CONFIG_STM32_I2C3
CONFIG_STM32_CAN1 CONFIG_STM32_CAN1
CONFIG_STM32_CAN2 CONFIG_STM32_CAN2
CONFIG_STM32_PWR
CONFIG_STM32_DAC CONFIG_STM32_DAC
APB2 APB2

94
configs/stm3240g-eval/include/board.h
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@ -54,48 +54,90 @@
************************************************************************************/ ************************************************************************************/
/* Clocking *************************************************************************/ /* Clocking *************************************************************************/
#warning "Revisit -- this is from the STM3210E-EVAL" /* Four clock sources are available on STM3240G-EVAL evaluation board for
* STM32F407IGH6 and RTC embedded:
*
* X1, 25 MHz crystal for ethernet PHY with socket. It can be removed when clock is
* provided by MCO pin of the MCU
* X2, 26 MHz crystal for USB OTG HS PHY
* X3, 32 kHz crystal for embedded RTC
* X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller (It can be removed
* from socket when internal RC clock is used.)
*
* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
* System Clock source : PLL (HSE)
* SYSCLK(Hz) : 168000000 Determined by PLL configuration
* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
* HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL)
* PLLM : 25 (STM32_PLLCFG_PLLM)
* PLLN : 336 (STM32_PLLCFG_PLLN)
* PLLP : 2 (STM32_PLLCFG_PLLP)
* PLLQ : 7 (STM32_PLLCFG_PPQ)
* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
* Flash Latency(WS) : 5
* Prefetch Buffer : OFF
* Instruction cache : ON
* Data cache : ON
* Require 48MHz for USB OTG FS, : Enabled
* SDIO and RNG clock
*/
/* On-board crystal frequency is 8MHz (HSE) */ /* HSI - 16 MHz RC factory-trimmed
* LSI - 32 KHz RC
* HSE - On-board crystal frequency is 25MHz
* LSE - 32.768 kHz
*/
#define STM32_BOARD_XTAL 8000000ul #define STM32_BOARD_XTAL 25000000ul
/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ #define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC /* Main PLL Configuration.
#define STM32_CFGR_PLLXTPRE 0 *
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 * PLL source is HSE
#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* = (25,000,000 / 25) * 336
* = 336,000,000
* SYSCLK = PLL_VCO / PLLP
* = 336,000,000 / 2 = 168,000,000
* USB OTG FS, SDIO and RNG Clock
* = PLL_VCO / PLLQ
* = 48,000,000
*/
/* Use the PLL and set the SYSCLK source to be the PLL */ #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
#define STM32_PLLCFG_PPQ RCC_PLLCFG_PLLQ(7)
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL #define STM32_SYSCLK_FREQUENCY 168000000ul
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
/* AHB clock (HCLK) is SYSCLK (72MHz) */ /* AHB clock (HCLK) is SYSCLK (168MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE1_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE2_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* USB divider -- Divide PLL clock by 1.5 */
#define STM32_CFGR_USBPRE 0
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx. * otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1 */ * Note: TIM1,8 are on APB2, others on APB1
*/
#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY #define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY #define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY

3
configs/stm3240g-eval/ostest/defconfig
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@ -157,7 +157,6 @@ CONFIG_STM32_I2C2=n
CONFIG_STM32_I2C3=n CONFIG_STM32_I2C3=n
CONFIG_STM32_CAN1=n CONFIG_STM32_CAN1=n
CONFIG_STM32_CAN2=n CONFIG_STM32_CAN2=n
CONFIG_STM32_PWR=n
CONFIG_STM32_DAC=n CONFIG_STM32_DAC=n
# APB2: # APB2:
CONFIG_STM32_TIM1=n CONFIG_STM32_TIM1=n
@ -169,7 +168,7 @@ CONFIG_STM32_ADC2=n
CONFIG_STM32_ADC3=n CONFIG_STM32_ADC3=n
CONFIG_STM32_SDIO=n CONFIG_STM32_SDIO=n
CONFIG_STM32_SPI1=n CONFIG_STM32_SPI1=n
CONFIG_STM32_SYSCFG=n CONFIG_STM32_SYSCFG=y
CONFIG_STM32_TIM9=n CONFIG_STM32_TIM9=n
CONFIG_STM32_TIM10=n CONFIG_STM32_TIM10=n
CONFIG_STM32_TIM11=n CONFIG_STM32_TIM11=n