arch/risc-v: Merge mcause.h into irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
Xiang Xiao
parent
eec94132c4
commit
b803919b9d
@ -66,6 +66,8 @@
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#define RISCV_IRQ_RESERVED (14) /* Reserved */
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#define RISCV_IRQ_SROREPF (15) /* Store/AMO page fault */
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#define RISCV_MAX_EXCEPTION (15)
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/* IRQ 16- : (async event:interrupt=1) */
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#define RISCV_IRQ_ASYNC (16)
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@ -77,6 +79,16 @@
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#define RISCV_IRQ_MEXT (RISCV_IRQ_ASYNC + 11) /* Machine External Int */
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#define RISCV_IRQ_HPMOV (RISCV_IRQ_ASYNC + 17) /* HPM Overflow Int */
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/* IRQ bit and IRQ mask */
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#ifdef CONFIG_ARCH_RV32
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# define RISCV_IRQ_BIT (1 << 31)
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#else
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# define RISCV_IRQ_BIT (1 << 63)
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#endif
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#define RISCV_IRQ_MASK (~RISCV_IRQ_BIT)
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/* Configuration ************************************************************/
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/* If this is a kernel build, how many nested system calls should we
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@ -1,63 +0,0 @@
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/****************************************************************************
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* arch/risc-v/include/mcause.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_MCAUSE_H
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#define __ARCH_RISCV_INCLUDE_MCAUSE_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Interrupt(BIT31) or Exception(0) */
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#define MCAUSE_INTERRUPT (1 << 31)
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#define MCAUSE_INTERRUPT_MASK (~MCAUSE_INTERRUPT)
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/* Exception values *********************************************************/
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#define MCAUSE_ADDE_MISALIGNED (0) /* Instruction address misaligned */
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#define MCAUSE_INST_ACCESS_FAULT (1) /* Instruction access fault */
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#define MCAUSE_ILLEGAL_INST (2) /* Illegal instruction */
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#define MCAUSE_BREAKPOINT (3) /* Breakpoint */
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#define MCAUSE_LOAD_MISALIGNED (4) /* Load address misaligned */
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#define MCAUSE_LOAD_ACCESS_FAULT (5) /* Load access fault */
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#define MCAUSE_STORE_MISALIGNED (6) /* Store/AMO address misaligned */
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#define MCAUSE_STORE_ACCESS_FAULT (7) /* Store/AMO access fault */
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#define MCAUSE_ECALL_U (8) /* Environment call from U-mode */
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#define MCAUSE_ECALL_S (9) /* Environment call from S-mode */
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#define MCAUSE_RESERVED (10) /* Reserved */
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#define MCAUSE_ECALL_M (11) /* Environment call from M-mode */
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#define MCAUSE_INST_PAGE_FAULT (12) /* Instruction page fault */
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#define MCAUSE_LOAD_PAGE_FAULT (13) /* Load page fault */
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#define MCAUSE_RESERVED (14) /* Reserved */
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#define MCAUSE_STORE_PAGE_FAULT (15) /* Store/AMO page fault */
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/* Max RISC-V defined mcause exception values. */
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#define MCAUSE_MAX_EXCEPTION (15)
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#endif /* __ARCH_RISCV_INCLUDE_MCAUSE_H */
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@ -25,7 +25,7 @@
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* Included Files
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****************************************************************************/
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#include <arch/mcause.h>
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#include <arch/irq.h>
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/****************************************************************************
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* Pre-processor Definitions
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@ -33,13 +33,12 @@
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#include <nuttx/arch.h>
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#include <nuttx/board.h>
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#include <nuttx/syslog/syslog.h>
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#include <arch/mcause.h>
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#include <arch/irq.h>
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#include "riscv_arch.h"
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#include "riscv_internal.h"
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#ifdef CONFIG_DEBUG_INFO
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static const char *g_reasons_str[MCAUSE_MAX_EXCEPTION + 1] =
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static const char *g_reasons_str[RISCV_MAX_EXCEPTION + 1] =
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{
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"Instruction address misaligned",
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"Instruction access fault",
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@ -58,7 +57,6 @@ static const char *g_reasons_str[MCAUSE_MAX_EXCEPTION + 1] =
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"Reserved",
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"Store/AMO page fault"
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};
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#endif
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/****************************************************************************
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* Public Functions
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@ -74,21 +72,19 @@ static const char *g_reasons_str[MCAUSE_MAX_EXCEPTION + 1] =
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void riscv_exception(uintptr_t mcause, uintptr_t *regs)
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{
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uintptr_t cause = mcause & MCAUSE_INTERRUPT_MASK;
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uintptr_t cause = mcause & RISCV_IRQ_MASK;
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#ifdef CONFIG_DEBUG_INFO
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if (mcause > MCAUSE_MAX_EXCEPTION)
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if (mcause > RISCV_MAX_EXCEPTION)
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{
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_alert("EXCEPTION: Unknown. MCAUSE: %08" PRIx32 "\n", cause);
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_alert("EXCEPTION: Unknown. MCAUSE: %" PRIxREG "\n", cause);
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}
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else
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{
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_alert("EXCEPTION: %s. MCAUSE: %08" PRIx32 "\n",
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_alert("EXCEPTION: %s. MCAUSE: %" PRIxREG "\n",
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g_reasons_str[cause], cause);
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}
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#endif
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_alert("PANIC!!! Exception = %08" PRIx32 "\n", cause);
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_alert("PANIC!!! Exception = %" PRIxREG "\n", cause);
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up_irq_save();
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CURRENT_REGS = regs;
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PANIC();
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@ -34,7 +34,6 @@
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#include <arch/board/board.h>
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#include <arch/irq.h>
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#include <arch/mcause.h>
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#include "riscv_internal.h"
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#include "hardware/esp32c3_interrupt.h"
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@ -378,8 +377,8 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
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int irq;
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uintptr_t *mepc = regs;
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if (((MCAUSE_INTERRUPT & mcause) == 0) &&
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(mcause != MCAUSE_ECALL_M))
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if (((RISCV_IRQ_BIT & mcause) == 0) &&
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(mcause != RISCV_IRQ_ECALLM))
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{
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#ifdef CONFIG_ESP32C3_EXCEPTION_ENABLE_CACHE
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if (!spi_flash_cache_enabled())
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@ -406,9 +405,9 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
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board_autoled_on(LED_INIRQ);
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if ((MCAUSE_INTERRUPT & mcause) != 0)
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if ((RISCV_IRQ_BIT & mcause) != 0)
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{
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uint8_t cpuint = mcause & MCAUSE_INTERRUPT_MASK;
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uint8_t cpuint = mcause & RISCV_IRQ_MASK;
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DEBUGASSERT(cpuint <= ESP32C3_CPUINT_MAX);
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@ -427,7 +426,7 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
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}
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else
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{
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if (mcause == MCAUSE_ECALL_M)
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if (mcause == RISCV_IRQ_ECALLM)
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{
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*mepc += 4;
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irq_dispatch(ESP32C3_IRQ_ECALL_M, regs);
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