From b803919b9dfc1428de1e5b4baa1f12c0bb9c1a83 Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Fri, 21 Jan 2022 23:39:28 +0800 Subject: [PATCH] arch/risc-v: Merge mcause.h into irq.h Signed-off-by: Huang Qi --- arch/risc-v/include/irq.h | 12 ++++ arch/risc-v/include/mcause.h | 63 -------------------- arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h | 2 +- arch/risc-v/src/common/riscv_exception.c | 18 +++--- arch/risc-v/src/esp32c3/esp32c3_irq.c | 11 ++-- 5 files changed, 25 insertions(+), 81 deletions(-) delete mode 100644 arch/risc-v/include/mcause.h diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h index 4773a6648c..d3e50c00e2 100644 --- a/arch/risc-v/include/irq.h +++ b/arch/risc-v/include/irq.h @@ -66,6 +66,8 @@ #define RISCV_IRQ_RESERVED (14) /* Reserved */ #define RISCV_IRQ_SROREPF (15) /* Store/AMO page fault */ +#define RISCV_MAX_EXCEPTION (15) + /* IRQ 16- : (async event:interrupt=1) */ #define RISCV_IRQ_ASYNC (16) @@ -77,6 +79,16 @@ #define RISCV_IRQ_MEXT (RISCV_IRQ_ASYNC + 11) /* Machine External Int */ #define RISCV_IRQ_HPMOV (RISCV_IRQ_ASYNC + 17) /* HPM Overflow Int */ +/* IRQ bit and IRQ mask */ + +#ifdef CONFIG_ARCH_RV32 +# define RISCV_IRQ_BIT (1 << 31) +#else +# define RISCV_IRQ_BIT (1 << 63) +#endif + +#define RISCV_IRQ_MASK (~RISCV_IRQ_BIT) + /* Configuration ************************************************************/ /* If this is a kernel build, how many nested system calls should we diff --git a/arch/risc-v/include/mcause.h b/arch/risc-v/include/mcause.h deleted file mode 100644 index 41a729286c..0000000000 --- a/arch/risc-v/include/mcause.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/risc-v/include/mcause.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_INCLUDE_MCAUSE_H -#define __ARCH_RISCV_INCLUDE_MCAUSE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Interrupt(BIT31) or Exception(0) */ - -#define MCAUSE_INTERRUPT (1 << 31) -#define MCAUSE_INTERRUPT_MASK (~MCAUSE_INTERRUPT) - -/* Exception values *********************************************************/ - -#define MCAUSE_ADDE_MISALIGNED (0) /* Instruction address misaligned */ -#define MCAUSE_INST_ACCESS_FAULT (1) /* Instruction access fault */ -#define MCAUSE_ILLEGAL_INST (2) /* Illegal instruction */ -#define MCAUSE_BREAKPOINT (3) /* Breakpoint */ -#define MCAUSE_LOAD_MISALIGNED (4) /* Load address misaligned */ -#define MCAUSE_LOAD_ACCESS_FAULT (5) /* Load access fault */ -#define MCAUSE_STORE_MISALIGNED (6) /* Store/AMO address misaligned */ -#define MCAUSE_STORE_ACCESS_FAULT (7) /* Store/AMO access fault */ -#define MCAUSE_ECALL_U (8) /* Environment call from U-mode */ -#define MCAUSE_ECALL_S (9) /* Environment call from S-mode */ -#define MCAUSE_RESERVED (10) /* Reserved */ -#define MCAUSE_ECALL_M (11) /* Environment call from M-mode */ -#define MCAUSE_INST_PAGE_FAULT (12) /* Instruction page fault */ -#define MCAUSE_LOAD_PAGE_FAULT (13) /* Load page fault */ -#define MCAUSE_RESERVED (14) /* Reserved */ -#define MCAUSE_STORE_PAGE_FAULT (15) /* Store/AMO page fault */ - -/* Max RISC-V defined mcause exception values. */ - -#define MCAUSE_MAX_EXCEPTION (15) - -#endif /* __ARCH_RISCV_INCLUDE_MCAUSE_H */ - diff --git a/arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h b/arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h index 783e06e084..f528d126e4 100644 --- a/arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h +++ b/arch/risc-v/include/rv32m1/rv32m1ri5cy_irq.h @@ -25,7 +25,7 @@ * Included Files ****************************************************************************/ -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/common/riscv_exception.c b/arch/risc-v/src/common/riscv_exception.c index 9819154688..421e95aa88 100644 --- a/arch/risc-v/src/common/riscv_exception.c +++ b/arch/risc-v/src/common/riscv_exception.c @@ -33,13 +33,12 @@ #include #include #include -#include +#include #include "riscv_arch.h" #include "riscv_internal.h" -#ifdef CONFIG_DEBUG_INFO -static const char *g_reasons_str[MCAUSE_MAX_EXCEPTION + 1] = +static const char *g_reasons_str[RISCV_MAX_EXCEPTION + 1] = { "Instruction address misaligned", "Instruction access fault", @@ -58,7 +57,6 @@ static const char *g_reasons_str[MCAUSE_MAX_EXCEPTION + 1] = "Reserved", "Store/AMO page fault" }; -#endif /**************************************************************************** * Public Functions @@ -74,21 +72,19 @@ static const char *g_reasons_str[MCAUSE_MAX_EXCEPTION + 1] = void riscv_exception(uintptr_t mcause, uintptr_t *regs) { - uintptr_t cause = mcause & MCAUSE_INTERRUPT_MASK; + uintptr_t cause = mcause & RISCV_IRQ_MASK; -#ifdef CONFIG_DEBUG_INFO - if (mcause > MCAUSE_MAX_EXCEPTION) + if (mcause > RISCV_MAX_EXCEPTION) { - _alert("EXCEPTION: Unknown. MCAUSE: %08" PRIx32 "\n", cause); + _alert("EXCEPTION: Unknown. MCAUSE: %" PRIxREG "\n", cause); } else { - _alert("EXCEPTION: %s. MCAUSE: %08" PRIx32 "\n", + _alert("EXCEPTION: %s. MCAUSE: %" PRIxREG "\n", g_reasons_str[cause], cause); } -#endif - _alert("PANIC!!! Exception = %08" PRIx32 "\n", cause); + _alert("PANIC!!! Exception = %" PRIxREG "\n", cause); up_irq_save(); CURRENT_REGS = regs; PANIC(); diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c index d91c8c1e13..f225f5972d 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_irq.c +++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c @@ -34,7 +34,6 @@ #include #include -#include #include "riscv_internal.h" #include "hardware/esp32c3_interrupt.h" @@ -378,8 +377,8 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs) int irq; uintptr_t *mepc = regs; - if (((MCAUSE_INTERRUPT & mcause) == 0) && - (mcause != MCAUSE_ECALL_M)) + if (((RISCV_IRQ_BIT & mcause) == 0) && + (mcause != RISCV_IRQ_ECALLM)) { #ifdef CONFIG_ESP32C3_EXCEPTION_ENABLE_CACHE if (!spi_flash_cache_enabled()) @@ -406,9 +405,9 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs) board_autoled_on(LED_INIRQ); - if ((MCAUSE_INTERRUPT & mcause) != 0) + if ((RISCV_IRQ_BIT & mcause) != 0) { - uint8_t cpuint = mcause & MCAUSE_INTERRUPT_MASK; + uint8_t cpuint = mcause & RISCV_IRQ_MASK; DEBUGASSERT(cpuint <= ESP32C3_CPUINT_MAX); @@ -427,7 +426,7 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs) } else { - if (mcause == MCAUSE_ECALL_M) + if (mcause == RISCV_IRQ_ECALLM) { *mepc += 4; irq_dispatch(ESP32C3_IRQ_ECALL_M, regs);