arch/mips/src/pic32mz/pic32mz-dma.c: Make the DMA interrupt event configurable when setting up a transfer. This allows changing the event without deallocating a channel first. Clear the DMA interrupt flag when the ISR is called. Change some misleading names.
This commit is contained in:
Ouss4
Gregory Nutt
parent
afb40d87fb
commit
b853a5c750
@ -66,7 +66,7 @@
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/* Convert a virtual address to a physical address */
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#define VIRT2PHY(a) ((a) & 0x1FFFFFFF)
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#define PHYS_ADDR(va) ((uint32_t)(va) & 0x1fffffff)
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/****************************************************************************
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* Private Types
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@ -137,12 +137,12 @@ static inline void pic32mz_dma_abortirq(FAR struct pic32mz_dmach_s *dmach,
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static inline void pic32mz_dma_forceabort(FAR struct pic32mz_dmach_s *dmach);
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static inline void pic32mz_dma_intctrl(FAR struct pic32mz_dmach_s *dmach,
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uint32_t cfg);
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uint8_t cfg);
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static inline void pic32mz_dma_intclr(FAR struct pic32mz_dmach_s *dmach);
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static int pic32mz_dma_interrupt(int irq, void *context, FAR void *arg);
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static void pic32mz_dma_mode(FAR struct pic32mz_dmach_s *dmach,
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enum pic32mz_dma_chmode_e mode);
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uint8_t mode);
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static void pic32mz_dma_config(FAR struct pic32mz_dmach_s *dmach,
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FAR const struct pic32mz_dma_chcfg_s *cfg);
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@ -370,7 +370,7 @@ static inline void pic32mz_dma_priority(FAR struct pic32mz_dmach_s *dmach,
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static inline void pic32mz_dma_srcaddr(FAR struct pic32mz_dmach_s *dmach,
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uint32_t addr)
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{
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pic32mz_dma_putreg(dmach, PIC32MZ_DMACH_SSA_OFFSET, VIRT2PHY(addr));
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pic32mz_dma_putreg(dmach, PIC32MZ_DMACH_SSA_OFFSET, PHYS_ADDR(addr));
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}
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/****************************************************************************
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@ -384,7 +384,7 @@ static inline void pic32mz_dma_srcaddr(FAR struct pic32mz_dmach_s *dmach,
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static inline void pic32mz_dma_destaddr(FAR struct pic32mz_dmach_s *dmach,
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uint32_t addr)
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{
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pic32mz_dma_putreg(dmach, PIC32MZ_DMACH_DSA_OFFSET, VIRT2PHY(addr));
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pic32mz_dma_putreg(dmach, PIC32MZ_DMACH_DSA_OFFSET, PHYS_ADDR(addr));
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}
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/****************************************************************************
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@ -522,7 +522,7 @@ static inline void pic32mz_dma_intclr(FAR struct pic32mz_dmach_s *dmach)
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****************************************************************************/
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static inline void pic32mz_dma_intctrl(FAR struct pic32mz_dmach_s *dmach,
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uint32_t cfg)
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uint8_t cfg)
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{
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/* Clear all interrupts flags */
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@ -535,7 +535,8 @@ static inline void pic32mz_dma_intctrl(FAR struct pic32mz_dmach_s *dmach,
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/* Enable the interrupts requested. */
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pic32mz_dma_putreg(dmach, PIC32MZ_DMACH_INTSET_OFFSET, cfg);
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pic32mz_dma_putreg(dmach, PIC32MZ_DMACH_INTSET_OFFSET,
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cfg << DMACH_INT_EN_SHIFT);
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}
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/****************************************************************************
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@ -564,6 +565,7 @@ static int pic32mz_dma_interrupt(int irq, void *context, FAR void *arg)
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/* Clear the interrupt flags. */
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up_clrpend_irq(dmach->irq);
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pic32mz_dma_intclr(dmach);
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/* Invoke the callback. */
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@ -585,7 +587,7 @@ static int pic32mz_dma_interrupt(int irq, void *context, FAR void *arg)
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****************************************************************************/
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static void pic32mz_dma_mode(FAR struct pic32mz_dmach_s *dmach,
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enum pic32mz_dma_chmode_e mode)
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uint8_t mode)
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{
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if (mode & PIC32MZ_DMA_MODE_BASIC)
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{
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@ -615,21 +617,17 @@ static void pic32mz_dma_config(FAR struct pic32mz_dmach_s *dmach,
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/* Set the channel's start and abort IRQs if they are specified */
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if (cfg->startirq != PIC32MZ_DMA_NOEVENT)
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if (cfg->startirq != PIC32MZ_DMA_NOIRQ)
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{
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pic32mz_dma_startirq(dmach, cfg->startirq);
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}
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if (cfg->abortirq != PIC32MZ_DMA_NOEVENT)
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if (cfg->abortirq != PIC32MZ_DMA_NOIRQ)
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{
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pic32mz_dma_abortirq(dmach, cfg->abortirq);
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}
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/* Set the interrupt event(s) */
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pic32mz_dma_intctrl(dmach, cfg->event);
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/* Set the cahnnel's mode */
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/* Set the channel's mode */
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pic32mz_dma_mode(dmach, cfg->mode);
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@ -909,10 +907,14 @@ int pic32mz_dma_xfrsetup(DMA_HANDLE handle,
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/* Set transfer size (source, destination and cell) */
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pic32mz_dma_srcsize(dmach, cfg->srcsize);
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pic32mz_dma_srcsize(dmach, cfg->srcsize);
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pic32mz_dma_destsize(dmach, cfg->destsize);
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pic32mz_dma_cellsize(dmach, cfg->cellsize);
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/* Set the interrupt event(s) */
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pic32mz_dma_intctrl(dmach, cfg->event);
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return OK;
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}
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@ -939,9 +941,9 @@ int pic32mz_dma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg)
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pic32mz_dma_enable(dmach);
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/* If no event is set to start the channel, force it */
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/* If no irq is set to start the channel, force it */
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if (dmach->cfg.startirq == PIC32MZ_DMA_NOEVENT)
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if (dmach->cfg.startirq == PIC32MZ_DMA_NOIRQ)
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{
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pic32mz_dma_forcestart(dmach);
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}
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@ -60,7 +60,7 @@
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*
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* If a start irq is set this function will only enable the channel.
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* The transfer will be controlled by the start irq.
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* If no start irq is specified then the a force start is performed.
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* If start irq is set to PIC32MZ_DMA_NOIRQ then a force start is performed.
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*
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* 4. Stop and free the channel
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*
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@ -80,31 +80,16 @@
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#include <sys/types.h>
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#include <stdint.h>
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#include "hardware/pic32mz-dma.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Interrupt type arguments for pic32mz_dma_intctrl. */
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/* This is used when setting a channel with no start/abort irq */
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#define PIC32MZ_DMA_INT_SRCDONE DMACH_INT_CHSDIE
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#define PIC32MZ_DMA_INT_SRCHALF DMACH_INT_CHSHIE
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#define PIC32MZ_DMA_INT_DESTDONE DMACH_INT_CHDDIE
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#define PIC32MZ_DMA_INT_DESTHALF DMACH_INT_CHDHIE
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#define PIC32MZ_DMA_INT_BLOCKDONE DMACH_INT_CHBCIE
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#define PIC32MZ_DMA_INT_CELLDONE DMACH_INT_CHCCIE
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#define PIC32MZ_DMA_INT_ABORT DMACH_INT_CHTAIE
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#define PIC32MZ_DMA_INT_ERR DMACH_INT_CHERIE
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#define PIC32MZ_DMA_INT_DISABLE (0)
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/* This is used when setting a channel with no start/abort event */
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#define PIC32MZ_DMA_NOEVENT (NR_IRQS + 1)
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#define PIC32MZ_DMA_NOIRQ (NR_IRQS + 1)
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/*******************************************************************************
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* Public Types
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*
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******************************************************************************/
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#ifndef __ASSEMBLY__
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@ -112,6 +97,8 @@
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typedef FAR void *DMA_HANDLE;
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typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
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/* DMA channel modes, arguments for pic32mz_dma_mode. */
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enum pic32mz_dma_chmode_e
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{
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PIC32MZ_DMA_MODE_BASIC = 1 << 0U, /* Basic transfert mode */
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@ -121,15 +108,29 @@ enum pic32mz_dma_chmode_e
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PIC32MZ_DMA_MODE_SFM = 1 << 4U /* Special Function Module mode */
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};
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/* Interrupt type arguments for pic32mz_dma_intctrl. */
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enum pic32Mz_dma_event_e
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{
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PIC32MZ_DMA_INT_DISABLE = 0U,
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PIC32MZ_DMA_INT_ADDRERR = 1 << 0U, /* Address error interrupt */
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PIC32MZ_DMA_INT_ABORT = 1 << 1U, /* Transfer abort interrupt */
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PIC32MZ_DMA_INT_CELLDONE = 1 << 2U, /* Cell transfer complete interrupt */
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PIC32MZ_DMA_INT_BLOCKDONE = 1 << 3U, /* Block transfer complete interrupt */
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PIC32MZ_DMA_INT_DESTHALF = 1 << 4U, /* Destination half full interrup t*/
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PIC32MZ_DMA_INT_DESTDONE = 1 << 5U, /* Destination done interrupt */
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PIC32MZ_DMA_INT_SRCHALF = 1 << 6U, /* Source half full interrupt */
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PIC32MZ_DMA_INT_SRCDONE = 1 << 7U /* Source done interrupt */
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};
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/* This structure holds the channel's configuration */
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struct pic32mz_dma_chcfg_s
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{
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uint8_t priority; /* Channel's priority (0..3) */
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uint8_t startirq; /* Start event */
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uint8_t abortirq; /* Abort event */
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uint8_t event; /* Interrupt event */
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enum pic32mz_dma_chmode_e mode; /* Channel's mode of operation */
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uint8_t priority; /* Channel's priority (0..3) */
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uint8_t startirq; /* Start event */
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uint8_t abortirq; /* Abort event */
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uint8_t mode; /* Channel's modes (enum pic32mz_dma_chmode_e) */
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};
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/* This structure holds a transfer's configuration */
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@ -141,6 +142,7 @@ struct pic32mz_dma_xfrcfg_s
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uint16_t srcsize; /* Source size */
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uint16_t destsize; /* Destination size */
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uint16_t cellsize; /* Cell size */
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uint8_t event; /* Interrupt events (enum pic32mz_dma_event_e) */
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};
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/* The following is used for sampling DMA registers when CONFIG_DEBUG_DMA
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