SAMA5: Fix SAMA5 so that interpretation of BMS bit is correct. From David Sidrane
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@ -7128,4 +7128,6 @@
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* arch/arm/src/sama5/sam_boot.c, sam_irq.c, and chip/sama5d3x_memorymap.h:
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When booting from SDRAM, don't relocated vectors to ISRAM. Instead,
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just set the VBAR register to address of the vectors in SDRAM.
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* arch/arm/src/sama5/sam_clockconfig.c: BMS Fixed to match what the HW
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does. From David Sidrane (2014-4-3).
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@ -482,10 +482,10 @@ static inline void sam_usbclockconfig(void)
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* configured to work in different ways using the BMS pin and the contents
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* of the Boot Sequence Configuration Register (BSC_CR).
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*
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* If the BMS_BIT is read "1", then the first level bootloader will
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* If the BMS_BIT is read "0", then the first level bootloader will
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* support execution of code in the memory connected to CS0 on the EBI
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* interface (presumably NOR flash). The following sequence is performed
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* by the first level bootloader if BMS_BIT is "1":
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* by the first level bootloader if BMS_BIT is "0":
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*
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* - The main clock is the on-chip 12 MHz RC oscillator,
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* - The Static Memory Controller is configured with timing allowing
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@ -504,7 +504,7 @@ static inline void sam_usbclockconfig(void)
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* - Program and Start the PLL
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* - Switch the system clock to the new value
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*
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* If the BMS_BIT is read "0", then the first level bootloader will
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* If the BMS_BIT is read "1", then the first level bootloader will
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* perform:
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*
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* - Basic chip initialization: XTal or external clock frequency
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@ -545,9 +545,9 @@ void sam_clockconfig(void)
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*/
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#ifdef CONFIG_SAMA5_BOOT_CS0FLASH
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/* Yes... did we get here via the first level bootloader? */
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/* Yes... did we get here via the first level bootloader? */
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if ((getreg32(SAM_SFR_EBICFG) & SFR_EBICFG_BMS) != 0)
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if ((getreg32(SAM_SFR_EBICFG) & SFR_EBICFG_BMS) == 0)
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{
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/* Yes.. Perform the following operations in order to complete the
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* clocks and SMC timings configuration to run at a higher clock
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