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SAMA5: Fix SAMA5 so that interpretation of BMS bit is correct. From David Sidrane

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This commit is contained in:
Gregory Nutt 2014-04-03 15:47:34 -06:00
parent 8d1781437d
commit b884ab50f4
2 changed files with 7 additions and 5 deletions
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2
ChangeLog
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@ -7128,4 +7128,6 @@
* arch/arm/src/sama5/sam_boot.c, sam_irq.c, and chip/sama5d3x_memorymap.h: * arch/arm/src/sama5/sam_boot.c, sam_irq.c, and chip/sama5d3x_memorymap.h:
When booting from SDRAM, don't relocated vectors to ISRAM. Instead, When booting from SDRAM, don't relocated vectors to ISRAM. Instead,
just set the VBAR register to address of the vectors in SDRAM. just set the VBAR register to address of the vectors in SDRAM.
* arch/arm/src/sama5/sam_clockconfig.c: BMS Fixed to match what the HW
does. From David Sidrane (2014-4-3).

10
arch/arm/src/sama5/sam_clockconfig.c
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@ -482,10 +482,10 @@ static inline void sam_usbclockconfig(void)
* configured to work in different ways using the BMS pin and the contents * configured to work in different ways using the BMS pin and the contents
* of the Boot Sequence Configuration Register (BSC_CR). * of the Boot Sequence Configuration Register (BSC_CR).
* *
* If the BMS_BIT is read "1", then the first level bootloader will * If the BMS_BIT is read "0", then the first level bootloader will
* support execution of code in the memory connected to CS0 on the EBI * support execution of code in the memory connected to CS0 on the EBI
* interface (presumably NOR flash). The following sequence is performed * interface (presumably NOR flash). The following sequence is performed
* by the first level bootloader if BMS_BIT is "1": * by the first level bootloader if BMS_BIT is "0":
* *
* - The main clock is the on-chip 12 MHz RC oscillator, * - The main clock is the on-chip 12 MHz RC oscillator,
* - The Static Memory Controller is configured with timing allowing * - The Static Memory Controller is configured with timing allowing
@ -504,7 +504,7 @@ static inline void sam_usbclockconfig(void)
* - Program and Start the PLL * - Program and Start the PLL
* - Switch the system clock to the new value * - Switch the system clock to the new value
* *
* If the BMS_BIT is read "0", then the first level bootloader will * If the BMS_BIT is read "1", then the first level bootloader will
* perform: * perform:
* *
* - Basic chip initialization: XTal or external clock frequency * - Basic chip initialization: XTal or external clock frequency
@ -545,9 +545,9 @@ void sam_clockconfig(void)
*/ */
#ifdef CONFIG_SAMA5_BOOT_CS0FLASH #ifdef CONFIG_SAMA5_BOOT_CS0FLASH
/* Yes... did we get here via the first level bootloader? */ /* Yes... did we get here via the first level bootloader? */
if ((getreg32(SAM_SFR_EBICFG) & SFR_EBICFG_BMS) != 0) if ((getreg32(SAM_SFR_EBICFG) & SFR_EBICFG_BMS) == 0)
{ {
/* Yes.. Perform the following operations in order to complete the /* Yes.. Perform the following operations in order to complete the
* clocks and SMC timings configuration to run at a higher clock * clocks and SMC timings configuration to run at a higher clock