Add framework for Spark Core board support. The initial commit is a clone of the Maple Mini and still needs Spark customizations
This commit is contained in:
Gregory Nutt
parent
afa475e948
commit
b885459624
@ -478,12 +478,9 @@
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F103 Medium Density Family *************************************************/
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/* STM32F103RB is in the Medium-density performance line and is provided in 64 pin
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* packages with 128K Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces
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*/
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/* STM32 F103 Medium Density Performance Line ***************************************/
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#elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6)
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#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB)
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# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
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# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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@ -491,17 +488,88 @@
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# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* General timers TIM2,3,4 */
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# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */
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# define STM32_NDMA 1 /* DMA1 */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 1 /* DMA1, 7 channels */
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# define STM32_NSPI 1 /* SPI1 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 2 /* USART1-2 */
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# define STM32_NI2C 1 /* I2C1 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 26 /* GPIOA-E */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB)
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# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
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# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* General timers TIM2,3,4 */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 1 /* DMA1, 7 channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S (?) */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 37 /* GPIOA-C */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB)
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# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
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# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* General timers TIM2,3,4 */
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# define STM32_NBTIM 0 /* No basic timers */
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# define STM32_NDMA 1 /* DMA1, 7 channels */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* bxCAN1 */
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@ -517,37 +585,6 @@
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32F103C8, STM32F103CB (Medium-density performance line and is provided in 48 pin package) */
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#elif defined(CONFIG_ARCH_CHIP_STM32F103C8)
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* General timers TIM2,3,4 */
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# define STM32_NBTIM 0 /* No basic timer */
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# define STM32_NDMA 1 /* DMA1 */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 37 /* GPIOA-C */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F103 High Density Family ***************************************************/
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/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and
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* differ only in the available FLASH and SRAM.
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@ -138,6 +138,8 @@
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DMACH_FLAG_MEMCHUNKSIZE_1)
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#endif
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#define ADC_CLOCK_MAX 20000000 /* Max ADC Clock Frequency (Hz) */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -255,8 +255,57 @@ config ARCH_CHIP_STM32F103C8
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select STM32_PERFORMANCELINE
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select STM32_MEDIUMDENSITY
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config ARCH_CHIP_STM32F103RBT6
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bool "STM32F103RBT6"
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config ARCH_CHIP_STM32F103T8
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bool "STM32F103T8"
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select ARCH_CORTEXM3
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select STM32_STM32F10XX
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select STM32_PERFORMANCELINE
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select STM32_MEDIUMDENSITY
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config ARCH_CHIP_STM32F103TB
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bool "STM32F103TB"
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select ARCH_CORTEXM3
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select STM32_STM32F10XX
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select STM32_PERFORMANCELINE
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select STM32_MEDIUMDENSITY
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config ARCH_CHIP_STM32F103C8
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bool "STM32F103C8"
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select ARCH_CORTEXM3
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select STM32_STM32F10XX
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select STM32_PERFORMANCELINE
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select STM32_MEDIUMDENSITY
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config ARCH_CHIP_STM32F103CB
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bool "STM32F103CB"
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select ARCH_CORTEXM3
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select STM32_STM32F10XX
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select STM32_PERFORMANCELINE
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select STM32_MEDIUMDENSITY
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config ARCH_CHIP_STM32F103R8
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bool "STM32F103R8"
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select ARCH_CORTEXM3
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select STM32_STM32F10XX
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select STM32_PERFORMANCELINE
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select STM32_MEDIUMDENSITY
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config ARCH_CHIP_STM32F103RB
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bool "STM32F103RB"
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select ARCH_CORTEXM3
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select STM32_STM32F10XX
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select STM32_PERFORMANCELINE
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select STM32_MEDIUMDENSITY
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config ARCH_CHIP_STM32F103V8
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bool "STM32F103V8"
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select ARCH_CORTEXM3
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select STM32_STM32F10XX
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select STM32_PERFORMANCELINE
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select STM32_MEDIUMDENSITY
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config ARCH_CHIP_STM32F103VB
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bool "STM32F103VB"
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select ARCH_CORTEXM3
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select STM32_STM32F10XX
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select STM32_PERFORMANCELINE
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@ -72,7 +72,8 @@
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/* STM32 F103 Low / Medium Density Family */
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# elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \
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defined(CONFIG_ARCH_CHIP_STM32F103C8) || \
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defined(CONFIG_ARCH_CHIP_STM32F103RBT6)
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defined(CONFIG_ARCH_CHIP_STM32F103CB) || \
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defined(CONFIG_ARCH_CHIP_STM32F103RB)
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# include "chip/stm32f103c_pinmap.h"
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/* STM32 F103 High Density Family */
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