Flesh out m8s12 serial driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3306 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
5a52fca179
commit
b88f6027d2
@ -132,9 +132,9 @@
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.globl up_lowsetup
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.type up_lowsetup, function
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up_lowsetup:
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#ifdef CONFIG_HCS12_SERIALMON
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rts
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#else
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#ifdef HAVE_SERIAL_CONSOLE
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#ifndef CONFIG_HCS12_SERIALMON
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/* Disable the console */
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ldab #0
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@ -158,9 +158,10 @@ up_lowsetup:
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ldab #(SCI_CR2_RE|SCI_CR2_TE)
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stab (HCS12_CONSOLE_BASE+HCS12_SCI_CR2_OFFSET)
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rts
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#endif
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#endif /* CONFIG_HCS12_SERIALMON */
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#endif /* HAVE_SERIAL_CONSOLE */
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rts
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.size up_lowsetup, . - up_lowsetup
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/**************************************************************************
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@ -171,12 +172,13 @@ up_lowsetup:
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.global up_lowputc
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.type up_lowputc, function
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up_lowputc:
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#ifdef HAVE_SERIAL_CONSOLE
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#ifdef CONFIG_HCS12_SERIALMON
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jmp PutChar
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#else
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# if HCS12_CONSOLE_BITS == 9
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#if HCS12_CONSOLE_BITS == 9
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staa 1, -sp
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# endif
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#endif /* HCS12_CONSOLE_BITS == 9 */
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/* Wait for the transmit data register to be available (TRDE==1) */
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@ -187,7 +189,7 @@ up_lowputc:
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/* Then write the byte to the transmit data register */
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# if HCS12_CONSOLE_BITS == 9
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#if HCS12_CONSOLE_BITS == 9
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ldaa 1, sp+
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bita #(0x01)
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bne .L8bit
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@ -197,9 +199,14 @@ up_lowputc:
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ldaa #0
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.Lwrdrh:
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staa (HCS12_CONSOLE_BASE+HCS12_SCI_DRH_OFFSET)
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# endif
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#endif /* HCS12_CONSOLE_BITS == 9 */
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stab (HCS12_CONSOLE_BASE+HCS12_SCI_DRL_OFFSET)
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rts
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#endif
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#endif /* !CONFIG_HCS12_SERIALMON */
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#else
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rts
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#endif /* HAVE_SERIAL_CONSOLE */
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.size up_lowputc, . - up_lowputc
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.end
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@ -113,8 +113,9 @@
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#define SCI_CR2_TE (1 << 3) /* Bit 3: Transmitter Enable */
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#define SCI_CR2_ILIE (1 << 4) /* Bit 4: Idle Line Interrupt Enable */
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#define SCI_CR2_RIE (1 << 5) /* Bit 5: Receiver Full Interrupt Enable Bit */
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#define SCI_CR2_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt En */
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#define SCI_CR2_TIE (1 << 7) /* Bit 7: Transmitter Interrupt Ena */
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#define SCI_CR2_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
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#define SCI_CR2_TIE (1 << 7) /* Bit 7: Transmitter Interrupt Enable */
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#define SCI_CR2_ALLINTS 0xf0
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/* SCI Status Register 1 Bit-Field Definitions */
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@ -40,63 +40,689 @@
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#include <nuttx/config.h>
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#include "up_internal.h"
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#include "m9s12_serial.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Some sanity checks *******************************************************/
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/* Configuration ************************************************************/
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/* Is there an SCI enabled? */
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#if !defined(CONFIG_HCS12_SCI0) && !defined(CONFIG_HCS12_SCI1)
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# undef HAVE_SERIAL
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#else
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# define HAVE_SERIAL 1
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#endif
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/* Is there a serial console? Need to have (1) at least SCI enabled, and (2)
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* serial console and file descriptors selected in the configuration
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/* Is there a serial console? Need to have (1) at least SCI enabled, (2)
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* a serial console defined on an enabled SCI, and (3) serial console and
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* file descriptors selected in the configuration. This driver is also
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* disabled if we are using ROM-resident serial I/O
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*/
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#if defined(HAVE_SERIAL) && defined(CONFIG_USE_SERIALDRIVER)
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# if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_HCS12_SCI0)
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# undef CONFIG_SCI1_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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# elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_HCS12_SCI1)
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# undef CONFIG_SCI0_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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# else
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# undef CONFIG_SCI0_SERIAL_CONSOLE
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# undef CONFIG_SCI1_SERIAL_CONSOLE
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# undef HAVE_SERIAL_CONSOLE
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# endif
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#else
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# undef CONFIG_SCI0_SERIAL_CONSOLE
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# undef CONFIG_SCI1_SERIAL_CONSOLE
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# undef HAVE_SERIAL_CONSOLE
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#if !defined(HAVE_SERIAL_CONSOLE) || !defined(CONFIG_USE_SERIALDRIVER) || \
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defined(CONFIG_HCS12_SERIALMON)
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# undef CONFIG_USE_SERIALDRIVER
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# undef CONFIG_USE_EARLYSERIALINIT
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#endif
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#ifdef CONFIG_USE_SERIALDRIVER
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/* Yes, which is ttyS0 and which is ttyS1 */
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#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_sci0port /* SCI0 is console */
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# define TTYS0_DEV g_sci0port /* SCI0 is ttyS0 */
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# ifndef CONFIG_SCI1_DISABLE
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# define TTYS1_DEV g_sci1port /* SCI1 is ttyS1 */
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# else
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# undef TTYS1_DEV /* No ttyS1 */
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# endif
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#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_sci1port /* SCI1 is console */
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# define TTYS0_DEV g_sci1port /* SCI1 is ttyS0 */
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# ifndef CONFIG_SCI0_DISABLE
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# define TTYS1_DEV g_sci0port /* SCI0 is ttyS1 */
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# else
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# undef TTYS1_DEV /* No ttyS1 */
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# endif
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#elif !defined(CONFIG_SCI0_DISABLE)
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# undef CONSOLE_DEV /* No console device */
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# define TTYS0_DEV g_sci1port /* SCI1 is ttyS0 */
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# ifndef CONFIG_SCI1_DISABLE
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# define TTYS1_DEV g_sci1port /* SCI1 is ttyS1 */
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# else
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# undef TTYS1_DEV /* No ttyS1 */
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# endif
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#elif !defined(CONFIG_SCI1_DISABLE)
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# undef CONSOLE_DEV /* No console device */
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# define TTYS0_DEV g_sci1port /* SCI1 is ttyS0 */
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# undef TTYS1_DEV /* No ttyS1 */
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#else
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# error "No valid TTY devices"
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# undef CONSOLE_DEV /* No console device */
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# undef TTYS0_DEV /* No ttyS0 */
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# undef TTYS1_DEV /* No ttyS1 */
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct up_dev_s
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{
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uint32_t baud; /* Configured baud */
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uint16_t scibase; /* Base address of SCI registers */
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uint8_t im; /* Saved CR1 interrupt enables */
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uint8_t sr1; /* Saved error status flags */
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uint8_t irq; /* IRQ associated with this SCI */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (8 or 9) */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static int up_setup(struct uart_dev_s *dev);
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static void up_shutdown(struct uart_dev_s *dev);
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static int up_attach(struct uart_dev_s *dev);
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static void up_detach(struct uart_dev_s *dev);
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static int up_interrupt(int irq, void *context);
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static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
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static int up_receive(struct uart_dev_s *dev, uint32_t *status);
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static void up_rxint(struct uart_dev_s *dev, bool enable);
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static bool up_rxavailable(struct uart_dev_s *dev);
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static void up_send(struct uart_dev_s *dev, int ch);
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static void up_txint(struct uart_dev_s *dev, bool enable);
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static bool up_txready(struct uart_dev_s *dev);
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static bool up_txempty(struct uart_dev_s *dev);
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/****************************************************************************
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* Private Variables
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****************************************************************************/
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struct uart_ops_s g_sci_ops =
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{
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.setup = up_setup,
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.shutdown = up_shutdown,
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.attach = up_attach,
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.detach = up_detach,
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.ioctl = up_ioctl,
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.receive = up_receive,
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.rxint = up_rxint,
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.rxavailable = up_rxavailable,
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.send = up_send,
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.txint = up_txint,
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.txready = up_txready,
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.txempty = up_txempty,
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};
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/* I/O buffers */
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#ifndef CONFIG_SCI0_DISABLE
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static char g_sci0rxbuffer[CONFIG_SCI0_RXBUFSIZE];
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static char g_sci0txbuffer[CONFIG_SCI0_TXBUFSIZE];
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#endif
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#ifndef CONFIG_SCI1_DISABLE
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static char g_sci1rxbuffer[CONFIG_SCI1_RXBUFSIZE];
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static char g_sci1txbuffer[CONFIG_SCI1_TXBUFSIZE];
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#endif
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/* This describes the state of the sci0 port. */
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#ifndef CONFIG_SCI0_DISABLE
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static struct up_dev_s g_sci0priv =
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{
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.baud = CONFIG_SCI0_BAUD,
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.uartbase = HCS12_SCI0_BASE,
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.irq = HCS12_IRQ_VSCI0,
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.parity = CONFIG_SCI0_PARITY,
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.bits = CONFIG_SCI0_BITS,
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};
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static uart_dev_t g_sci0port =
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{
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.recv =
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{
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.size = CONFIG_SCI0_RXBUFSIZE,
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.buffer = g_sci0rxbuffer,
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},
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.xmit =
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{
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.size = CONFIG_SCI0_TXBUFSIZE,
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.buffer = g_sci0txbuffer,
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},
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.ops = &g_sci_ops,
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.priv = &g_sci0priv,
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};
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#endif
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/* This describes the state of the sci1 port. */
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#ifndef CONFIG_SCI1_DISABLE
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static struct up_dev_s g_sci1priv =
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{
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.baud = CONFIG_SCI1_BAUD,
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.uartbase = HCS12_SCI1_BASE,
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.irq = HCS12_IRQ_VSCI1,
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.parity = CONFIG_SCI1_PARITY,
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.bits = CONFIG_SCI1_BITS,
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};
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static uart_dev_t g_sci1port =
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{
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.recv =
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{
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.size = CONFIG_SCI1_RXBUFSIZE,
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.buffer = g_sci1rxbuffer,
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},
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.xmit =
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{
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.size = CONFIG_SCI1_TXBUFSIZE,
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.buffer = g_sci1txbuffer,
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},
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.ops = &g_sci_ops,
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.priv = &g_sci1priv,
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};
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_serialin
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****************************************************************************/
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static inline uint8_t up_serialin(struct up_dev_s *priv, int offset)
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{
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return getreg8(priv->uartbase + offset);
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}
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/****************************************************************************
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* Name: up_serialout
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****************************************************************************/
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static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value)
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{
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putreg8(value, priv->uartbase + offset);
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}
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/****************************************************************************
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* Name: up_setsciint
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****************************************************************************/
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static inline void up_setsciint(struct up_dev_s *priv)
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{
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uint8_t regval;
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regval = up_serialin(priv, HCS12_SCI_CR2_OFFSET);
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regval &= ~SCI_CR2_ALLINTS;
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regval |= priv->im;
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up_serialout(priv, HCS12_SCI_CR2_OFFSET, regval);
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}
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/****************************************************************************
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* Name: up_disablesciint
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****************************************************************************/
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static inline void up_disablesciint(struct up_dev_s *priv, uint8_t *im)
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{
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uint8_t regval;
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/* Return the current interrupt mask value */
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if (im)
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{
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*im = priv->im;
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}
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/* Disable all interrupts */
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priv->im = 0;
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up_setsciint(priv);
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}
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/****************************************************************************
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* Name: up_restoresciint
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****************************************************************************/
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static inline void up_restoresciint(struct up_dev_s *priv, uint32_t im)
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{
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priv->im = im & SCI_CR2_ALLINTS;
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up_setsciint(priv);
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}
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/****************************************************************************
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* Name: up_waittxnotfull
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****************************************************************************/
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#ifdef HAVE_CONSOLE
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static inline void up_waittxnotfull(struct up_dev_s *priv)
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{
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int tmp;
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/* Limit how long we will wait for the TX available condition */
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for (tmp = 1000 ; tmp > 0 ; tmp--)
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{
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/* Check Tx data register is empty */
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if ((up_serialin(priv, HCS12_SCI_SR1_OFFSET) & SCI_SR1_TDRE) != 0)
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{
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/* The Tx is empty... return */
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break;
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}
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}
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/* If we get here, then the wait has timed out and the Tx data register
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* remains full.
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*/
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}
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#endif
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/****************************************************************************
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* Name: up_setup
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*
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* Description:
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* Configure the SCI baud, bits, parity, fifos, etc. This method is called
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* the first time that the serial port is opened.
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*
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****************************************************************************/
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static int up_setup(struct uart_dev_s *dev)
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{
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struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
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#ifndef CONFIG_SUPPRESS_SCI_CONFIG
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uint8_t cr1;
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/* Calculate the BAUD divisor */
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tmp = SCIBR_VALUE(priv->baud);
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DEBUGASSERT(tmp < 0xff);
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/* Disable the SCI */
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up_serialout(priv, HCS12_SCI_CR1_OFFSET, 0);
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up_serialout(priv, HCS12_SCI_CR2_OFFSET, 0);
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/* Set the BAUD divisor */
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up_serialout(priv, HCS12_SCI_BDH_OFFSET, (uint8_t)(tmp >> 8));
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up_serialout(priv, HCS12_SCI_BDL_OFFSET, (uint8_t)(tmp & 0xff));
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/* Set up the SCICR1 register */
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cr1 = 0;
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if (priv->bits == 9)
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{
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cr1 |= SCI_CR1_M;
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}
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switch (priv->parity)
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{
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case 0:
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default:
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break;
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case 1:
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cr1 |= SCI_CR1_PE|SCI_CR1_PT;
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break;
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case 2:
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cr1 |= SCI_CR1_PE;
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break;
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}
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up_serialout(priv, HCS12_SCI_CR1_OFFSET, cr1);
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#endif
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/* Enable Rx interrupts from the SCI. We don't want Tx interrupts until we
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* have something to send. We will check for serial errors as part of Rx
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* interrupt processing. Interrupts won't be fully enabled until the
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* interrupt vector is attached.
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*/
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priv->im = SCI_CR2_RIE;
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/* Enable Rx and Tx */
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up_serialout(priv, HCS12_SCI_CR2_OFFSET, (SCI_CR2_RIE|SCI_CR2_TE|SCI_CR2_RE));
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return OK;
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}
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/****************************************************************************
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* Name: up_shutdown
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*
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* Description:
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* Disable the SCI. This method is called when the serial port is closed.
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*
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****************************************************************************/
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static void up_shutdown(struct uart_dev_s *dev)
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{
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struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
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up_disablesciint(priv, NULL);
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}
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/****************************************************************************
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* Name: up_attach
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*
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* Description:
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* Configure the SCI to operation in interrupt driven mode. This method is
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* called when the serial port is opened. Normally, this is just after the
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* the setup() method is called, however, the serial console may operate in
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* a non-interrupt driven mode during the boot phase.
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*
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* RX and TX interrupts are not enabled when by the attach method (unless the
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* hardware supports multiple levels of interrupt enabling). The RX and TX
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* interrupts are not enabled until the txint() and rxint() methods are called.
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*
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****************************************************************************/
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|
||||
static int up_attach(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
int ret;
|
||||
|
||||
/* Attach and enable the IRQ */
|
||||
|
||||
ret = irq_attach(priv->irq, up_interrupt);
|
||||
if (ret == OK)
|
||||
{
|
||||
/* Enable the interrupt (RX and TX interrupts are still disabled
|
||||
* in the SCI
|
||||
*/
|
||||
|
||||
up_enable_irq(priv->irq);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_detach
|
||||
*
|
||||
* Description:
|
||||
* Detach SCI interrupts. This method is called when the serial port is
|
||||
* closed normally just before the shutdown method is called. The
|
||||
* exception is the serial console which is never shutdown.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void up_detach(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
up_disable_irq(priv->irq);
|
||||
irq_detach(priv->irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_interrupt
|
||||
*
|
||||
* Description:
|
||||
* This is the SCI interrupt handler. It will be invoked
|
||||
* when an interrupt received on the 'irq' It should call
|
||||
* uart_transmitchars or uart_receivechar to perform the
|
||||
* appropriate data transfers. The interrupt handling logic\
|
||||
* must be able to map the 'irq' number into the approprite
|
||||
* uart_dev_s structure in order to call these functions.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int up_interrupt(int irq, void *context)
|
||||
{
|
||||
struct uart_dev_s *dev = NULL;
|
||||
struct up_dev_s *priv;
|
||||
int passes;
|
||||
bool handled;
|
||||
|
||||
#ifndef CONFIG_SCI0_DISABLE
|
||||
if (g_sci0priv.irq == irq)
|
||||
{
|
||||
dev = &g_sci0port;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifndef CONFIG_SCI1_DISABLE
|
||||
if (g_sci1priv.irq == irq)
|
||||
{
|
||||
dev = &g_sci1port;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
PANIC(OSERR_INTERNAL);
|
||||
}
|
||||
priv = (struct up_dev_s*)dev->priv;
|
||||
|
||||
/* Loop until there are no characters to be transferred or,
|
||||
* until we have been looping for a long time.
|
||||
*/
|
||||
|
||||
handled = true;
|
||||
for (passes = 0; passes < 256 && handled; passes++)
|
||||
{
|
||||
handled = false;
|
||||
|
||||
/* Get the masked SCI status and clear the pending interrupts. */
|
||||
|
||||
priv->sr1 = up_serialin(priv, HCS12_SCI_SR1_OFFSET);
|
||||
|
||||
/* Handle incoming, receive bytes */
|
||||
|
||||
if ((mis & SCI_SR1_RDRF) != 0)
|
||||
{
|
||||
/* Rx buffer not empty ... process incoming bytes */
|
||||
|
||||
uart_recvchars(dev);
|
||||
handled = true;
|
||||
}
|
||||
|
||||
/* Handle outgoing, transmit bytes */
|
||||
|
||||
if ((mis & SCI_SR1_TDRE) != 0)
|
||||
{
|
||||
/* Tx FIFO not full ... process outgoing bytes */
|
||||
|
||||
uart_xmitchars(dev);
|
||||
handled = true;
|
||||
}
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ioctl
|
||||
*
|
||||
* Description:
|
||||
* All ioctl calls will be routed through this method
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
{
|
||||
struct inode *inode = filep->f_inode;
|
||||
struct uart_dev_s *dev = inode->i_private;
|
||||
int ret = OK;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
/* Add IOCTL command support here */
|
||||
|
||||
default:
|
||||
ret = -ENOTTY;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_receive
|
||||
*
|
||||
* Description:
|
||||
* Called (usually) from the interrupt level to receive one
|
||||
* character from the SCI. Error bits associated with the
|
||||
* receipt are provided in the return 'status'.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
int rxd;
|
||||
|
||||
/* Return the error indications */
|
||||
|
||||
*status = (uint32_t)(priv->sr1 & ~SCI_CR2_ALLINTS);
|
||||
|
||||
/* Get the Rx data */
|
||||
|
||||
rxd = (int)up_serialin(priv, HCS12_SCI_DRL_OFFSET);
|
||||
if (priv->bits == 9)
|
||||
{
|
||||
if ((up_serialin(priv, HCS12_SCI_DRH_OFFSET) & SCI_DRH_R8) != 0)
|
||||
{
|
||||
rxd |= 0x0100;
|
||||
}
|
||||
}
|
||||
|
||||
return rxd;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_rxint
|
||||
*
|
||||
* Description:
|
||||
* Call to enable or disable RX interrupts
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void up_rxint(struct uart_dev_s *dev, bool enable)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
|
||||
if (enable)
|
||||
{
|
||||
/* Receive an interrupt when their is anything in the Rx FIFO (or an Rx
|
||||
* timeout occurs.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
priv->im |= SCI_CR2_RIE;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
priv->im &= ~SCI_CR2_RIE;
|
||||
}
|
||||
|
||||
up_setsciint(priv);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_rxavailable
|
||||
*
|
||||
* Description:
|
||||
* Return true if the receive fifo is not empty
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static bool up_rxavailable(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
return ((up_serialin(priv, HCS12_SCI_SR1_OFFSET) & SCI_SR1_RDRF) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_send
|
||||
*
|
||||
* Description:
|
||||
* This method will send one byte on the SCI
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void up_send(struct uart_dev_s *dev, int ch)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
uint8_t regval;
|
||||
|
||||
if (priv->bits == 9)
|
||||
{
|
||||
regval = up_serialin(priv, HCS12_SCI_DRH_OFFSET);
|
||||
if ((ch & 0x0100) == 0)
|
||||
{
|
||||
regval &= ~SCI_DRH_T8;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval |= SCI_DRH_T8;
|
||||
}
|
||||
up_serialout(priv, HCS12_SCI_DRH_OFFSET, regval);
|
||||
}
|
||||
|
||||
up_serialout(priv, HCS12_SCI_DRL_OFFSET, (uint8_t)(ch & 0xff));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_txint
|
||||
*
|
||||
* Description:
|
||||
* Call to enable or disable TX interrupts
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void up_txint(struct uart_dev_s *dev, bool enable)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
irqstate_t flags;
|
||||
|
||||
flags = irqsave();
|
||||
if (enable)
|
||||
{
|
||||
/* Set to receive an interrupt when the TX data register is empty */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
priv->im |= SCI_CR2_TIE;
|
||||
up_setsciint(priv);
|
||||
|
||||
/* Fake a TX interrupt */
|
||||
|
||||
uart_xmitchars(dev);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the TX interrupt */
|
||||
|
||||
priv->im &= ~SCI_CR2_TIE;
|
||||
up_setsciint(priv);
|
||||
}
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_txready
|
||||
*
|
||||
* Description:
|
||||
* Return true if the tranmsit fifo is not full
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static bool up_txready(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
return ((up_serialin(priv, HCS12_SCI_SR1_OFFSET) & SCI_SR1_TDRE) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_txempty
|
||||
*
|
||||
* Description:
|
||||
* Return true if the transmit fifo is empty
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static bool up_txempty(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
return ((up_serialin(priv, HCS12_SCI_SR1_OFFSET) & SCI_SR1_TC) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -114,7 +740,19 @@
|
||||
#ifdef CONFIG_USE_EARLYSERIALINIT
|
||||
void up_earlyserialinit(void)
|
||||
{
|
||||
#error "Serial support not-implemented"
|
||||
/* Disable all UARTS */
|
||||
|
||||
up_disablesciint(TTYS0_DEV.priv, NULL);
|
||||
#ifdef TTYS1_DEV
|
||||
up_disablesciint(TTYS1_DEV.priv, NULL);
|
||||
#endif
|
||||
|
||||
/* Configuration whichever one is the console */
|
||||
|
||||
#ifdef HAVE_CONSOLE
|
||||
CONSOLE_DEV.isconsole = true;
|
||||
up_setup(&CONSOLE_DEV);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -129,7 +767,18 @@ void up_earlyserialinit(void)
|
||||
|
||||
void up_serialinit(void)
|
||||
{
|
||||
#error "Serial support not-implemented"
|
||||
/* Register the console */
|
||||
|
||||
#ifdef HAVE_CONSOLE
|
||||
(void)uart_register("/dev/console", &CONSOLE_DEV);
|
||||
#endif
|
||||
|
||||
/* Register all UARTs */
|
||||
|
||||
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
|
||||
#ifdef TTYS1_DEV
|
||||
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -142,7 +791,28 @@ void up_serialinit(void)
|
||||
|
||||
int up_putc(int ch)
|
||||
{
|
||||
#error "Serial support not-implemented"
|
||||
#ifdef HAVE_CONSOLE
|
||||
struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
|
||||
uint32_t im;
|
||||
|
||||
up_disablesciint(priv, &im);
|
||||
up_waittxnotfull(priv);
|
||||
up_send(CONSOLE_DEV, ch);
|
||||
|
||||
/* Check for LF */
|
||||
|
||||
if (ch == '\n')
|
||||
{
|
||||
/* Add CR */
|
||||
|
||||
up_waittxnotfull(priv);
|
||||
up_send(CONSOLE_DEV, '\r');
|
||||
}
|
||||
|
||||
up_waittxnotfull(priv);
|
||||
up_restoresciint(priv, im);
|
||||
#endif
|
||||
return ch;
|
||||
}
|
||||
|
||||
#else /* CONFIG_USE_SERIALDRIVER */
|
||||
@ -158,6 +828,8 @@ int up_putc(int ch)
|
||||
int up_putc(int ch)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_LOWPUTC
|
||||
up_lowputc(ch);
|
||||
|
||||
/* Check for LF */
|
||||
|
||||
if (ch == '\n')
|
||||
@ -167,7 +839,6 @@ int up_putc(int ch)
|
||||
up_lowputc('\r');
|
||||
}
|
||||
|
||||
up_lowputc(ch);
|
||||
#endif
|
||||
return ch;
|
||||
}
|
||||
|
||||
@ -51,22 +51,63 @@
|
||||
/* Is there a SCI enabled? */
|
||||
|
||||
#if defined(CONFIG_SCI0_DISABLE) && defined(CONFIG_SCI1_DISABLE)
|
||||
# error "No SCIs enabled"
|
||||
# undef HAVE_SERIAL_DEVICE
|
||||
# warning "No SCIs enabled"
|
||||
#else
|
||||
# define HAVE_SERIAL_DEVICE 1
|
||||
#endif
|
||||
|
||||
/* Is there a serial console? */
|
||||
|
||||
#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && !defined(CONFIG_SCI0_DISABLE)
|
||||
# undef CONFIG_SCI1_SERIAL_CONSOLE
|
||||
# define HAVE_CONSOLE 1
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && !defined(CONFIG_SCI1_DISABLE)
|
||||
# undef CONFIG_SCI0_SERIAL_CONSOLE
|
||||
# define HAVE_CONSOLE 1
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#else
|
||||
# warning "No valid CONFIG_SCIn_SERIAL_CONSOLE Setting"
|
||||
# undef CONFIG_SCI0_SERIAL_CONSOLE
|
||||
# undef CONFIG_SCI1_SERIAL_CONSOLE
|
||||
# undef HAVE_CONSOLE
|
||||
# undef HAVE_SERIAL_CONSOLE
|
||||
#endif
|
||||
|
||||
/* Sanity checking */
|
||||
|
||||
#ifndef CONFIG_SCI0_DISABLE
|
||||
# ifndef CONFIG_SCI0_PARITY
|
||||
# warning "CONFIG_SCI0_PARITY not defined -- Assuming none"
|
||||
# define CONFIG_SCI0_PARITY 0
|
||||
# elif CONFIG_SCI0_PARITY != 0 && CONFIG_SCI0_PARITY != 2 && CONFIG_SCI0_PARITY != 2
|
||||
# error "CONFIG_SCI0_PARITY value not recognized"
|
||||
# endif
|
||||
# ifndef CONFIG_SCI0_BITS
|
||||
# warning "CONFIG_SCI0_BITS not defined -- Assuming 8"
|
||||
# define CONFIG_SCI0_BITS 8
|
||||
# elif CONFIG_SCI0_BITS != 8 && CONFIG_SCI0_BITS != 9
|
||||
# error "CONFIG_SCI0_BITS value not supported"
|
||||
# endif
|
||||
# if defined(CONFIG_SCI0_2STOP) && CONFIG_SCI0_2STOP != 0
|
||||
# error "Only a single stop bit is supported"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SCI1_DISABLE
|
||||
# ifndef CONFIG_SCI1_PARITY
|
||||
# warning "CONFIG_SCI1_PARITY not defined -- Assuming none"
|
||||
# define CONFIG_SCI1_PARITY 0
|
||||
# elif CONFIG_SCI1_PARITY != 0 && CONFIG_SCI1_PARITY != 2 && CONFIG_SCI1_PARITY != 2
|
||||
# error "CONFIG_SCI1_PARITY value not recognized"
|
||||
# endif
|
||||
# ifndef CONFIG_SCI1_BITS
|
||||
# warning "CONFIG_SCI1_BITS not defined -- Assuming 8"
|
||||
# define CONFIG_SCI1_BITS 8
|
||||
# elif CONFIG_SCI1_BITS != 8 && CONFIG_SCI1_BITS != 9
|
||||
# error "CONFIG_SCI1_BITS value not supported"
|
||||
# endif
|
||||
# if defined(CONFIG_SCI1_2STOP) && CONFIG_SCI1_2STOP != 0
|
||||
# error "Only a single stop bit is supported"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* BAUD *****************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user