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arhc: avr: nxstyle fixes

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nxstyle fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-31 07:05:28 +02:00 committed by Xiang Xiao
parent 3e76370919
commit b8db0014db
57 changed files with 1389 additions and 1097 deletions
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29
arch/avr/include/at32uc3/irq.h
View File

@ -38,6 +38,7 @@
****************************************************************************/ ****************************************************************************/
/* Configuration ************************************************************/ /* Configuration ************************************************************/
/* Configuration CONFIG_AVR32_GPIOIRQ must be selected to enable the overall /* Configuration CONFIG_AVR32_GPIOIRQ must be selected to enable the overall
* GPIO IRQ feature and CONFIG_AVR32_GPIOIRQSETA and/or * GPIO IRQ feature and CONFIG_AVR32_GPIOIRQSETA and/or
* CONFIG_AVR32_GPIOIRQSETB must be enabled to select GPIOs to support * CONFIG_AVR32_GPIOIRQSETB must be enabled to select GPIOs to support
@ -50,6 +51,7 @@
#endif #endif
/* IRQ numbers **************************************************************/ /* IRQ numbers **************************************************************/
/* Events. These exclude: /* Events. These exclude:
* *
* - The Reset event which vectors directly either to 0x8000:0000 (uc3a) or * - The Reset event which vectors directly either to 0x8000:0000 (uc3a) or
@ -90,17 +92,18 @@
* interrupts, and a Non-Maskable Interrupt (NMI)." * interrupts, and a Non-Maskable Interrupt (NMI)."
* *
* "The INTC supports up to 64 groups of interrupts. Each group can have up * "The INTC supports up to 64 groups of interrupts. Each group can have up
* to 32 interrupt request lines, these lines are connected to the peripherals. * to 32 interrupt request lines, these lines are connected to the
* Each group has an Interrupt Priority Register (IPR) and an Interrupt Request * peripherals.
* Register (IRR). The IPRs are used to assign a priority level and an autovector * Each group has an Interrupt Priority Register (IPR) and an Interrupt
* to each group, and the IRRs are used to identify the active interrupt request * Request Register (IRR). The IPRs are used to assign a priority level and
* within each group. If a group has only one interrupt request line, an active * an autovector to each group, and the IRRs are used to identify the active
* interrupt group uniquely identifies the active interrupt request line, and * interrupt request within each group. If a group has only one interrupt
* the corresponding IRR is not needed. The INTC also provides one Interrupt * request line, an active interrupt group uniquely identifies the active
* Cause Register (ICR) per priority level. These registers identify the group * interrupt request line, and the corresponding IRR is not needed. The INTC
* that has a pending interrupt of the corresponding priority level. If several * also provides one Interrupt Cause Register (ICR) per priority level.
* groups have a pending interrupt of the same level, the group with the lowest * These registers identify the group that has a pending interrupt of the
* number takes priority." * corresponding priority level. If several groups have a pending interrupt
* of the same level, the group with the lowest number takes priority."
*/ */
/* Only 19 groups (0-18) are used with the AT32UC3A/B: */ /* Only 19 groups (0-18) are used with the AT32UC3A/B: */
@ -171,6 +174,7 @@
#define AVR32_IRQ_USART0 47 /* 0 Universal Synchronous/Asynchronous #define AVR32_IRQ_USART0 47 /* 0 Universal Synchronous/Asynchronous
* Receiver/Transmitter 0 */ * Receiver/Transmitter 0 */
/* Group 6 */ /* Group 6 */
#define AVR32_IRQ_BASEIRQGRP6 48 #define AVR32_IRQ_BASEIRQGRP6 48
@ -178,6 +182,7 @@
#define AVR32_IRQ_USART1 48 /* 0 Universal Synchronous/Asynchronous #define AVR32_IRQ_USART1 48 /* 0 Universal Synchronous/Asynchronous
* Receiver/Transmitter 1 */ * Receiver/Transmitter 1 */
/* Group 7 */ /* Group 7 */
#define AVR32_IRQ_BASEIRQGRP7 49 #define AVR32_IRQ_BASEIRQGRP7 49
@ -259,6 +264,7 @@
#define NR_IRQS 60 #define NR_IRQS 60
/* GPIO IRQ Numbers *********************************************************/ /* GPIO IRQ Numbers *********************************************************/
/* These numbers correspond to GPIO port numbers that have interrupts /* These numbers correspond to GPIO port numbers that have interrupts
* enabled. These are all decoded by the AVR32_IRQ_GPIO interrupt handler. * enabled. These are all decoded by the AVR32_IRQ_GPIO interrupt handler.
* A lot of effort was made here to keep the number of IRQs to a minimum * A lot of effort was made here to keep the number of IRQs to a minimum
@ -493,7 +499,6 @@
# define __IRQ_GPIO_PB0 __IRQ_GPIO_PA31 # define __IRQ_GPIO_PB0 __IRQ_GPIO_PA31
#endif #endif
/* Up to 12 GPIO interrupts in PORTB0-11 */ /* Up to 12 GPIO interrupts in PORTB0-11 */
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000001) != 0 #if (CONFIG_AVR32_GPIOIRQSETB & 0x00000001) != 0

16
arch/avr/include/atmega/irq.h
View File

@ -124,14 +124,14 @@
#elif defined(CONFIG_ARCH_CHIP_ATMEGA2560) #elif defined(CONFIG_ARCH_CHIP_ATMEGA2560)
# define ATMEGA_IRQ_INT0 2 /* 0x0002 INT0 External Interrupt Request 0 */ # define ATMEGA_IRQ_INT0 2 /* 0x0002 INT0 External Interrupt Request 0 */
# define ATMEGA_IRQ_INT1 3 /* 0x0004 INT1 External Interrupt Request 1 */ # define ATMEGA_IRQ_INT1 3 /* 0x0004 INT1 External Interrupt Request 1 */
# define ATMEGA_IRQ_INT2 4 /* 0x0006 INT2 External Interrupt Request 2 */ # define ATMEGA_IRQ_INT2 4 /* 0x0006 INT2 External Interrupt Request 2 */
# define ATMEGA_IRQ_INT3 5 /* 0x0008 INT3 External Interrupt Request 3 */ # define ATMEGA_IRQ_INT3 5 /* 0x0008 INT3 External Interrupt Request 3 */
# define ATMEGA_IRQ_INT4 6 /* 0x000A INT4 External Interrupt Request 4 */ # define ATMEGA_IRQ_INT4 6 /* 0x000A INT4 External Interrupt Request 4 */
# define ATMEGA_IRQ_INT5 7 /* 0x000C INT5 External Interrupt Request 5 */ # define ATMEGA_IRQ_INT5 7 /* 0x000C INT5 External Interrupt Request 5 */
# define ATMEGA_IRQ_INT6 8 /* 0x000E INT6 External Interrupt Request 6 */ # define ATMEGA_IRQ_INT6 8 /* 0x000E INT6 External Interrupt Request 6 */
# define ATMEGA_IRQ_INT7 9 /* 0x0010 INT7 External Interrupt Request 7 */ # define ATMEGA_IRQ_INT7 9 /* 0x0010 INT7 External Interrupt Request 7 */
# define ATMEGA_IRQ_PCINT0 10 /* 0x0012 PCINT0 Pin Change Interrupt Req 0 */ # define ATMEGA_IRQ_PCINT0 10 /* 0x0012 PCINT0 Pin Change Interrupt Req 0 */
# define ATMEGA_IRQ_PCINT1 11 /* 0x0014 PCINT1 Pin Change Interrupt Req 1 */ # define ATMEGA_IRQ_PCINT1 11 /* 0x0014 PCINT1 Pin Change Interrupt Req 1 */
# define ATMEGA_IRQ_PCINT2 12 /* 0x0016 PCINT2 Pin Change Interrupt Req 2 */ # define ATMEGA_IRQ_PCINT2 12 /* 0x0016 PCINT2 Pin Change Interrupt Req 2 */

2
arch/avr/include/avr/avr.h
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@ -40,7 +40,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_INCLUDE_AVR_AVR_H */ #endif /* __ARCH_AVR_INCLUDE_AVR_AVR_H */

6
arch/avr/include/avr/irq.h
View File

@ -138,13 +138,13 @@ struct xcptcontext
static inline irqstate_t getsreg(void) static inline irqstate_t getsreg(void)
{ {
irqstate_t sreg; irqstate_t sreg;
asm volatile ("in %0, __SREG__" : "=r" (sreg) :: ); asm volatile ("in %0, __SREG__" : "=r" (sreg) ::);
return sreg; return sreg;
} }
static inline void putsreg(irqstate_t sreg) static inline void putsreg(irqstate_t sreg)
{ {
asm volatile ("out __SREG__, %s" : : "r" (sreg) : ); asm volatile ("out __SREG__, %s" : : "r" (sreg) :);
} }
/* Interrupt enable/disable */ /* Interrupt enable/disable */
@ -177,7 +177,7 @@ static inline irqstate_t up_irq_save(void)
static inline void up_irq_restore(irqstate_t flags) static inline void up_irq_restore(irqstate_t flags)
{ {
asm volatile ("out __SREG__, %0" : : "r" (flags) : ); asm volatile ("out __SREG__, %0" : : "r" (flags) :);
} }
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */

2
arch/avr/include/avr32/avr32.h
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@ -184,7 +184,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_INCLUDE_AVR32_AVR32_H */ #endif /* __ARCH_AVR_INCLUDE_AVR32_AVR32_H */

8
arch/avr/include/limits.h
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@ -25,10 +25,6 @@
* Included Files * Included Files
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Include AVR architecture-specific limits */ /* Include AVR architecture-specific limits */
#ifdef CONFIG_ARCH_FAMILY_AVR32 #ifdef CONFIG_ARCH_FAMILY_AVR32
@ -37,4 +33,8 @@
# include <arch/avr/limits.h> # include <arch/avr/limits.h>
#endif #endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#endif /* __ARCH_AVR_INCLUDE_LIMITS_H */ #endif /* __ARCH_AVR_INCLUDE_LIMITS_H */

1
arch/avr/include/xmega/chip.h
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@ -31,6 +31,7 @@
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* Eventually, we will provide characteristics of the various supported /* Eventually, we will provide characteristics of the various supported
* XMega chips here. * XMega chips here.
*/ */

2
arch/avr/include/xmega/irq.h
View File

@ -34,7 +34,7 @@
#include <arch/xmega/xmegac_irq.h> #include <arch/xmega/xmegac_irq.h>
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/

4
arch/avr/src/at32uc3/at32uc3.h
View File

@ -113,7 +113,6 @@
#define GPIO_ENABLE (1 << 8) /* Bit 8: GPIO enable */ #define GPIO_ENABLE (1 << 8) /* Bit 8: GPIO enable */
#define GPIO_PERIPH (0) #define GPIO_PERIPH (0)
/* Port Number /* Port Number
* .... .... .... .... .... .... PPP. .... * .... .... .... .... .... .... PPP. ....
*/ */
@ -188,7 +187,8 @@ void usart_reset(uintptr_t usart_base);
* *
****************************************************************************/ ****************************************************************************/
void usart_configure(uintptr_t usart_base, uint32_t baud, unsigned int parity, void usart_configure(uintptr_t usart_base,
uint32_t baud, unsigned int parity,
unsigned int nbits, bool stop2); unsigned int nbits, bool stop2);
/**************************************************************************** /****************************************************************************

7
arch/avr/src/at32uc3/at32uc3_abdac.h
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@ -54,6 +54,7 @@
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions ***************************************************/
/* Sample Data Register Bit-field Definitions */ /* Sample Data Register Bit-field Definitions */
/* This register contains a 32-bit data and, hence, has no bit-fiels */ /* This register contains a 32-bit data and, hence, has no bit-fiels */
/* Control Register Bit-field Definitions */ /* Control Register Bit-field Definitions */
@ -62,9 +63,13 @@
#define ABDAC_CR_EN (1 << 31) /* Bit 31: Enable Audio Bitstream DAC */ #define ABDAC_CR_EN (1 << 31) /* Bit 31: Enable Audio Bitstream DAC */
/* Interrupt Mask Register Bit-field Definitions */ /* Interrupt Mask Register Bit-field Definitions */
/* Interrupt Enable Register Bit-field Definitions */ /* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */ /* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Clear Register Bit-field Definitions */ /* Interrupt Clear Register Bit-field Definitions */
/* Interrupt Status Register Bit-field Definitions */ /* Interrupt Status Register Bit-field Definitions */
#define ABDAC_INT_UNDERRUN (1 << 28) /* Bit 28: Underrun Interrupt Status */ #define ABDAC_INT_UNDERRUN (1 << 28) /* Bit 28: Underrun Interrupt Status */
@ -79,7 +84,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_ABDAC_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_ABDAC_H */

39
arch/avr/src/at32uc3/at32uc3_adc.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_adc.h * arch/avr/src/at32uc3/at32uc3_adc.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_ADC_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_ADC_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_ADC_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_ADC_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_ADC_CR_OFFSET 0x000 /* Control Register */ #define AVR32_ADC_CR_OFFSET 0x000 /* Control Register */
#define AVR32_ADC_MR_OFFSET 0x004 /* Mode Register */ #define AVR32_ADC_MR_OFFSET 0x004 /* Mode Register */
@ -54,7 +54,7 @@
#define AVR32_ADC_CDR7_OFFSET 0x04c /* Channel Data Register 7 */ #define AVR32_ADC_CDR7_OFFSET 0x04c /* Channel Data Register 7 */
#define AVR32_ADC_VERSION_OFFSET 0x0fc /* Version Register */ #define AVR32_ADC_VERSION_OFFSET 0x0fc /* Version Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_ADC_CR (AVR32_ADC_BASE+AVR32_ADC_CR_OFFSET) #define AVR32_ADC_CR (AVR32_ADC_BASE+AVR32_ADC_CR_OFFSET)
#define AVR32_ADC_MR (AVR32_ADC_BASE+AVR32_ADC_MR_OFFSET) #define AVR32_ADC_MR (AVR32_ADC_BASE+AVR32_ADC_MR_OFFSET)
@ -77,7 +77,7 @@
#define AVR32_ADC_CDR7 (AVR32_ADC_BASE+AVR32_ADC_CDR7_OFFSET) #define AVR32_ADC_CDR7 (AVR32_ADC_BASE+AVR32_ADC_CDR7_OFFSET)
#define AVR32_ADC_VERSION (AVR32_ADC_BASE+AVR32_ADC_VERSION_OFFSET) #define AVR32_ADC_VERSION (AVR32_ADC_BASE+AVR32_ADC_VERSION_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Control Register Bit-field Definitions */ /* Control Register Bit-field Definitions */
@ -90,6 +90,7 @@
#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */ #define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT) #define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT)
# define ADC_MR_TRGSEL_TRIG(n) ((n) << ADC_MR_TRGSEL_SHIFT) /* Internal trigger n */ # define ADC_MR_TRGSEL_TRIG(n) ((n) << ADC_MR_TRGSEL_SHIFT) /* Internal trigger n */
# define ADC_MR_TRGSEL_TRIG0 (0 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 0 */ # define ADC_MR_TRGSEL_TRIG0 (0 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 0 */
# define ADC_MR_TRGSEL_TRIG1 (1 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 1 */ # define ADC_MR_TRGSEL_TRIG1 (1 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 1 */
# define ADC_MR_TRGSEL_TRIG2 (2 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 2 */ # define ADC_MR_TRGSEL_TRIG2 (2 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 2 */
@ -98,6 +99,7 @@
# define ADC_MR_TRGSEL_TRIG5 (5 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 5 */ # define ADC_MR_TRGSEL_TRIG5 (5 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 5 */
# define ADC_MR_TRGSEL_TRIG6 (6 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 6 */ # define ADC_MR_TRGSEL_TRIG6 (6 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 6 */
# define ADC_MR_TRGSEL_EXT (7 << ADC_MR_TRGSEL_SHIFT) /* External trigger */ # define ADC_MR_TRGSEL_EXT (7 << ADC_MR_TRGSEL_SHIFT) /* External trigger */
#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */ #define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */
#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ #define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */ #define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */
@ -108,7 +110,9 @@
#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT) #define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT)
/* Channel Enable Register Bit-field Definitions */ /* Channel Enable Register Bit-field Definitions */
/* Channel Disable Register Bit-field Definitions */ /* Channel Disable Register Bit-field Definitions */
/* Channel Status Register Bit-field Definitions */ /* Channel Status Register Bit-field Definitions */
#define ADC_CHAN(n) (1 << (n)) #define ADC_CHAN(n) (1 << (n))
@ -122,8 +126,11 @@
#define ADC_CHAN7 (1 << 7) #define ADC_CHAN7 (1 << 7)
/* Status Register Bit-field Definitions */ /* Status Register Bit-field Definitions */
/* Interrupt Enable Register Bit-field Definitions */ /* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */ /* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */ /* Interrupt Mask Register Bit-field Definitions */
#define ADC_INT_EOC(n) (1 << (n)) #define ADC_INT_EOC(n) (1 << (n))
@ -164,16 +171,16 @@
#define ADC_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ #define ADC_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define ADC_VERSION_VARIANT_MASK (15 << ADC_VERSION_VARIANT_SHIFT) #define ADC_VERSION_VARIANT_MASK (15 << ADC_VERSION_VARIANT_SHIFT)
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_ADC_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_ADC_H */

33
arch/avr/src/at32uc3/at32uc3_clkinit.c
View File

@ -95,7 +95,8 @@ static inline void up_enableosc32(void)
regval = getreg32(AVR32_PM_OSCCTRL32); regval = getreg32(AVR32_PM_OSCCTRL32);
regval &= ~PM_OSCCTRL32_STARTUP_MASK; regval &= ~PM_OSCCTRL32_STARTUP_MASK;
regval |= PM_OSCCTRL32_EN | (AVR32_OSC32STARTUP << PM_OSCCTRL32_STARTUP_SHIFT); regval |= PM_OSCCTRL32_EN |
(AVR32_OSC32STARTUP << PM_OSCCTRL32_STARTUP_SHIFT);
putreg32(regval, AVR32_PM_OSCCTRL32); putreg32(regval, AVR32_PM_OSCCTRL32);
} }
#endif #endif
@ -113,12 +114,14 @@ static inline void up_enableosc0(void)
{ {
uint32_t regval; uint32_t regval;
/* Enable OSC0 in the correct crystal mode by setting the mode value in OSCCTRL0 */ /* Enable OSC0 in the correct crystal mode by setting the mode value in
* OSCCTRL0
*/
regval = getreg32(AVR32_PM_OSCCTRL0); regval = getreg32(AVR32_PM_OSCCTRL0);
regval &= ~PM_OSCCTRL_MODE_MASK; regval &= ~PM_OSCCTRL_MODE_MASK;
#if AVR32_FOSC0 < 900000 #if AVR32_FOSC0 < 900000
regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */ regval |= PM_OSCCTRL_MODE_XTALP9; /* Crystal XIN 0.4-0.9MHz */
#elif AVR32_FOSC0 < 3000000 #elif AVR32_FOSC0 < 3000000
regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */ regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */
#elif AVR32_FOSC0 < 8000000 #elif AVR32_FOSC0 < 8000000
@ -128,8 +131,8 @@ static inline void up_enableosc0(void)
#endif #endif
putreg32(regval, AVR32_PM_OSCCTRL0); putreg32(regval, AVR32_PM_OSCCTRL0);
/* Enable OSC0 using the startup time provided in board.h. This startup time /* Enable OSC0 using the startup time provided in board.h. This startup
* is critical and depends on the characteristics of the crystal. * time is critical and depends on the characteristics of the crystal.
*/ */
regval = getreg32(AVR32_PM_OSCCTRL0); regval = getreg32(AVR32_PM_OSCCTRL0);
@ -162,12 +165,14 @@ static inline void up_enableosc1(void)
{ {
uint32_t regval; uint32_t regval;
/* Enable OSC1 in the correct crystal mode by setting the mode value in OSCCTRL1 */ /* Enable OSC1 in the correct crystal mode by setting the mode value in
* OSCCTRL1
*/
regval = getreg32(AVR32_PM_OSCCTRL1); regval = getreg32(AVR32_PM_OSCCTRL1);
regval &= ~PM_OSCCTRL_MODE_MASK; regval &= ~PM_OSCCTRL_MODE_MASK;
#if AVR32_FOSC1 < 900000 #if AVR32_FOSC1 < 900000
regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */ regval |= PM_OSCCTRL_MODE_XTALP9; /* Crystal XIN 0.4-0.9MHz */
#elif AVR32_FOSC1 < 3000000 #elif AVR32_FOSC1 < 3000000
regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */ regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */
#elif AVR32_FOSC1 < 8000000 #elif AVR32_FOSC1 < 8000000
@ -177,8 +182,8 @@ static inline void up_enableosc1(void)
#endif #endif
putreg32(regval, AVR32_PM_OSCCTRL1); putreg32(regval, AVR32_PM_OSCCTRL1);
/* Enable OSC1 using the startup time provided in board.h. This startup time /* Enable OSC1 using the startup time provided in board.h. This startup
* is critical and depends on the characteristics of the crystal. * time is critical and depends on the characteristics of the crystal.
*/ */
regval = getreg32(AVR32_PM_OSCCTRL1); regval = getreg32(AVR32_PM_OSCCTRL1);
@ -211,7 +216,9 @@ static inline void up_enablepll0(void)
{ {
/* Setup PLL0 */ /* Setup PLL0 */
regval = (AVR32_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) | (AVR32_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT) regval = (AVR32_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) |
(AVR32_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) |
(16 << PM_PLL_PLLCOUNT_SHIFT)
/* Select PLL0/1 oscillator */ /* Select PLL0/1 oscillator */
@ -261,7 +268,9 @@ static inline void up_enablepll1(void)
{ {
/* Setup PLL1 */ /* Setup PLL1 */
regval = (AVR32_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) | (AVR32_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT) regval = (AVR32_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) |
(AVR32_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) |
(16 << PM_PLL_PLLCOUNT_SHIFT)
/* Select PLL0/1 oscillator */ /* Select PLL0/1 oscillator */
@ -358,6 +367,7 @@ static void up_fws(uint32_t cpuclock)
{ {
regval &= ~FLASHC_FCR_FWS; regval &= ~FLASHC_FCR_FWS;
} }
putreg32(regval, AVR32_FLASHC_FCR); putreg32(regval, AVR32_FLASHC_FCR);
} }
@ -400,7 +410,6 @@ static inline void up_usbclock(void)
#endif #endif
#if AVR32_CLOCK_USB_DIV > 0 #if AVR32_CLOCK_USB_DIV > 0
u_avr32_pm_gcctrl.GCCTRL.diven = diven; u_avr32_pm_gcctrl.GCCTRL.diven = diven;
u_avr32_pm_gcctrl.GCCTRL.div = div; u_avr32_pm_gcctrl.GCCTRL.div = div;
#endif #endif

34
arch/avr/src/at32uc3/at32uc3_config.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_config.h * arch/avr/src/at32uc3/at32uc3_config.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_CONFIG_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_CONFIG_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_CONFIG_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_CONFIG_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "chip.h" #include "chip.h"
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* USART can be configured as a number of different devices (Only UART is supported /* USART can be configured as a number of different devices (Only UART is
* here now, that will be extended). Check for consistency between USART enable * supported here now, that will be extended).
* options. * Check for consistency between USART enable options.
*/ */
#if AVR32_NUSART < 1 #if AVR32_NUSART < 1
@ -102,7 +102,7 @@
#if defined(CONFIG_AVR32_USART0_RS232) || \ #if defined(CONFIG_AVR32_USART0_RS232) || \
defined(CONFIG_AVR32_USART1_RS232) || \ defined(CONFIG_AVR32_USART1_RS232) || \
defined(CONFIG_AVR32_USART2_RS232) defined(CONFIG_AVR32_USART2_RS232)
# define HAVE_RS232_DEVICE # define HAVE_RS232_DEVICE
#else #else
# undef HAVE_RS232_DEVICE # undef HAVE_RS232_DEVICE
@ -166,16 +166,16 @@
# undef CONFIG_AVR32_GPIOIRQ # undef CONFIG_AVR32_GPIOIRQ
#endif #endif
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_CONFIG_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_CONFIG_H */

45
arch/avr/src/at32uc3/at32uc3_eic.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_eic.h * arch/avr/src/at32uc3/at32uc3_eic.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_EIC_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_EIC_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_EIC_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_EIC_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_EIC_IER_OFFSET 0x000 /* Interrupt Enable Register */ #define AVR32_EIC_IER_OFFSET 0x000 /* Interrupt Enable Register */
#define AVR32_EIC_IDR_OFFSET 0x004 /* Interrupt Disable Register */ #define AVR32_EIC_IDR_OFFSET 0x004 /* Interrupt Disable Register */
@ -49,7 +49,7 @@
#define AVR32_EIC_DIS_OFFSET 0x034 /* Disable Register */ #define AVR32_EIC_DIS_OFFSET 0x034 /* Disable Register */
#define AVR32_EIC_CTRL_OFFSET 0x038 /* Control Register */ #define AVR32_EIC_CTRL_OFFSET 0x038 /* Control Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_EIC_IER (AVR32_EIC_BASE+AVR32_EIC_IER_OFFSET) #define AVR32_EIC_IER (AVR32_EIC_BASE+AVR32_EIC_IER_OFFSET)
#define AVR32_EIC_IDR (AVR32_EIC_BASE+AVR32_EIC_IDR_OFFSET) #define AVR32_EIC_IDR (AVR32_EIC_BASE+AVR32_EIC_IDR_OFFSET)
@ -67,21 +67,34 @@
#define AVR32_EIC_DIS (AVR32_EIC_BASE+AVR32_EIC_DIS_OFFSET) #define AVR32_EIC_DIS (AVR32_EIC_BASE+AVR32_EIC_DIS_OFFSET)
#define AVR32_EIC_CTRL (AVR32_EIC_BASE+AVR32_EIC_CTRL_OFFSET) #define AVR32_EIC_CTRL (AVR32_EIC_BASE+AVR32_EIC_CTRL_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Interrupt Enable Register Bit-field Definitions */ /* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */ /* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */ /* Interrupt Mask Register Bit-field Definitions */
/* Interrupt Status Register Bit-field Definitions */ /* Interrupt Status Register Bit-field Definitions */
/* Interrupt Clear Register Bit-field Definitions */ /* Interrupt Clear Register Bit-field Definitions */
/* Mode Register Bit-field Definitions */ /* Mode Register Bit-field Definitions */
/* Edge Register Bit-field Definitions */ /* Edge Register Bit-field Definitions */
/* Level Register Bit-field Definitions */ /* Level Register Bit-field Definitions */
/* Filter Register Bit-field Definitions */ /* Filter Register Bit-field Definitions */
/* Test Register Bit-field Definitions */ /* Test Register Bit-field Definitions */
/* Asynchronous Register Bit-field Definitions */ /* Asynchronous Register Bit-field Definitions */
/* Enable Register Bit-field Definitions */ /* Enable Register Bit-field Definitions */
/* Disable Register Bit-field Definitions */ /* Disable Register Bit-field Definitions */
/* Control Register Bit-field Definitions */ /* Control Register Bit-field Definitions */
#define EIC_INT0 (1 << 0) /* Bit 0: External interrupt 0 */ #define EIC_INT0 (1 << 0) /* Bit 0: External interrupt 0 */
@ -102,16 +115,16 @@
#define EIC_SCAN_PRESC_MASK (0x1f << EIC_SCAN_PRESC_SHIFT) #define EIC_SCAN_PRESC_MASK (0x1f << EIC_SCAN_PRESC_SHIFT)
#define EIC_SCAN_EN (1 << 0) /* Bit 0: Enable keypad scanning */ #define EIC_SCAN_EN (1 << 0) /* Bit 0: Enable keypad scanning */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_EIC_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_EIC_H */

2
arch/avr/src/at32uc3/at32uc3_flashc.h
View File

@ -207,7 +207,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_FLASHC_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_FLASHC_H */

29
arch/avr/src/at32uc3/at32uc3_gpio.c
View File

@ -64,19 +64,19 @@
static uint32_t g_portmap[AVR32_NGPIO_PORTS] = static uint32_t g_portmap[AVR32_NGPIO_PORTS] =
{ {
#if AVR32_NGPIO > 0 #if AVR32_NGPIO > 0
AVR32_GPIO0_BASE AVR32_GPIO0_BASE
#endif #endif
#if AVR32_NGPIO > 32 #if AVR32_NGPIO > 32
, AVR32_GPIO1_BASE, , AVR32_GPIO1_BASE,
#endif #endif
#if AVR32_NGPIO > 64 #if AVR32_NGPIO > 64
, AVR32_GPIO2_BASE, , AVR32_GPIO2_BASE,
#endif #endif
#if AVR32_NGPIO > 96 #if AVR32_NGPIO > 96
, AVR32_GPIO3_BASE, , AVR32_GPIO3_BASE,
#endif #endif
#if AVR32_NGPIO > 128 #if AVR32_NGPIO > 128
, AVR32_GPIO4_BASE, , AVR32_GPIO4_BASE,
#endif #endif
}; };
@ -88,13 +88,13 @@ static uint32_t g_portmap[AVR32_NGPIO_PORTS] =
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Name: at32uc3_configgpio * Name: at32uc3_configgpio
* *
* Description: * Description:
* Configure a GPIO pin based on bit-encoded description of the pin. * Configure a GPIO pin based on bit-encoded description of the pin.
* *
************************************************************************************/ ****************************************************************************/
int at32uc3_configgpio(uint16_t cfgset) int at32uc3_configgpio(uint16_t cfgset)
{ {
@ -115,9 +115,9 @@ int at32uc3_configgpio(uint16_t cfgset)
base = g_portmap[port]; base = g_portmap[port];
/* First, just to be safe, disable the output driver, give GPIO control of /* First, just to be safe, disable the output driver, give GPIO control of
* the pin, rese the peripheral mux, set the output low, remove the pull-up, * the pin, rese the peripheral mux, set the output low, remove the
* disable GPIO interrupts, reset the interrupt mode, and disable glitch * pull-up, disable GPIO interrupts, reset the interrupt mode, and disable
* filtering, while we reconfigure the pin. * glitch filtering, while we reconfigure the pin.
*/ */
putreg32(pinmask, base + AVR32_GPIO_ODERC_OFFSET); putreg32(pinmask, base + AVR32_GPIO_ODERC_OFFSET);
@ -147,6 +147,7 @@ int at32uc3_configgpio(uint16_t cfgset)
{ {
putreg32(pinmask, base + AVR32_GPIO_OVRS_OFFSET); putreg32(pinmask, base + AVR32_GPIO_OVRS_OFFSET);
} }
putreg32(pinmask, base + AVR32_GPIO_ODERS_OFFSET); putreg32(pinmask, base + AVR32_GPIO_ODERS_OFFSET);
} }
else else
@ -211,13 +212,13 @@ int at32uc3_configgpio(uint16_t cfgset)
return OK; return OK;
} }
/************************************************************************************ /****************************************************************************
* Name: at32uc3_gpiowrite * Name: at32uc3_gpiowrite
* *
* Description: * Description:
* Write one or zero to the selected GPIO pin * Write one or zero to the selected GPIO pin
* *
************************************************************************************/ ****************************************************************************/
void at32uc3_gpiowrite(uint16_t pinset, bool value) void at32uc3_gpiowrite(uint16_t pinset, bool value)
{ {
@ -249,13 +250,13 @@ void at32uc3_gpiowrite(uint16_t pinset, bool value)
} }
} }
/************************************************************************************ /****************************************************************************
* Name: at32uc3_gpioread * Name: at32uc3_gpioread
* *
* Description: * Description:
* Read one or zero from the selected GPIO pin * Read one or zero from the selected GPIO pin
* *
************************************************************************************/ ****************************************************************************/
bool at32uc3_gpioread(uint16_t pinset) bool at32uc3_gpioread(uint16_t pinset)
{ {

43
arch/avr/src/at32uc3/at32uc3_gpio.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_gpio.h * arch/avr/src/at32uc3/at32uc3_gpio.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_GPIO_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_GPIO_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_GPIO_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_GPIO_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Port Identifiers *****************************************************************/
/* Port Identifiers *********************************************************/
#define AVR32_GPIO0 0 /* General Purpose Input/Output Port 0 */ #define AVR32_GPIO0 0 /* General Purpose Input/Output Port 0 */
#define AVR32_GPIO1 1 /* General Purpose Input/Output Port 1 */ #define AVR32_GPIO1 1 /* General Purpose Input/Output Port 1 */
@ -38,7 +39,7 @@
#define AVR32_GPIO3 3 /* General Purpose Input/Output Port 3 */ #define AVR32_GPIO3 3 /* General Purpose Input/Output Port 3 */
#define AVR32_GPIO4 4 /* General Purpose Input/Output Port 4 */ #define AVR32_GPIO4 4 /* General Purpose Input/Output Port 4 */
/* Port Offsets *********************************************************************/ /* Port Offsets *************************************************************/
#define AVR32_GPIOn_OFFSET(n) ((n) << 8) #define AVR32_GPIOn_OFFSET(n) ((n) << 8)
#define AVR32_GPIO0_OFFSET 0x0000 /* General Purpose Input/Output Port 0 */ #define AVR32_GPIO0_OFFSET 0x0000 /* General Purpose Input/Output Port 0 */
@ -47,7 +48,7 @@
#define AVR32_GPIO3_OFFSET 0x0300 /* General Purpose Input/Output Port 3 */ #define AVR32_GPIO3_OFFSET 0x0300 /* General Purpose Input/Output Port 3 */
#define AVR32_GPIO4_OFFSET 0x0400 /* General Purpose Input/Output Port 4 */ #define AVR32_GPIO4_OFFSET 0x0400 /* General Purpose Input/Output Port 4 */
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_GPIO_GPER_OFFSET 0x00 /* GPIO Enable Register */ #define AVR32_GPIO_GPER_OFFSET 0x00 /* GPIO Enable Register */
#define AVR32_GPIO_GPERS_OFFSET 0x04 /* GPIO Enable Register Set */ #define AVR32_GPIO_GPERS_OFFSET 0x04 /* GPIO Enable Register Set */
@ -93,7 +94,7 @@
#define AVR32_GPIO_IFR_OFFSET 0xd0 /* Interrupt Flag Register Read */ #define AVR32_GPIO_IFR_OFFSET 0xd0 /* Interrupt Flag Register Read */
#define AVR32_GPIO_IFRC_OFFSET 0xd8 /* Interrupt Flag Register Clear */ #define AVR32_GPIO_IFRC_OFFSET 0xd8 /* Interrupt Flag Register Clear */
/* Port Base Addresses **************************************************************/ /* Port Base Addresses ******************************************************/
#define AVR32_GPIOn_BASE(n) (AVR32_GPIO_BASE+AVR32_GPIO_OFFSET(n)) #define AVR32_GPIOn_BASE(n) (AVR32_GPIO_BASE+AVR32_GPIO_OFFSET(n))
#define AVR32_GPIO0_BASE (AVR32_GPIO_BASE+AVR32_GPIO0_OFFSET) #define AVR32_GPIO0_BASE (AVR32_GPIO_BASE+AVR32_GPIO0_OFFSET)
@ -108,7 +109,7 @@
#define AVR32_GPIO0_LBUS_BASE (AVR32_GPIO_LBUS_BASE+AVR32_GPIO0_OFFSET) #define AVR32_GPIO0_LBUS_BASE (AVR32_GPIO_LBUS_BASE+AVR32_GPIO0_OFFSET)
#define AVR32_GPIO1_LBUS_BASE (AVR32_GPIO_LBUS_BASE+AVR32_GPIO1_OFFSET) #define AVR32_GPIO1_LBUS_BASE (AVR32_GPIO_LBUS_BASE+AVR32_GPIO1_OFFSET)
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_GPIO_GPER(n) (AVR32_GPIOn_BASE(n)+AVR32_GPIO_GPER_OFFSET) #define AVR32_GPIO_GPER(n) (AVR32_GPIOn_BASE(n)+AVR32_GPIO_GPER_OFFSET)
#define AVR32_GPIO_GPERS(n) (AVR32_GPIOn_BASE(n)+AVR32_GPIO_GPERS_OFFSET) #define AVR32_GPIO_GPERS(n) (AVR32_GPIOn_BASE(n)+AVR32_GPIO_GPERS_OFFSET)
@ -396,9 +397,11 @@
#define AVR32_GPIO1_LBUS_OVRT (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_OVRT_OFFSET) #define AVR32_GPIO1_LBUS_OVRT (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_OVRT_OFFSET)
#define AVR32_GPIO1_LBUS_PVR (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_PVR_OFFSET) #define AVR32_GPIO1_LBUS_PVR (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_PVR_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* For all registers, there are 32 bits, each associated with one pin on the port. */ /* For all registers, there are 32 bits,
* each associated with one pin on the port.
*/
#define GPIO_PIN(n) (1 << (n)) #define GPIO_PIN(n) (1 << (n))
#define GPIO_PIN0 (1 << 0) #define GPIO_PIN0 (1 << 0)
@ -434,16 +437,16 @@
#define GPIO_PIN30 (1 << 30) #define GPIO_PIN30 (1 << 30)
#define GPIO_PIN31 (1 << 31) #define GPIO_PIN31 (1 << 31)
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_GPIO_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_GPIO_H */

6
arch/avr/src/at32uc3/at32uc3_gpioirq.c
View File

@ -174,7 +174,8 @@ static inline int gpio_pin(unsigned int irq)
* *
****************************************************************************/ ****************************************************************************/
static void gpio_porthandler(uint32_t regbase, int irqbase, uint32_t irqset, void *context) static void gpio_porthandler(uint32_t regbase, int irqbase,
uint32_t irqset, void *context)
{ {
uint32_t ifr; uint32_t ifr;
int irq; int irq;
@ -233,7 +234,8 @@ static void gpio_porthandler(uint32_t regbase, int irqbase, uint32_t irqset, voi
putreg32(bit, regbase + AVR32_GPIO_IFRC_OFFSET); putreg32(bit, regbase + AVR32_GPIO_IFRC_OFFSET);
ifr &= ~bit; ifr &= ~bit;
warn("WARNING: IRQ on unconfigured pin: pin=%d ifr=%08x irqset=%08x", warn("WARNING:"
" IRQ on unconfigured pin: pin=%d ifr=%08x irqset=%08x",
pin, ifr, irqset); pin, ifr, irqset);
} }
} }

39
arch/avr/src/at32uc3/at32uc3_hmatrix.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_hmatrix.h * arch/avr/src/at32uc3/at32uc3_hmatrix.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_HMATRIX_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_HMATRIX_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_HMATRIX_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_HMATRIX_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_HMATRIX_MCFG_OFFSET(n) (0x0000+((n)<<2)) #define AVR32_HMATRIX_MCFG_OFFSET(n) (0x0000+((n)<<2))
#define AVR32_HMATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ #define AVR32_HMATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
@ -122,7 +122,7 @@
#define AVR32_HMATRIX_SFR14_OFFSET 0x0148 /* Special Function Register 14 */ #define AVR32_HMATRIX_SFR14_OFFSET 0x0148 /* Special Function Register 14 */
#define AVR32_HMATRIX_SFR15_OFFSET 0x014c /* Special Function Register 15 */ #define AVR32_HMATRIX_SFR15_OFFSET 0x014c /* Special Function Register 15 */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_HMATRIX_MCFG(n) (AVR32_HMATRIX_BASE+AVR32_HMATRIX_MCFG_OFFSET(n)) #define AVR32_HMATRIX_MCFG(n) (AVR32_HMATRIX_BASE+AVR32_HMATRIX_MCFG_OFFSET(n))
#define AVR32_HMATRIX_MCFG0 (AVR32_HMATRIX_BASE+AVR32_HMATRIX_MCFG0_OFFSET) #define AVR32_HMATRIX_MCFG0 (AVR32_HMATRIX_BASE+AVR32_HMATRIX_MCFG0_OFFSET)
@ -213,7 +213,7 @@
#define AVR32_HMATRIX_SFR14 (AVR32_HMATRIX_BASE+AVR32_HMATRIX_SFR14_OFFSET) #define AVR32_HMATRIX_SFR14 (AVR32_HMATRIX_BASE+AVR32_HMATRIX_SFR14_OFFSET)
#define AVR32_HMATRIX_SFR15 (AVR32_HMATRIX_BASE+AVR32_HMATRIX_SFR15_OFFSET) #define AVR32_HMATRIX_SFR15 (AVR32_HMATRIX_BASE+AVR32_HMATRIX_SFR15_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Master Configuration Register Bit-field Definitions */ /* Master Configuration Register Bit-field Definitions */
@ -227,14 +227,14 @@
/* Slave Configuration Register Bit-field Definitions */ /* Slave Configuration Register Bit-field Definitions */
#define HMATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst #define HMATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
#define HMATRIX_SCFG_SLOTCYCLE_MASK (0xff << HMATRIX_SCFG_SLOTCYCLE_SHIFT) #define HMATRIX_SCFG_SLOTCYCLE_MASK (0xff << HMATRIX_SCFG_SLOTCYCLE_SHIFT)
#define HMATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type #define HMATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */
#define HMATRIX_SCFG_DEFMSTRTYPE_MASK (3 << HMATRIX_SCFG_DEFMSTRTYPE_SHIFT) #define HMATRIX_SCFG_DEFMSTRTYPE_MASK (3 << HMATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define HMATRIX_SCFG_DEFMSTRTYPE_NONE (0 << HMATRIX_SCFG_DEFMSTRTYPE_SHIFT) # define HMATRIX_SCFG_DEFMSTRTYPE_NONE (0 << HMATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define HMATRIX_SCFG_DEFMSTRTYPE_LAST (1 << HMATRIX_SCFG_DEFMSTRTYPE_SHIFT) # define HMATRIX_SCFG_DEFMSTRTYPE_LAST (1 << HMATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define HMATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << HMATRIX_SCFG_DEFMSTRTYPE_SHIFT) # define HMATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << HMATRIX_SCFG_DEFMSTRTYPE_SHIFT)
#define HMATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-21: Fixed Default Master #define HMATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-21: Fixed Default Master */
#define HMATRIX_SCFG_FIXEDDEFMSTR_MASK (15 << HMATRIX_SCFG_FIXEDDEFMSTR_SHIFT) #define HMATRIX_SCFG_FIXEDDEFMSTR_MASK (15 << HMATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
#define HMATRIX_SCFG_ARBT (1 << 24) /* Bit 24: Arbitration Type */ #define HMATRIX_SCFG_ARBT (1 << 24) /* Bit 24: Arbitration Type */
@ -281,18 +281,19 @@
#define HMATRIX_PRBS_M15PR_MASK (3 << HMATRIX_PRBS_M15PR_SHIFT) #define HMATRIX_PRBS_M15PR_MASK (3 << HMATRIX_PRBS_M15PR_SHIFT)
/* Special Function Register Bit-field Definitions */ /* Special Function Register Bit-field Definitions */
/* This register contains only the 32-bit SFR value and has no bit-fields */ /* This register contains only the 32-bit SFR value and has no bit-fields */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_HMATRIX_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_HMATRIX_H */

2
arch/avr/src/at32uc3/at32uc3_intc.h
View File

@ -76,7 +76,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_INTC_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_INTC_H */

17
arch/avr/src/at32uc3/at32uc3_irq.c
View File

@ -147,6 +147,7 @@ static int up_getgrp(unsigned int irq)
} }
} }
} }
return -EINVAL; return -EINVAL;
} }
@ -184,10 +185,14 @@ void up_irqinitialize(void)
*/ */
#if 1 /* REVISIT -- Can we come up with a way to statically initialize? */ #if 1 /* REVISIT -- Can we come up with a way to statically initialize? */
g_ipr[0] = ((AVR32_INT0_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT0); g_ipr[0] = ((AVR32_INT0_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) |
g_ipr[1] = ((AVR32_INT1_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT1); INTC_IPR_INTLEVEL_INT0);
g_ipr[2] = ((AVR32_INT2_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT2); g_ipr[1] = ((AVR32_INT1_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) |
g_ipr[3] = ((AVR32_INT3_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT3); INTC_IPR_INTLEVEL_INT1);
g_ipr[2] = ((AVR32_INT2_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) |
INTC_IPR_INTLEVEL_INT2);
g_ipr[3] = ((AVR32_INT3_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) |
INTC_IPR_INTLEVEL_INT3);
#endif #endif
/* Set the interrupt group priority to a default value. All are linked to /* Set the interrupt group priority to a default value. All are linked to
@ -305,8 +310,8 @@ unsigned int avr32_intirqno(unsigned int level)
mask <<= 1; mask <<= 1;
} }
_err("ERROR: Spurious interrupt: group=%d IRR=%08x\n", group, irr); _err("ERROR: Spurious interrupt: group=%d IRR=%08x\n", group, irr);
return -ENODEV; return -ENODEV;
} }
_err("ERROR: Bad group: %d\n", group); _err("ERROR: Bad group: %d\n", group);

44
arch/avr/src/at32uc3/at32uc3_lowconsole.c
View File

@ -95,7 +95,8 @@
****************************************************************************/ ****************************************************************************/
#ifdef HAVE_RS232_DEVICE #ifdef HAVE_RS232_DEVICE
static inline void usart_putreg(uintptr_t usart_base, unsigned int offset, uint32_t value) static inline void usart_putreg(uintptr_t usart_base,
unsigned int offset, uint32_t value)
{ {
putreg32(value, usart_base + offset); putreg32(value, usart_base + offset);
} }
@ -110,7 +111,8 @@ static inline void usart_putreg(uintptr_t usart_base, unsigned int offset, uint3
****************************************************************************/ ****************************************************************************/
#ifdef HAVE_RS232_DEVICE #ifdef HAVE_RS232_DEVICE
static inline uint32_t usart_getreg(uintptr_t usart_base, unsigned int offset) static inline uint32_t usart_getreg(uintptr_t usart_base,
unsigned int offset)
{ {
return getreg32(usart_base + offset); return getreg32(usart_base + offset);
} }
@ -218,7 +220,8 @@ void usart_reset(uintptr_t usart_base)
****************************************************************************/ ****************************************************************************/
#ifdef HAVE_RS232_DEVICE #ifdef HAVE_RS232_DEVICE
void usart_configure(uintptr_t usart_base, uint32_t baud, unsigned int parity, void usart_configure(uintptr_t usart_base,
uint32_t baud, unsigned int parity,
unsigned int nbits, bool stop2) unsigned int nbits, bool stop2)
{ {
uint32_t regval; uint32_t regval;
@ -281,8 +284,8 @@ void usart_configure(uintptr_t usart_base, uint32_t baud, unsigned int parity,
* *
* Description: * Description:
* Initialize a console for debug output. This function is called very * Initialize a console for debug output. This function is called very
* early in the initialization sequence to configure the serial console uart * early in the initialization sequence to configure the serial console
* (only). * uart (only).
* *
****************************************************************************/ ****************************************************************************/
@ -291,18 +294,23 @@ void up_consoleinit(void)
uint32_t pbamask = 0; uint32_t pbamask = 0;
uint32_t regval; uint32_t regval;
/* Setup GPIO pins fand enable module clocking or each configured USART/UART */ /* Setup GPIO pins fand enable module clocking or each configured
* USART/UART
*/
#ifdef CONFIG_AVR32_USART0_RS232 #ifdef CONFIG_AVR32_USART0_RS232
/* PINMUX_USART0_RXD and PINMUX_USART0_TXD must be defined in board.h. It /* PINMUX_USART0_RXD and PINMUX_USART0_TXD must be defined in board.h.
* must define them be be one of {PINMUX_USART0_RXD_1, PINMUX_USART0_RXD_2} * It must define them be be one of {PINMUX_USART0_RXD_1,
* and {PINMUX_USART_0TXD_1, PINMUX_USART0_TXD_2}, respectively. * PINMUX_USART0_RXD_2} and {PINMUX_USART_0TXD_1, PINMUX_USART0_TXD_2},
* respectively.
*/ */
at32uc3_configgpio(PINMUX_USART0_RXD); at32uc3_configgpio(PINMUX_USART0_RXD);
at32uc3_configgpio(PINMUX_USART0_TXD); at32uc3_configgpio(PINMUX_USART0_TXD);
/* Enable clocking to USART0 (This should be the default state after reset) */ /* Enable clocking to USART0
* (This should be the default state after reset)
*/
pbamask |= PM_PBAMASK_USART0; pbamask |= PM_PBAMASK_USART0;
@ -317,7 +325,9 @@ void up_consoleinit(void)
at32uc3_configgpio(PINMUX_USART1_RXD); at32uc3_configgpio(PINMUX_USART1_RXD);
at32uc3_configgpio(PINMUX_USART1_TXD); at32uc3_configgpio(PINMUX_USART1_TXD);
/* Enable clocking to USART1 (This should be the default state after reset) */ /* Enable clocking to USART1
* (This should be the default state after reset)
*/
pbamask |= PM_PBAMASK_USART1; pbamask |= PM_PBAMASK_USART1;
@ -331,7 +341,9 @@ void up_consoleinit(void)
at32uc3_configgpio(PINMUX_USART2_RXD); at32uc3_configgpio(PINMUX_USART2_RXD);
at32uc3_configgpio(PINMUX_USART2_TXD); at32uc3_configgpio(PINMUX_USART2_TXD);
/* Enable clocking to USART2 (This should be the default state after reset) */ /* Enable clocking to USART2
* (This should be the default state after reset)
*/
pbamask |= PM_PBAMASK_USART2; pbamask |= PM_PBAMASK_USART2;
@ -349,8 +361,9 @@ void up_consoleinit(void)
*/ */
#if defined(HAVE_SERIAL_CONSOLE) && !defined(USE_EARLYSERIALINIT) #if defined(HAVE_SERIAL_CONSOLE) && !defined(USE_EARLYSERIALINIT)
usart_configure(AVR32_CONSOLE_BASE, AVR32_CONSOLE_BAUD, AVR32_CONSOLE_PARITY, usart_configure(AVR32_CONSOLE_BASE, AVR32_CONSOLE_BAUD,
AVR32_CONSOLE_BITS, (bool)AVR32_CONSOLE_2STOP); AVR32_CONSOLE_PARITY, AVR32_CONSOLE_BITS,
(bool)AVR32_CONSOLE_2STOP);
#endif #endif
} }
@ -367,7 +380,8 @@ void up_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE #ifdef HAVE_SERIAL_CONSOLE
/* Wait until the TX to become ready */ /* Wait until the TX to become ready */
while ((usart_getreg(AVR32_CONSOLE_BASE, AVR32_USART_CSR_OFFSET) & USART_CSR_TXRDY) == 0); while ((usart_getreg(AVR32_CONSOLE_BASE,
AVR32_USART_CSR_OFFSET) & USART_CSR_TXRDY) == 0);
/* Then send the character */ /* Then send the character */

2
arch/avr/src/at32uc3/at32uc3_memorymap.h
View File

@ -92,7 +92,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_MEMORYMAP_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_MEMORYMAP_H */

43
arch/avr/src/at32uc3/at32uc3_pdca.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_pdca.h * arch/avr/src/at32uc3/at32uc3_pdca.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_PDCA_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_PDCA_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_PDCA_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_PDCA_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* DMA Channel Offsets **************************************************************/
/* DMA Channel Offsets ******************************************************/
#define AVR32_PDCA_CHAN_OFFSET(n) ((n) << 6) #define AVR32_PDCA_CHAN_OFFSET(n) ((n) << 6)
#define AVR32_PDCA_CHAN0_OFFSET 0x000 #define AVR32_PDCA_CHAN0_OFFSET 0x000
@ -42,7 +43,7 @@
#define AVR32_PDCA_CHAN6_OFFSET 0x180 #define AVR32_PDCA_CHAN6_OFFSET 0x180
#define AVR32_PDCA_CHAN7_OFFSET 0x1c0 #define AVR32_PDCA_CHAN7_OFFSET 0x1c0
/* Channel Register Offsets *********************************************************/ /* Channel Register Offsets *************************************************/
#define AVR32_PDCA_MAR_OFFSET 0x000 /* Memory Address Register */ #define AVR32_PDCA_MAR_OFFSET 0x000 /* Memory Address Register */
#define AVR32_PDCA_PSR_OFFSET 0x004 /* Peripheral Select Register */ #define AVR32_PDCA_PSR_OFFSET 0x004 /* Peripheral Select Register */
@ -57,7 +58,7 @@
#define AVR32_PDCA_IMR_OFFSET 0x028 /* Interrupt Mask Register */ #define AVR32_PDCA_IMR_OFFSET 0x028 /* Interrupt Mask Register */
#define AVR32_PDCA_ISR_OFFSET 0x02C /* Interrupt Status Register */ #define AVR32_PDCA_ISR_OFFSET 0x02C /* Interrupt Status Register */
/* DMA Channel Base Addresses *******************************************************/ /* DMA Channel Base Addresses ***********************************************/
#define AVR32_PDCA_CHAN_BASE(n) (AVR32_PDCA_BASE+AVR32_PDCA_CHAN_OFFSET(n)) #define AVR32_PDCA_CHAN_BASE(n) (AVR32_PDCA_BASE+AVR32_PDCA_CHAN_OFFSET(n))
#define AVR32_PDCA_CHAN0_BASE (AVR32_PDCA_BASE+AVR32_PDCA_CHAN0_OFFSET) #define AVR32_PDCA_CHAN0_BASE (AVR32_PDCA_BASE+AVR32_PDCA_CHAN0_OFFSET)
@ -69,7 +70,7 @@
#define AVR32_PDCA_CHAN6_BASE (AVR32_PDCA_BASE+AVR32_PDCA_CHAN6_OFFSET) #define AVR32_PDCA_CHAN6_BASE (AVR32_PDCA_BASE+AVR32_PDCA_CHAN6_OFFSET)
#define AVR32_PDCA_CHAN7_BASE (AVR32_PDCA_BASE+AVR32_PDCA_CHAN7_OFFSET) #define AVR32_PDCA_CHAN7_BASE (AVR32_PDCA_BASE+AVR32_PDCA_CHAN7_OFFSET)
/* Channel Register Addresses *******************************************************/ /* Channel Register Addresses ***********************************************/
#define AVR32_PDCA_MAR(n) (AVR32_PDCA_CHAN_BASE(n)+AVR32_PDCA_MAR_OFFSET) #define AVR32_PDCA_MAR(n) (AVR32_PDCA_CHAN_BASE(n)+AVR32_PDCA_MAR_OFFSET)
#define AVR32_PDCA_PSR(n) (AVR32_PDCA_CHAN_BASE(n)+AVR32_PDCA_PSR_OFFSET) #define AVR32_PDCA_PSR(n) (AVR32_PDCA_CHAN_BASE(n)+AVR32_PDCA_PSR_OFFSET)
@ -188,10 +189,12 @@
#define AVR32_PDCA_CHAN7_IMR (AVR32_PDCA_CHAN7_BASE+AVR32_PDCA_IMR_OFFSET) #define AVR32_PDCA_CHAN7_IMR (AVR32_PDCA_CHAN7_BASE+AVR32_PDCA_IMR_OFFSET)
#define AVR32_PDCA_CHAN7_ISR (AVR32_PDCA_CHAN7_BASE+AVR32_PDCA_ISR_OFFSET) #define AVR32_PDCA_CHAN7_ISR (AVR32_PDCA_CHAN7_BASE+AVR32_PDCA_ISR_OFFSET)
/* Channel Register Bit-field Definitions *******************************************/ /* Channel Register Bit-field Definitions ***********************************/
/* Memory Address Register Bit-field Definitions */ /* Memory Address Register Bit-field Definitions */
/* Memory Address Reload Register Bit-field Definitions */ /* Memory Address Reload Register Bit-field Definitions */
/* These registers hold a 32-bit address and contain no bit-fields */ /* These registers hold a 32-bit address and contain no bit-fields */
/* Peripheral Select Register Bit-field Definitions */ /* Peripheral Select Register Bit-field Definitions */
@ -214,6 +217,7 @@
# define PDCA_PSR_PID_ABDACTX (13 << PDCA_PSR_PID_SHIFT) /* ABDAC - TX */ # define PDCA_PSR_PID_ABDACTX (13 << PDCA_PSR_PID_SHIFT) /* ABDAC - TX */
/* Transfer Counter Register Bit-field Definitions */ /* Transfer Counter Register Bit-field Definitions */
/* Transfer Counter Reload Register Bit-field Definitions */ /* Transfer Counter Reload Register Bit-field Definitions */
#define PDCA_TCV_SHIFT (0) /* Bits 0-15: Transfer Counter Value */ #define PDCA_TCV_SHIFT (0) /* Bits 0-15: Transfer Counter Value */
@ -238,24 +242,27 @@
#define PDCA_SR_TEN (1 << 0) /* Bit 0: Transfer Enabled */ #define PDCA_SR_TEN (1 << 0) /* Bit 0: Transfer Enabled */
/* Interrupt Enable Register Bit-field Definitions */ /* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */ /* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */ /* Interrupt Mask Register Bit-field Definitions */
/* Interrupt Status Register Bit-field Definitions */ /* Interrupt Status Register Bit-field Definitions */
#define PDCA_INT_RCZ (1 << 0) /* Bit 0: Reload Counter Zero */ #define PDCA_INT_RCZ (1 << 0) /* Bit 0: Reload Counter Zero */
#define PDCA_INT_TRC (1 << 1) /* Bit 1: Transfer Complete */ #define PDCA_INT_TRC (1 << 1) /* Bit 1: Transfer Complete */
#define PDCA_INT_TERR (1 << 2) /* Bit 2: Transfer Error */ #define PDCA_INT_TERR (1 << 2) /* Bit 2: Transfer Error */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PDCA_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PDCA_H */

2
arch/avr/src/at32uc3/at32uc3_pinmux.h
View File

@ -49,7 +49,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PINMUX_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PINMUX_H */

47
arch/avr/src/at32uc3/at32uc3_pm.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_pm.h * arch/avr/src/at32uc3/at32uc3_pm.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_PM_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_PM_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_PM_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_PM_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_PM_MCCTRL_OFFSET 0x0000 /* Main Clock Control Register */ #define AVR32_PM_MCCTRL_OFFSET 0x0000 /* Main Clock Control Register */
#define AVR32_PM_CKSEL_OFFSET 0x0004 /* Clock Select Register */ #define AVR32_PM_CKSEL_OFFSET 0x0004 /* Clock Select Register */
@ -50,7 +50,9 @@
#define AVR32_PM_ISR_OFFSET 0x004c /* Interrupt Status Register */ #define AVR32_PM_ISR_OFFSET 0x004c /* Interrupt Status Register */
#define AVR32_PM_ICR_OFFSET 0x0050 /* Interrupt Clear Register */ #define AVR32_PM_ICR_OFFSET 0x0050 /* Interrupt Clear Register */
#define AVR32_PM_POSCSR_OFFSET 0x0054 /* Power and Oscillators Status Register */ #define AVR32_PM_POSCSR_OFFSET 0x0054 /* Power and Oscillators Status Register */
#define AVR32_PM_GCCTRL_OFFSET(n) (0x0060+((n)<<2)) /* 0x0060-0x070 Generic Clock Control Register */ #define AVR32_PM_GCCTRL_OFFSET(n) (0x0060+((n)<<2)) /* 0x0060-0x070 Generic Clock Control Register */
#define AVR32_PM_RCCR_OFFSET 0x00c0 /* RC Oscillator Calibration Register */ #define AVR32_PM_RCCR_OFFSET 0x00c0 /* RC Oscillator Calibration Register */
#define AVR32_PM_BGCR_OFFSET 0x00c4 /* Bandgap Calibration Register */ #define AVR32_PM_BGCR_OFFSET 0x00c4 /* Bandgap Calibration Register */
#define AVR32_PM_VREGCR_OFFSET 0x00c8 /* Linear Regulator Calibration Register */ #define AVR32_PM_VREGCR_OFFSET 0x00c8 /* Linear Regulator Calibration Register */
@ -60,7 +62,7 @@
#define AVR32_PM_GPLP0_OFFSET 0x0200 /* General Purpose Low-Power Register 0 */ #define AVR32_PM_GPLP0_OFFSET 0x0200 /* General Purpose Low-Power Register 0 */
#define AVR32_PM_GPLP1_OFFSET 0x0204 /* General Purpose Low-Power Register 1 */ #define AVR32_PM_GPLP1_OFFSET 0x0204 /* General Purpose Low-Power Register 1 */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_PM_MCCTRL (AVR32_PM_BASE+AVR32_PM_MCCTRL_OFFSET) #define AVR32_PM_MCCTRL (AVR32_PM_BASE+AVR32_PM_MCCTRL_OFFSET)
#define AVR32_PM_CKSEL (AVR32_PM_BASE+AVR32_PM_CKSEL_OFFSET) #define AVR32_PM_CKSEL (AVR32_PM_BASE+AVR32_PM_CKSEL_OFFSET)
@ -89,7 +91,7 @@
#define AVR32_PM_GPLP0 (AVR32_PM_BASE+AVR32_PM_GPLP0_OFFSET) #define AVR32_PM_GPLP0 (AVR32_PM_BASE+AVR32_PM_GPLP0_OFFSET)
#define AVR32_PM_GPLP1 (AVR32_PM_BASE+AVR32_PM_GPLP1_OFFSET) #define AVR32_PM_GPLP1 (AVR32_PM_BASE+AVR32_PM_GPLP1_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Main Clock Control Register Bit-field Definitions */ /* Main Clock Control Register Bit-field Definitions */
@ -98,6 +100,7 @@
# define PM_MCCTRL_MCSEL_SLOW (0 << PM_MCCTRL_MCSEL_SHIFT) /* slow clock is source */ # define PM_MCCTRL_MCSEL_SLOW (0 << PM_MCCTRL_MCSEL_SHIFT) /* slow clock is source */
# define PM_MCCTRL_MCSEL_OSC0 (1 << PM_MCCTRL_MCSEL_SHIFT) /* Oscillator 0 is source */ # define PM_MCCTRL_MCSEL_OSC0 (1 << PM_MCCTRL_MCSEL_SHIFT) /* Oscillator 0 is source */
# define PM_MCCTRL_MCSEL_PLL0 (2 << PM_MCCTRL_MCSEL_SHIFT) /* PLL0 is source */ # define PM_MCCTRL_MCSEL_PLL0 (2 << PM_MCCTRL_MCSEL_SHIFT) /* PLL0 is source */
#define PM_MCCTRL_OSC0EN (1 << 2) /* Bit 2: Oscillator 0 Enable */ #define PM_MCCTRL_OSC0EN (1 << 2) /* Bit 2: Oscillator 0 Enable */
#define PM_MCCTRL_OSC1EN (1 << 3) /* Bit 3: Oscillator 1 Enable */ #define PM_MCCTRL_OSC1EN (1 << 3) /* Bit 3: Oscillator 1 Enable */
@ -160,6 +163,7 @@
# define PM_PLL_PLLOPT_VCO (1 << PM_PLL_PLLOPT_SHIFT) /* Select the VCO frequency range */ # define PM_PLL_PLLOPT_VCO (1 << PM_PLL_PLLOPT_SHIFT) /* Select the VCO frequency range */
# define PM_PLL_PLLOPT_XTRADIV (2 << PM_PLL_PLLOPT_SHIFT) /* Enable the extra output divider */ # define PM_PLL_PLLOPT_XTRADIV (2 << PM_PLL_PLLOPT_SHIFT) /* Enable the extra output divider */
# define PM_PLL_PLLOPT_WBWDIS (4 << PM_PLL_PLLOPT_SHIFT) /* Disable the Wide-Bandwidth mode */ # define PM_PLL_PLLOPT_WBWDIS (4 << PM_PLL_PLLOPT_SHIFT) /* Disable the Wide-Bandwidth mode */
#define PM_PLL_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */ #define PM_PLL_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */
#define PM_PLL_PLLDIV_MASK (15 << PM_PLL_PLLDIV_SHIFT) #define PM_PLL_PLLDIV_MASK (15 << PM_PLL_PLLDIV_SHIFT)
#define PM_PLL_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */ #define PM_PLL_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */
@ -172,10 +176,11 @@
#define PM_OSCCTRL_MODE_SHIFT (0) /* Bits 0-2: Oscillator Mode */ #define PM_OSCCTRL_MODE_SHIFT (0) /* Bits 0-2: Oscillator Mode */
#define PM_OSCCTRL_MODE_MASK (7 << PM_OSCCTRL_MODE_SHIFT) #define PM_OSCCTRL_MODE_MASK (7 << PM_OSCCTRL_MODE_SHIFT)
# define PM_OSCCTRL_MODE_EXT (0 << PM_OSCCTRL_MODE_SHIFT) /* External clock */ # define PM_OSCCTRL_MODE_EXT (0 << PM_OSCCTRL_MODE_SHIFT) /* External clock */
# define PM_OSCCTRL_MODE_XTALp9 (4 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.4-0.9MHz */ # define PM_OSCCTRL_MODE_XTALP9 (4 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.4-0.9MHz */
# define PM_OSCCTRL_MODE_XTAL3 (5 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.9-3.0MHz */ # define PM_OSCCTRL_MODE_XTAL3 (5 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 0.9-3.0MHz */
# define PM_OSCCTRL_MODE_XTAL8 (6 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 3.0-8.0MHz */ # define PM_OSCCTRL_MODE_XTAL8 (6 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN 3.0-8.0MHz */
# define PM_OSCCTRL_MODE_XTALHI (7 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN above 8.0MHz */ # define PM_OSCCTRL_MODE_XTALHI (7 << PM_OSCCTRL_MODE_SHIFT) /* Crystal XIN above 8.0MHz */
#define PM_OSCCTRL_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator Startup Time */ #define PM_OSCCTRL_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator Startup Time */
#define PM_OSCCTRL_STARTUP_MASK (7 << PM_OSCCTRL_STARTUP_SHIFT) #define PM_OSCCTRL_STARTUP_MASK (7 << PM_OSCCTRL_STARTUP_SHIFT)
# define PM_OSCCTRL_STARTUP_0 (0 << PM_OSCCTRL_STARTUP_SHIFT) /* Num RCOsc cycles */ # define PM_OSCCTRL_STARTUP_0 (0 << PM_OSCCTRL_STARTUP_SHIFT) /* Num RCOsc cycles */
@ -193,6 +198,7 @@
#define PM_OSCCTRL32_MODE_MASK (7 << PM_OSCCTRL32_MODE_SHIFT) #define PM_OSCCTRL32_MODE_MASK (7 << PM_OSCCTRL32_MODE_SHIFT)
# define PM_OSCCTRL32_MODE_EXT (0 << PM_OSCCTRL32_MODE_SHIFT) /* External clock */ # define PM_OSCCTRL32_MODE_EXT (0 << PM_OSCCTRL32_MODE_SHIFT) /* External clock */
# define PM_OSCCTRL32_MODE_XTAL (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */ # define PM_OSCCTRL32_MODE_XTAL (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */
#define PM_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Startup Time */ #define PM_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Startup Time */
#define PM_OSCCTRL32_STARTUP_MASK (7 << PM_OSCCTRL32_STARTUP_SHIFT) #define PM_OSCCTRL32_STARTUP_MASK (7 << PM_OSCCTRL32_STARTUP_SHIFT)
# define PM_OSCCTRL32_STARTUP_0 (0 << PM_OSCCTRL32_STARTUP_SHIFT) /* Num RCOsc cycles */ # define PM_OSCCTRL32_STARTUP_0 (0 << PM_OSCCTRL32_STARTUP_SHIFT) /* Num RCOsc cycles */
@ -204,9 +210,13 @@
# define PM_OSCCTRL32_STARTUP_512K (6 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */ # define PM_OSCCTRL32_STARTUP_512K (6 << PM_OSCCTRL32_STARTUP_SHIFT) /* " " " " " " */
/* Interrupt Enable Register Bit-field Definitions */ /* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */ /* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */ /* Interrupt Mask Register Bit-field Definitions */
/* Interrupt Status Register Bit-field Definitions */ /* Interrupt Status Register Bit-field Definitions */
/* Interrupt Clear Register Bit-field Definitions */ /* Interrupt Clear Register Bit-field Definitions */
#define PM_INT_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */ #define PM_INT_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */
@ -273,6 +283,7 @@
# define PM_BOD_CTRL_OFF (xxx << PM_BOD_CTRL_SHIFT) /* BOD is off */ # define PM_BOD_CTRL_OFF (xxx << PM_BOD_CTRL_SHIFT) /* BOD is off */
# define PM_BOD_CTRL_RESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/can reset */ # define PM_BOD_CTRL_RESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/can reset */
# define PM_BOD_CTRL_NORESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/cannot reset */ # define PM_BOD_CTRL_NORESET (xxx << PM_BOD_CTRL_SHIFT) /* BOD enabled/cannot reset */
#define PM_BOD_FCD (1 << 16) /* Bit 16: BOD Fuse calibration done */ #define PM_BOD_FCD (1 << 16) /* Bit 16: BOD Fuse calibration done */
#define PM_BOD_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */ #define PM_BOD_KEY_SHIFT (24) /* Bits 24-31: Register Write protection */
#define PM_BOD_KEY_MASK (0xff << PM_BOD_KEY_SHIFT) #define PM_BOD_KEY_MASK (0xff << PM_BOD_KEY_SHIFT)
@ -296,7 +307,7 @@
/* These registers contain a 32-bit value with no smaller bit-field */ /* These registers contain a 32-bit value with no smaller bit-field */
/* GCLK Allocation ******************************************************************/ /* GCLK Allocation **********************************************************/
#define AVR32_PM_GCLK0 (0) /* GCLK0 pin */ #define AVR32_PM_GCLK0 (0) /* GCLK0 pin */
#define AVR32_PM_GCLK1 (1) /* GCLK2 pin */ #define AVR32_PM_GCLK1 (1) /* GCLK2 pin */
@ -304,16 +315,16 @@
#define AVR32_PM_GCLK_USBB (3) /* USBB */ #define AVR32_PM_GCLK_USBB (3) /* USBB */
#define AVR32_PM_GCLK_ABDAC (4) /* ABDAC */ #define AVR32_PM_GCLK_ABDAC (4) /* ABDAC */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PM_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PM_H */

48
arch/avr/src/at32uc3/at32uc3_pwm.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_pwm.h * arch/avr/src/at32uc3/at32uc3_pwm.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,28 +16,28 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_PWM_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_PWM_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_PWM_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_PWM_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* PWM Channel Offsets **************************************************************/ /* PWM Channel Offsets ******************************************************/
#define AVR32_PWM_CHAN_OFFSET(n) (0x200+((n)<<5)) #define AVR32_PWM_CHAN_OFFSET(n) (0x200+((n)<<5))
#define AVR32_PWM_CHAN0_OFFSET (0x200) #define AVR32_PWM_CHAN0_OFFSET (0x200)
#define AVR32_PWM_CHAN1_OFFSET (0x220) #define AVR32_PWM_CHAN1_OFFSET (0x220)
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_PWM_MR_OFFSET 0x000 /* PWM Mode Register */ #define AVR32_PWM_MR_OFFSET 0x000 /* PWM Mode Register */
#define AVR32_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */ #define AVR32_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */
@ -72,13 +72,13 @@
#define AVR32_PWMCH1_CCNT_OFFSET (AVR32_PWM_CHAN1_OFFSET+PWM_CCNT_OFFSET) #define AVR32_PWMCH1_CCNT_OFFSET (AVR32_PWM_CHAN1_OFFSET+PWM_CCNT_OFFSET)
#define AVR32_PWMCH1_CUPD_OFFSET (AVR32_PWM_CHAN1_OFFSET+PWM_CUPD_OFFSET) #define AVR32_PWMCH1_CUPD_OFFSET (AVR32_PWM_CHAN1_OFFSET+PWM_CUPD_OFFSET)
/* PWM Channel Base Addresses *******************************************************/ /* PWM Channel Base Addresses ***********************************************/
#define AVR32_PWM_CHAN_BASE(n) (AVR32_PWM_BASE+PWM_CHAN_OFFSET(n)) #define AVR32_PWM_CHAN_BASE(n) (AVR32_PWM_BASE+PWM_CHAN_OFFSET(n))
#define AVR32_PWM_CHAN0_BASE (AVR32_PWM_BASE+PWM_CHAN0_OFFSET) #define AVR32_PWM_CHAN0_BASE (AVR32_PWM_BASE+PWM_CHAN0_OFFSET)
#define AVR32_PWM_CHAN1_BASE (AVR32_PWM_BASE+PWM_CHAN1_OFFSET) #define AVR32_PWM_CHAN1_BASE (AVR32_PWM_BASE+PWM_CHAN1_OFFSET)
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_PWM_MR (AVR32_PWM_BASE+AVR32_PWM_MR_OFFSET) #define AVR32_PWM_MR (AVR32_PWM_BASE+AVR32_PWM_MR_OFFSET)
#define AVR32_PWM_ENA (AVR32_PWM_BASE+AVR32_PWM_ENA_OFFSET) #define AVR32_PWM_ENA (AVR32_PWM_BASE+AVR32_PWM_ENA_OFFSET)
@ -107,7 +107,7 @@
#define AVR32_PWMCH1_CCNT (AVR32_PWM_CHAN1_BASE+PWM_CCNT_OFFSET) #define AVR32_PWMCH1_CCNT (AVR32_PWM_CHAN1_BASE+PWM_CCNT_OFFSET)
#define AVR32_PWMCH1_CUPD (AVR32_PWM_CHAN1_BASE+PWM_CUPD_OFFSET) #define AVR32_PWMCH1_CUPD (AVR32_PWM_CHAN1_BASE+PWM_CUPD_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* PWM Mode Register Bit-field Definitions */ /* PWM Mode Register Bit-field Definitions */
@ -128,6 +128,7 @@
# define PWM_MR_PREA_MCKDIV256 (8 << PWM_MR_PREA_SHIFT) /* MCK/256 */ # define PWM_MR_PREA_MCKDIV256 (8 << PWM_MR_PREA_SHIFT) /* MCK/256 */
# define PWM_MR_PREA_MCKDIV512 (9 << PWM_MR_PREA_SHIFT) /* MCK/512 */ # define PWM_MR_PREA_MCKDIV512 (9 << PWM_MR_PREA_SHIFT) /* MCK/512 */
# define PWM_MR_PREA_MCKDIV1024 (10 << PWM_MR_PREA_SHIFT) /* MCK/1024 */ # define PWM_MR_PREA_MCKDIV1024 (10 << PWM_MR_PREA_SHIFT) /* MCK/1024 */
#define PWM_MR_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */ #define PWM_MR_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */
#define PWM_MR_DIVB_MASK (0xff << PWM_MR_DIVB_SHIFT) #define PWM_MR_DIVB_MASK (0xff << PWM_MR_DIVB_SHIFT)
# define PWM_MR_DIVB_OFF (0 << PWM_MR_DIVB_SHIFT) # define PWM_MR_DIVB_OFF (0 << PWM_MR_DIVB_SHIFT)
@ -147,14 +148,21 @@
# define PWM_MR_PREB_MCKDIV1024 (10 << PWM_MR_PREB_SHIFT) /* MCK/1024 */ # define PWM_MR_PREB_MCKDIV1024 (10 << PWM_MR_PREB_SHIFT) /* MCK/1024 */
/* PWM Enable Register Bit-field Definitions */ /* PWM Enable Register Bit-field Definitions */
/* PWM Disable Register Bit-field Definitions */ /* PWM Disable Register Bit-field Definitions */
/* PWM Status Register Bit-field Definitions */ /* PWM Status Register Bit-field Definitions */
/* PWM Interrupt Enable Register Bit-field Definitions */ /* PWM Interrupt Enable Register Bit-field Definitions */
/* PWM Interrupt Disable Register Bit-field Definitions */ /* PWM Interrupt Disable Register Bit-field Definitions */
/* PWM Interrupt Mask Register Bit-field Definitions */ /* PWM Interrupt Mask Register Bit-field Definitions */
/* PWM Interrupt Status Register Bit-field Definitions */ /* PWM Interrupt Status Register Bit-field Definitions */
#define PWM_CHID(n) (1 << (n)) /* Bit n: Channel ID n */ #define PWM_CHID(n) (1 << (n)) /* Bit n: Channel ID n */
#define PWM_CHID0 (1 << 0) /* Bit 0: Channel ID 0 */ #define PWM_CHID0 (1 << 0) /* Bit 0: Channel ID 0 */
#define PWM_CHID1 (1 << 1) /* Bit 1: Channel ID 1 */ #define PWM_CHID1 (1 << 1) /* Bit 1: Channel ID 1 */
#define PWM_CHID2 (1 << 2) /* Bit 2: Channel ID 2 */ #define PWM_CHID2 (1 << 2) /* Bit 2: Channel ID 2 */
@ -180,27 +188,31 @@
# define PWM_CMR_CPRE_MCKDIV1024 (10 << PWM_CMR_CPRE_SHIFT) /* MCK/1024 */ # define PWM_CMR_CPRE_MCKDIV1024 (10 << PWM_CMR_CPRE_SHIFT) /* MCK/1024 */
# define PWM_CMR_CPRE_CLKA (11 << PWM_CMR_CPRE_SHIFT) /* CLKA */ # define PWM_CMR_CPRE_CLKA (11 << PWM_CMR_CPRE_SHIFT) /* CLKA */
# define PWM_CMR_CPRE_CLKB (12 << PWM_CMR_CPRE_SHIFT) /* CLB */ # define PWM_CMR_CPRE_CLKB (12 << PWM_CMR_CPRE_SHIFT) /* CLB */
#define PWM_CMR_CALG (1 << 8) /* Bit 8: Channel Alignment */ #define PWM_CMR_CALG (1 << 8) /* Bit 8: Channel Alignment */
#define PWM_CMR_CPOL (1 << 9) /* Bit 9: Channel Polarity */ #define PWM_CMR_CPOL (1 << 9) /* Bit 9: Channel Polarity */
#define PWM_CMR_CPD (1 << 10) /* Bit 10: Channel Update Period */ #define PWM_CMR_CPD (1 << 10) /* Bit 10: Channel Update Period */
/* Channel Duty Cycle Register Bit-field Definitions */ /* Channel Duty Cycle Register Bit-field Definitions */
/* Channel Period Register Bit-field Definitions */ /* Channel Period Register Bit-field Definitions */
/* Channel Counter Register Bit-field Definitions */ /* Channel Counter Register Bit-field Definitions */
/* Channel Update Register Bit-field Definitions */ /* Channel Update Register Bit-field Definitions */
/* These registers hold a 32-bit value with bit-fiels */ /* These registers hold a 32-bit value with bit-fiels */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PWM_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PWM_H */

34
arch/avr/src/at32uc3/at32uc3_rtc.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_rtc.h * arch/avr/src/at32uc3/at32uc3_rtc.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_RTC_CTRL_OFFSET 0x00 /* Control Register */ #define AVR32_RTC_CTRL_OFFSET 0x00 /* Control Register */
#define AVR32_RTC_VAL_OFFSET 0x04 /* Value Register */ #define AVR32_RTC_VAL_OFFSET 0x04 /* Value Register */
@ -42,7 +42,7 @@
#define AVR32_RTC_ISR_OFFSET 0x1c /* Interrupt Status Register */ #define AVR32_RTC_ISR_OFFSET 0x1c /* Interrupt Status Register */
#define AVR32_RTC_ICR_OFFSET 0x20 /* Interrupt Clear Register */ #define AVR32_RTC_ICR_OFFSET 0x20 /* Interrupt Clear Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_RTC_CTRL (AVR32_RTC_BASE+AVR32_RTC_CTRL_OFFSET) #define AVR32_RTC_CTRL (AVR32_RTC_BASE+AVR32_RTC_CTRL_OFFSET)
#define AVR32_RTC_VAL (AVR32_RTC_BASE+AVR32_RTC_VAL_OFFSET) #define AVR32_RTC_VAL (AVR32_RTC_BASE+AVR32_RTC_VAL_OFFSET)
@ -53,7 +53,7 @@
#define AVR32_RTC_ISR (AVR32_RTC_BASE+AVR32_RTC_ISR_OFFSET) #define AVR32_RTC_ISR (AVR32_RTC_BASE+AVR32_RTC_ISR_OFFSET)
#define AVR32_RTC_ICR (AVR32_RTC_BASE+AVR32_RTC_ICR_OFFSET) #define AVR32_RTC_ICR (AVR32_RTC_BASE+AVR32_RTC_ICR_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Control Register Bit-field Definitions */ /* Control Register Bit-field Definitions */
@ -67,9 +67,11 @@
#define RTC_CTRL_CLKEN (1 << 16) /* Bit 16: Clock Enable */ #define RTC_CTRL_CLKEN (1 << 16) /* Bit 16: Clock Enable */
/* Value Register Bit-field Definitions */ /* Value Register Bit-field Definitions */
/* This is a 32-bit data register and, hence, has no bit field */ /* This is a 32-bit data register and, hence, has no bit field */
/* Top Register Bit-field Definitions */ /* Top Register Bit-field Definitions */
/* This is a 32-bit data register and, hence, has no bit field */ /* This is a 32-bit data register and, hence, has no bit field */
/* Interrupt Enable Register Bit-field Definitions /* Interrupt Enable Register Bit-field Definitions
@ -81,16 +83,16 @@
#define RTC_INT_TOPI (1 << 0) /* Bit 0: Top interrupt */ #define RTC_INT_TOPI (1 << 0) /* Bit 0: Top interrupt */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_RTC_H */

40
arch/avr/src/at32uc3/at32uc3_spi.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_spi.h * arch/avr/src/at32uc3/at32uc3_spi.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_SPI_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_SPI_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_SPI_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_SPI_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_SPI_CR_OFFSET 0x000 /* Control Register */ #define AVR32_SPI_CR_OFFSET 0x000 /* Control Register */
#define AVR32_SPI_MR_OFFSET 0x004 /* Mode Register */ #define AVR32_SPI_MR_OFFSET 0x004 /* Mode Register */
@ -47,7 +47,7 @@
#define AVR32_SPI_CSR3_OFFSET 0x03c /* Chip Select Register 3 */ #define AVR32_SPI_CSR3_OFFSET 0x03c /* Chip Select Register 3 */
#define AVR32_SPI_VERSION_OFFSET 0x0fc /* Version Register */ #define AVR32_SPI_VERSION_OFFSET 0x0fc /* Version Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_SPI0_CR (AVR32_SPI0_BASE+AVR32_SPI_CR_OFFSET) #define AVR32_SPI0_CR (AVR32_SPI0_BASE+AVR32_SPI_CR_OFFSET)
#define AVR32_SPI0_MR (AVR32_SPI0_BASE+AVR32_SPI_MR_OFFSET) #define AVR32_SPI0_MR (AVR32_SPI0_BASE+AVR32_SPI_MR_OFFSET)
@ -63,7 +63,7 @@
#define AVR32_SPI0_CSR3 (AVR32_SPI0_BASE+AVR32_SPI_CSR3_OFFSET) #define AVR32_SPI0_CSR3 (AVR32_SPI0_BASE+AVR32_SPI_CSR3_OFFSET)
#define AVR32_SPI0_VERSION (AVR32_SPI0_BASE+AVR32_SPI_VERSION_OFFSET) #define AVR32_SPI0_VERSION (AVR32_SPI0_BASE+AVR32_SPI_VERSION_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Control Register */ /* Control Register */
@ -74,7 +74,6 @@
/* Mode Register */ /* Mode Register */
#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */ #define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */ #define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */ #define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
@ -94,8 +93,11 @@
#define SPI_TDR_MASK (0xffff) #define SPI_TDR_MASK (0xffff)
/* Status Register */ /* Status Register */
/* Interrupt Enable Register */ /* Interrupt Enable Register */
/* Interrupt Disable Register */ /* Interrupt Disable Register */
/* Interrupt Mask Register */ /* Interrupt Mask Register */
#define SPI_INT_DRF (1 << 0) /* Bit 0: Receive Data Register Full */ #define SPI_INT_DRF (1 << 0) /* Bit 0: Receive Data Register Full */
@ -131,20 +133,20 @@
#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */ #define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */
#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT) #define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT)
/* Version Register (Values in the Version Register vary with the version of the IP /* Version Register (Values in the Version Register vary with the version of
* block implementation.) * the IP block implementation.)
*/ */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_SPI_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_SPI_H */

47
arch/avr/src/at32uc3/at32uc3_ssc.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_ssc.h * arch/avr/src/at32uc3/at32uc3_ssc.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_SSC_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_SSC_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_SSC_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_SSC_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_SSC_CR_OFFSET 0x00 /* Control Register */ #define AVR32_SSC_CR_OFFSET 0x00 /* Control Register */
#define AVR32_SSC_CMR_OFFSET 0x04 /* Clock Mode Register */ #define AVR32_SSC_CMR_OFFSET 0x04 /* Clock Mode Register */
@ -50,7 +50,7 @@
#define AVR32_SSC_IDR_OFFSET 0x48 /* Interrupt Disable Register */ #define AVR32_SSC_IDR_OFFSET 0x48 /* Interrupt Disable Register */
#define AVR32_SSC_IMR_OFFSET 0x4c /* Interrupt Mask Register */ #define AVR32_SSC_IMR_OFFSET 0x4c /* Interrupt Mask Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_SSC_CR (AVR32_SSC_BASE+AVR32_SSC_CR_OFFSET) #define AVR32_SSC_CR (AVR32_SSC_BASE+AVR32_SSC_CR_OFFSET)
#define AVR32_SSC_CMR (AVR32_SSC_BASE+AVR32_SSC_CMR_OFFSET) #define AVR32_SSC_CMR (AVR32_SSC_BASE+AVR32_SSC_CMR_OFFSET)
@ -69,7 +69,7 @@
#define AVR32_SSC_IDR (AVR32_SSC_BASE+AVR32_SSC_IDR_OFFSET) #define AVR32_SSC_IDR (AVR32_SSC_BASE+AVR32_SSC_IDR_OFFSET)
#define AVR32_SSC_IMR (AVR32_SSC_BASE+AVR32_SSC_IMR_OFFSET) #define AVR32_SSC_IMR (AVR32_SSC_BASE+AVR32_SSC_IMR_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Control Register Bit-field Definitions */ /* Control Register Bit-field Definitions */
@ -91,17 +91,20 @@
# define SSC_RCMR_CKS_DIVCLK (0 << SSC_RCMR_CKS_SHIFT) /* Divided clock */ # define SSC_RCMR_CKS_DIVCLK (0 << SSC_RCMR_CKS_SHIFT) /* Divided clock */
# define SSC_RCMR_CKS_TXCLK (1 << SSC_RCMR_CKS_SHIFT) /* TX_CLOCK clock signal */ # define SSC_RCMR_CKS_TXCLK (1 << SSC_RCMR_CKS_SHIFT) /* TX_CLOCK clock signal */
# define SSC_RCMR_CKS_RXCLK (2 << SSC_RCMR_CKS_SHIFT) /* RX_CLOCK pin */ # define SSC_RCMR_CKS_RXCLK (2 << SSC_RCMR_CKS_SHIFT) /* RX_CLOCK pin */
#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ #define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */
#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) #define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT)
# define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None (Input-only) */ # define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None (Input-only) */
# define SSC_RCMR_CKO_CONT (1 << SSC_RCMR_CKO_SHIFT) /* Continuous receive clock */ # define SSC_RCMR_CKO_CONT (1 << SSC_RCMR_CKO_SHIFT) /* Continuous receive clock */
# define SSC_RCMR_CKO_XFR (2 << SSC_RCMR_CKO_SHIFT) /* Receive clock only during data transfers */ # define SSC_RCMR_CKO_XFR (2 << SSC_RCMR_CKO_SHIFT) /* Receive clock only during data transfers */
#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ #define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */
#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */ #define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */
#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT) #define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT)
# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */ # define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */
# define SSC_RCMR_CKG_LOW (1 << SSC_RCMR_CKG_SHIFT) /* Enable if RX_FRAME_SYNC low */ # define SSC_RCMR_CKG_LOW (1 << SSC_RCMR_CKG_SHIFT) /* Enable if RX_FRAME_SYNC low */
# define SSC_RCMR_CKG_HIGH (2 << SSC_RCMR_CKG_SHIFT) /* Enable if RX_FRAME_SYNC high */ # define SSC_RCMR_CKG_HIGH (2 << SSC_RCMR_CKG_SHIFT) /* Enable if RX_FRAME_SYNC high */
#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */ #define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */
#define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT) #define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT)
# define SSC_RCMR_START_CONT (0 << SSC_RCMR_START_SHIFT) /* Continuous */ # define SSC_RCMR_START_CONT (0 << SSC_RCMR_START_SHIFT) /* Continuous */
@ -113,6 +116,7 @@
# define SSC_RCMR_START_CHANGE (6 << SSC_RCMR_START_SHIFT) /* RX_FRAME_SYNC change */ # define SSC_RCMR_START_CHANGE (6 << SSC_RCMR_START_SHIFT) /* RX_FRAME_SYNC change */
# define SSC_RCMR_START_BOTH (7 << SSC_RCMR_START_SHIFT) /* Any edge RX_FRAME_SYNC */ # define SSC_RCMR_START_BOTH (7 << SSC_RCMR_START_SHIFT) /* Any edge RX_FRAME_SYNC */
# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ # define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */
#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Selection */ #define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Selection */
#define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */ #define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */
#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) #define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT)
@ -137,6 +141,7 @@
# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* Driven Low during data transfer */ # define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* Driven Low during data transfer */
# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* Driven High during data transfer */ # define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* Driven High during data transfer */
# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* Toggling at each start of data transfer */ # define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* Toggling at each start of data transfer */
#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Receive Frame Sync Edge Detection */ #define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Receive Frame Sync Edge Detection */
#define SSC_RFMR_FSLENHI_SHIFT (28) /* Bits 28-31: Receive Frame Sync Length High Part */ #define SSC_RFMR_FSLENHI_SHIFT (28) /* Bits 28-31: Receive Frame Sync Length High Part */
#define SSC_RFMR_FSLENHI_MASK (15 << SSC_RFMR_FSLENHI_SHIFT) #define SSC_RFMR_FSLENHI_MASK (15 << SSC_RFMR_FSLENHI_SHIFT)
@ -148,17 +153,20 @@
# define SSC_TCMR_CKS_DIVCLK (0 << SSC_TCMR_CKS_SHIFT) /* Divided clock */ # define SSC_TCMR_CKS_DIVCLK (0 << SSC_TCMR_CKS_SHIFT) /* Divided clock */
# define SSC_TCMR_CKS_TXCLK (1 << SSC_TCMR_CKS_SHIFT) /* RX_CLOCK clock signal */ # define SSC_TCMR_CKS_TXCLK (1 << SSC_TCMR_CKS_SHIFT) /* RX_CLOCK clock signal */
# define SSC_TCMR_CKS_RXCLK (2 << SSC_TCMR_CKS_SHIFT) /* TX_CLOCK pin */ # define SSC_TCMR_CKS_RXCLK (2 << SSC_TCMR_CKS_SHIFT) /* TX_CLOCK pin */
#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ #define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */
#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) #define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT)
# define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None (Input-only) */ # define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None (Input-only) */
# define SSC_TCMR_CKO_CONT (1 << SSC_TCMR_CKO_SHIFT) /* Continuous transmit clock Output */ # define SSC_TCMR_CKO_CONT (1 << SSC_TCMR_CKO_SHIFT) /* Continuous transmit clock Output */
# define SSC_TCMR_CKO_XFR (2 << SSC_TCMR_CKO_SHIFT) /* Transmit clock only during data transfers Output */ # define SSC_TCMR_CKO_XFR (2 << SSC_TCMR_CKO_SHIFT) /* Transmit clock only during data transfers Output */
#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */ #define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */
#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT) #define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT)
# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */ # define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */
# define SSC_TCMR_CKG_LOW (1 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC low */ # define SSC_TCMR_CKG_LOW (1 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC low */
# define SSC_TCMR_CKG_HIGH (2 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC high */ # define SSC_TCMR_CKG_HIGH (2 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC high */
#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */ #define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */
#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT) #define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT)
# define SSC_TCMR_START_CONT (0 << SSC_TCMR_START_SHIFT) /* Continuous */ # define SSC_TCMR_START_CONT (0 << SSC_TCMR_START_SHIFT) /* Continuous */
@ -169,6 +177,7 @@
# define SSC_TCMR_START_RISING (5 << SSC_TCMR_START_SHIFT) /* Rising TX_FRAME_SYNC */ # define SSC_TCMR_START_RISING (5 << SSC_TCMR_START_SHIFT) /* Rising TX_FRAME_SYNC */
# define SSC_TCMR_START_CHANGE (6 << SSC_TCMR_START_SHIFT) /* TX_FRAME_SYNC change */ # define SSC_TCMR_START_CHANGE (6 << SSC_TCMR_START_SHIFT) /* TX_FRAME_SYNC change */
# define SSC_TCMR_START_BOTH (7 << SSC_TCMR_START_SHIFT) /* Any edge TX_FRAME_SYNC */ # define SSC_TCMR_START_BOTH (7 << SSC_TCMR_START_SHIFT) /* Any edge TX_FRAME_SYNC */
#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */ #define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */
#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT) #define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT)
#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */ #define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */
@ -192,12 +201,14 @@
# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* Driven Low during data transfer */ # define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* Driven Low during data transfer */
# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* Driven High during data transfer */ # define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* Driven High during data transfer */
# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* Toggling at each start of data transfer */ # define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* Toggling at each start of data transfer */
#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Transmit Frame Sync Data Enable */ #define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Transmit Frame Sync Data Enable */
#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Transmit Frame Sync Edge Detection */ #define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Transmit Frame Sync Edge Detection */
#define SSC_TFMR_FSLENHI_SHIFT (28) /* Bits 28-31: Transmit Frame Sync Length High Part */ #define SSC_TFMR_FSLENHI_SHIFT (28) /* Bits 28-31: Transmit Frame Sync Length High Part */
#define SSC_TFMR_FSLENHI_MASK (15 << SSC_TFMR_FSLENHI_SHIFT) #define SSC_TFMR_FSLENHI_MASK (15 << SSC_TFMR_FSLENHI_SHIFT)
/* Receive Holding Register Bit-field Definitions */ /* Receive Holding Register Bit-field Definitions */
/* Transmit Holding Register Bit-field Definitions */ /* Transmit Holding Register Bit-field Definitions */
/* These register hold 32-bit values with no bit-fields */ /* These register hold 32-bit values with no bit-fields */
@ -219,7 +230,9 @@
#define SSC_RC1R_MASK (0xffff) #define SSC_RC1R_MASK (0xffff)
/* Interrupt Enable Register Bit-field Definitions */ /* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */ /* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */ /* Interrupt Mask Register Bit-field Definitions */
#define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */ #define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */
@ -236,16 +249,16 @@
#define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable */ #define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable */
#define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable */ #define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_SSC_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_SSC_H */

48
arch/avr/src/at32uc3/at32uc3_tc.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_tc.h * arch/avr/src/at32uc3/at32uc3_tc.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_TC_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_TC_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_TC_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_TC_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Timer Channel Offset *************************************************************/
/* Timer Channel Offset *****************************************************/
#define AVR32_TC_CHAN_OFFSET(n) ((n) << 6) #define AVR32_TC_CHAN_OFFSET(n) ((n) << 6)
#define AVR32_TC_CHAN0_OFFSET (0x000) #define AVR32_TC_CHAN0_OFFSET (0x000)
#define AVR32_TC_CHAN1_OFFSET (0x040) #define AVR32_TC_CHAN1_OFFSET (0x040)
#define AVR32_TC_CHAN2_OFFSET (0x080) #define AVR32_TC_CHAN2_OFFSET (0x080)
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_TC_CCR_OFFSET 0x000 /* Channel Control Register */ #define AVR32_TC_CCR_OFFSET 0x000 /* Channel Control Register */
#define AVR32_TC_CMR_OFFSET 0x004 /* Channel Mode Register */ #define AVR32_TC_CMR_OFFSET 0x004 /* Channel Mode Register */
@ -97,14 +98,14 @@
#define AVR32_TC_BCR_OFFSET 0x0c0 /* Block Control Register */ #define AVR32_TC_BCR_OFFSET 0x0c0 /* Block Control Register */
#define AVR32_TC_BMR_OFFSET 0x0c4 /* Block Mode Register */ #define AVR32_TC_BMR_OFFSET 0x0c4 /* Block Mode Register */
/* Timer Channel Base Addresses *****************************************************/ /* Timer Channel Base Addresses *********************************************/
#define AVR32_TC_CHAN_BASE(n) (AVR32_TC_BASE+AVR32_TC_CHAN_OFFSET(n)) #define AVR32_TC_CHAN_BASE(n) (AVR32_TC_BASE+AVR32_TC_CHAN_OFFSET(n))
#define AVR32_TC_CHAN0_BASE (AVR32_TC_BASE+AVR32_TC_CHAN0_OFFSET) #define AVR32_TC_CHAN0_BASE (AVR32_TC_BASE+AVR32_TC_CHAN0_OFFSET)
#define AVR32_TC_CHAN1_BASE (AVR32_TC_BASE+AVR32_TC_CHAN1_OFFSET) #define AVR32_TC_CHAN1_BASE (AVR32_TC_BASE+AVR32_TC_CHAN1_OFFSET)
#define AVR32_TC_CHAN2_BASE (AVR32_TC_BASE+AVR32_TC_CHAN2_OFFSET) #define AVR32_TC_CHAN2_BASE (AVR32_TC_BASE+AVR32_TC_CHAN2_OFFSET)
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_TC_CCR(n) (AVR32_TC_CHAN0_BASE(n)+AVR32_TC_CCR_OFFSET) #define AVR32_TC_CCR(n) (AVR32_TC_CHAN0_BASE(n)+AVR32_TC_CCR_OFFSET)
#define AVR32_TC_CMRn(n) (AVR32_TC_CHAN0_BASE(n)+AVR32_TC_CMR_OFFSET) #define AVR32_TC_CMRn(n) (AVR32_TC_CHAN0_BASE(n)+AVR32_TC_CMR_OFFSET)
@ -153,7 +154,7 @@
#define AVR32_TC_BCR (AVR32_TC_BASE+AVR32_TC_BCR_OFFSET) #define AVR32_TC_BCR (AVR32_TC_BASE+AVR32_TC_BCR_OFFSET)
#define AVR32_TC_BMR (AVR32_TC_BASE+AVR32_TC_BMR_OFFSET) #define AVR32_TC_BMR (AVR32_TC_BASE+AVR32_TC_BMR_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Channel Control Register */ /* Channel Control Register */
@ -173,6 +174,7 @@
# define TC_CMR_TCCLKS_XC0 (5 << TC_CMR_TCCLKS_SHIFT) /* XC0 */ # define TC_CMR_TCCLKS_XC0 (5 << TC_CMR_TCCLKS_SHIFT) /* XC0 */
# define TC_CMR_TCCLKS_XC1 (6 << TC_CMR_TCCLKS_SHIFT) /* XC1 */ # define TC_CMR_TCCLKS_XC1 (6 << TC_CMR_TCCLKS_SHIFT) /* XC1 */
# define TC_CMR_TCCLKS_XC2 (7 << TC_CMR_TCCLKS_SHIFT) /* XC2 */ # define TC_CMR_TCCLKS_XC2 (7 << TC_CMR_TCCLKS_SHIFT) /* XC2 */
#define TC_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert */ #define TC_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert */
#define TC_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection */ #define TC_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection */
#define TC_CMR_BURST_MASK (3 << TC_CMR_BURST_SHIFT) #define TC_CMR_BURST_MASK (3 << TC_CMR_BURST_SHIFT)
@ -193,6 +195,7 @@
# define TC_CMR_ETRGEDG_RISING (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */ # define TC_CMR_ETRGEDG_RISING (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */
# define TC_CMR_ETRGEDG_FALLING (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */ # define TC_CMR_ETRGEDG_FALLING (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */
# define TC_CMR_ETRGEDG_BOTH (3 << TC_CMR_ETRGEDG_SHIFT) /* Each edge */ # define TC_CMR_ETRGEDG_BOTH (3 << TC_CMR_ETRGEDG_SHIFT) /* Each edge */
#define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */ #define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */
#define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */ #define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */
#define TC_CMR_LDRA_SHIFT (16) /* Bits 16-17: A Loading Selection */ #define TC_CMR_LDRA_SHIFT (16) /* Bits 16-17: A Loading Selection */
@ -201,6 +204,7 @@
# define TC_CMR_LDRA_RISING (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ # define TC_CMR_LDRA_RISING (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */
# define TC_CMR_LDRA_FALLING (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ # define TC_CMR_LDRA_FALLING (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */
# define TC_CMR_LDRA_BOTH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */ # define TC_CMR_LDRA_BOTH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */
#define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection */ #define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection */
#define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT) #define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT)
# define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */ # define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */
@ -218,12 +222,14 @@
# define TC_CMR_EEVTEDG_RISING (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */ # define TC_CMR_EEVTEDG_RISING (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */
# define TC_CMR_EEVTEDG_FALLING (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */ # define TC_CMR_EEVTEDG_FALLING (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */
# define TC_CMR_EEVTEDG_BOTH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */ # define TC_CMR_EEVTEDG_BOTH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */
#define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection */ #define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection */
#define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT) #define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT)
# define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB Input */ # define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB Input */
# define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 Output */ # define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 Output */
# define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 Output */ # define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 Output */
# define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 Output */ # define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 Output */
#define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable */ #define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable */
#define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection */ #define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection */
#define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT) #define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT)
@ -231,6 +237,7 @@
# define TC_CMR_WAVSEL_UPDWNNOT (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode no trigger on RC compare */ # define TC_CMR_WAVSEL_UPDWNNOT (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode no trigger on RC compare */
# define TC_CMR_WAVSEL_UPT (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode with trigger on RC compare */ # define TC_CMR_WAVSEL_UPT (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode with trigger on RC compare */
# define TC_CMR_WAVSEL_UPDWNT (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode with trigger on RC compare */ # define TC_CMR_WAVSEL_UPDWNT (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode with trigger on RC compare */
#define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA */ #define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA */
#define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT) #define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT)
# define TC_CMR_ACPA_NONE (0 << TC_CMR_ACPA_SHIFT) # define TC_CMR_ACPA_NONE (0 << TC_CMR_ACPA_SHIFT)
@ -297,8 +304,11 @@
#define TC_RC_MASK (0xffff) #define TC_RC_MASK (0xffff)
/* Channel Status Register (common) */ /* Channel Status Register (common) */
/* Interrupt Enable Register */ /* Interrupt Enable Register */
/* Channel Interrupt Disable Register */ /* Channel Interrupt Disable Register */
/* Channel Interrupt Mask Register */ /* Channel Interrupt Mask Register */
#define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow Status/Int */ #define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow Status/Int */
@ -328,12 +338,14 @@
# define TC_BMR_TC2XC0S_NONE (1 << TC_BMR_TC2XC0S_SHIFT) /* None */ # define TC_BMR_TC2XC0S_NONE (1 << TC_BMR_TC2XC0S_SHIFT) /* None */
# define TC_BMR_TC2XC0S_TIOA1 (2 << TC_BMR_TC2XC0S_SHIFT) /* TIOA1 */ # define TC_BMR_TC2XC0S_TIOA1 (2 << TC_BMR_TC2XC0S_SHIFT) /* TIOA1 */
# define TC_BMR_TC2XC0S_TIOA2 (3 << TC_BMR_TC2XC0S_SHIFT) /* TIOA2 */ # define TC_BMR_TC2XC0S_TIOA2 (3 << TC_BMR_TC2XC0S_SHIFT) /* TIOA2 */
#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */ #define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */
#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_SHIFT) #define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_SHIFT)
# define TC_BMR_TC2XC1S_TCLK1 (0 << TC_BMR_TC2XC1S_SHIFT) /* TCLK1 */ # define TC_BMR_TC2XC1S_TCLK1 (0 << TC_BMR_TC2XC1S_SHIFT) /* TCLK1 */
# define TC_BMR_TC2XC1S_NONE (1 << TC_BMR_TC2XC1S_SHIFT) /* None */ # define TC_BMR_TC2XC1S_NONE (1 << TC_BMR_TC2XC1S_SHIFT) /* None */
# define TC_BMR_TC2XC1S_TIOA0 (2 << TC_BMR_TC2XC1S_SHIFT) /* TIOA0 */ # define TC_BMR_TC2XC1S_TIOA0 (2 << TC_BMR_TC2XC1S_SHIFT) /* TIOA0 */
# define TC_BMR_TC2XC1S_TIOA2 (3 << TC_BMR_TC2XC1S_SHIFT) /* TIOA2 */ # define TC_BMR_TC2XC1S_TIOA2 (3 << TC_BMR_TC2XC1S_SHIFT) /* TIOA2 */
#define TC_BMR_TC2XC2S_SHIFT (3) /* Bits 4-5: External Clock Signal 2 Selection */ #define TC_BMR_TC2XC2S_SHIFT (3) /* Bits 4-5: External Clock Signal 2 Selection */
#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) #define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) /* TCLK2 */ # define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) /* TCLK2 */
@ -341,16 +353,16 @@
# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) /* TIOA0 */ # define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) /* TIOA0 */
# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) /* TIOA1 */ # define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) /* TIOA1 */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_TC_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_TC_H */

21
arch/avr/src/at32uc3/at32uc3_timerisr.c
View File

@ -42,8 +42,9 @@
/* The desired timer interrupt frequency is normally provided by the /* The desired timer interrupt frequency is normally provided by the
* definition CLK_TCK (see include/time.h). CLK_TCK defines the desired * definition CLK_TCK (see include/time.h). CLK_TCK defines the desired
* number of system clock ticks per second. That value is a user configurable * number of system clock ticks per second. That value is a user
* setting that defaults to 100 (100 ticks per second = 10 MS interval). * configurable setting that defaults to 100 (100 ticks per second = 10 MS
* interval).
* *
* However, the AVR RTC does not support that default value well and so, we * However, the AVR RTC does not support that default value well and so, we
* will insist that default is over-ridden by CONFIG_USEC_PER_TICK in the * will insist that default is over-ridden by CONFIG_USEC_PER_TICK in the
@ -172,10 +173,11 @@ void up_timer_initialize(void)
{ {
uint32_t regval; uint32_t regval;
/* Enable clocking: "The clock for the RTC bus interface (CLK_RTC) is generated /* Enable clocking: "The clock for the RTC bus interface (CLK_RTC) is
* by the Power Manager. This clock is enabled at reset, and can be disabled * generated by the Power Manager. This clock is enabled at reset, and can
* in the Power Manager. It is recommended to disable the RTC before disabling * be disabled in the Power Manager. It is recommended to disable the RTC
* the clock, to avoid freezing the RTC in an undefined state." * before disabling the clock, to avoid freezing the RTC in an undefined
* state."
*/ */
#if 0 #if 0
@ -188,14 +190,17 @@ void up_timer_initialize(void)
rtc_waitnotbusy(); rtc_waitnotbusy();
#ifdef AVR32_CLOCK_OSC32 #ifdef AVR32_CLOCK_OSC32
putreg32((RTC_CTRL_CLK32 | (AV32_PSEL << RTC_CTRL_PSEL_SHIFT) | RTC_CTRL_CLKEN), putreg32((RTC_CTRL_CLK32 | (AV32_PSEL << RTC_CTRL_PSEL_SHIFT) |
RTC_CTRL_CLKEN),
AVR32_RTC_CTRL); AVR32_RTC_CTRL);
#else #else
putreg32(((AV32_PSEL << RTC_CTRL_PSEL_SHIFT) | RTC_CTRL_CLKEN), putreg32(((AV32_PSEL << RTC_CTRL_PSEL_SHIFT) | RTC_CTRL_CLKEN),
AVR32_RTC_CTRL); AVR32_RTC_CTRL);
#endif #endif
/* Set the counter value to zero and the TOP value to AVR32_TOP (see above) */ /* Set the counter value to zero and the TOP value to AVR32_TOP
* (see above)
*/
rtc_waitnotbusy(); rtc_waitnotbusy();
putreg32(AV32_TOP, AVR32_RTC_TOP); putreg32(AV32_TOP, AVR32_RTC_TOP);

36
arch/avr/src/at32uc3/at32uc3_twi.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_twi.h * arch/avr/src/at32uc3/at32uc3_twi.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_TWI_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_TWI_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_TWI_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_TWI_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_TWI_CR_OFFSET 0x00 /* Control Register */ #define AVR32_TWI_CR_OFFSET 0x00 /* Control Register */
#define AVR32_TWI_MMR_OFFSET 0x04 /* Master Mode Register */ #define AVR32_TWI_MMR_OFFSET 0x04 /* Master Mode Register */
@ -45,7 +45,7 @@
#define AVR32_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */ #define AVR32_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */
#define AVR32_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */ #define AVR32_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_TWI_CR (AVR32_TWI_BASE+AVR32_TWI_CR_OFFSET) #define AVR32_TWI_CR (AVR32_TWI_BASE+AVR32_TWI_CR_OFFSET)
#define AVR32_TWI_MMR (AVR32_TWI_BASE+AVR32_TWI_MMR_OFFSET) #define AVR32_TWI_MMR (AVR32_TWI_BASE+AVR32_TWI_MMR_OFFSET)
@ -59,7 +59,7 @@
#define AVR32_TWI_RHR (AVR32_TWI_BASE+AVR32_TWI_RHR_OFFSET) #define AVR32_TWI_RHR (AVR32_TWI_BASE+AVR32_TWI_RHR_OFFSET)
#define AVR32_TWI_THR (AVR32_TWI_BASE+AVR32_TWI_THR_OFFSET) #define AVR32_TWI_THR (AVR32_TWI_BASE+AVR32_TWI_THR_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Control Register Bit-field Definitions */ /* Control Register Bit-field Definitions */
@ -79,6 +79,7 @@
# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */ # define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */
# define TWI_MMR_IADRSZ_2BYTES (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ # define TWI_MMR_IADRSZ_2BYTES (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */
# define TWI_MMR_IADRSZ_3BYTES (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ # define TWI_MMR_IADRSZ_3BYTES (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */
#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ #define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */ #define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */
#define TWI_MMR_DADR:_MASK (0x7f << TWI_MMR_DADR_SHIFT) #define TWI_MMR_DADR:_MASK (0x7f << TWI_MMR_DADR_SHIFT)
@ -102,8 +103,11 @@
#define TWI_CWGR_CKDIV:_MASK (7 << TWI_CWGR_CKDIV_SHIFT) #define TWI_CWGR_CKDIV:_MASK (7 << TWI_CWGR_CKDIV_SHIFT)
/* Status Register Bit-field Definitions */ /* Status Register Bit-field Definitions */
/* Interrupt Enable Register Bit-field Definitions */ /* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */ /* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */ /* Interrupt Mask Register Bit-field Definitions */
#define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed (automatically set / reset) */ #define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed (automatically set / reset) */
@ -130,16 +134,16 @@
#define TWI_THR_MASK (0xff) #define TWI_THR_MASK (0xff)
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_TWI_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_TWI_H */

40
arch/avr/src/at32uc3/at32uc3_usart.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_usart.h * arch/avr/src/at32uc3/at32uc3_usart.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_USART_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_USART_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_USART_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_USART_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_USART_CR_OFFSET 0x0000 /* Control Register */ #define AVR32_USART_CR_OFFSET 0x0000 /* Control Register */
#define AVR32_USART_MR_OFFSET 0x0004 /* Mode Register */ #define AVR32_USART_MR_OFFSET 0x0004 /* Mode Register */
@ -50,7 +50,7 @@
#define AVR32_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register */ #define AVR32_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register */
#define AVR32_USART_VERSION_OFFSET 0x00fc /* Version Register */ #define AVR32_USART_VERSION_OFFSET 0x00fc /* Version Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_USART0_CR (AVR32_USART0_BASE+AVR32_USART_CR_OFFSET) #define AVR32_USART0_CR (AVR32_USART0_BASE+AVR32_USART_CR_OFFSET)
#define AVR32_USART0_MR (AVR32_USART0_BASE+AVR32_USART_MR_OFFSET) #define AVR32_USART0_MR (AVR32_USART0_BASE+AVR32_USART_MR_OFFSET)
@ -103,7 +103,7 @@
#define AVR32_USART2_MAN (AVR32_USART2_BASE+AVR32_USART_MAN_OFFSET) #define AVR32_USART2_MAN (AVR32_USART2_BASE+AVR32_USART_MAN_OFFSET)
#define AVR32_USART2_VERSION (AVR32_USART2_BASE+AVR32_USART_VERSION_OFFSET) #define AVR32_USART2_VERSION (AVR32_USART2_BASE+AVR32_USART_VERSION_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* CR Register Bit-field Definitions */ /* CR Register Bit-field Definitions */
@ -141,11 +141,13 @@
# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */ # define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */
# define USART_MR_MODE_MASTER (14 << USART_MR_MODE_SHIFT) /* SPI Master */ # define USART_MR_MODE_MASTER (14 << USART_MR_MODE_SHIFT) /* SPI Master */
# define USART_MR_MODE_SLAVE (15 << USART_MR_MODE_SHIFT) /* SPI Slave */ # define USART_MR_MODE_SLAVE (15 << USART_MR_MODE_SHIFT) /* SPI Slave */
#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */ #define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */
#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT) #define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT)
# define USART_MR_USCLKS_CLKUSART (0 << USART_MR_USCLKS_SHIFT) /* CLK_USART */ # define USART_MR_USCLKS_CLKUSART (0 << USART_MR_USCLKS_SHIFT) /* CLK_USART */
# define USART_MR_USCLKS_DIV (1 << USART_MR_USCLKS_SHIFT) /* CLK_USART/DIV */ # define USART_MR_USCLKS_DIV (1 << USART_MR_USCLKS_SHIFT) /* CLK_USART/DIV */
# define USART_MR_USCLKS_CLK (3 << USART_MR_USCLKS_SHIFT) /* CLK */ # define USART_MR_USCLKS_CLK (3 << USART_MR_USCLKS_SHIFT) /* CLK */
#define USART_MR_CHRL_SHIFT (6) /* Bit 6-7: Character Length */ #define USART_MR_CHRL_SHIFT (6) /* Bit 6-7: Character Length */
#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT) #define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT)
# define USART_MR_CHRL_BITS(n) (((n) - 5) << USART_MR_CHRL_SHIFT) # define USART_MR_CHRL_BITS(n) (((n) - 5) << USART_MR_CHRL_SHIFT)
@ -153,6 +155,7 @@
# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */ # define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */
# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */ # define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */
# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */ # define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */
#define USART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select */ #define USART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select */
#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase */ #define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase */
#define USART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type */ #define USART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type */
@ -163,17 +166,20 @@
# define USART_MR_PAR_MARK (3 << USART_MR_PAR_SHIFT) /* Parity forced to 1 (Mark) */ # define USART_MR_PAR_MARK (3 << USART_MR_PAR_SHIFT) /* Parity forced to 1 (Mark) */
# define USART_MR_PAR_NONE (4 << USART_MR_PAR_SHIFT) /* No parity */ # define USART_MR_PAR_NONE (4 << USART_MR_PAR_SHIFT) /* No parity */
# define USART_MR_PAR_MULTIDROP (6 << USART_MR_PAR_SHIFT) /* Multidrop mode */ # define USART_MR_PAR_MULTIDROP (6 << USART_MR_PAR_SHIFT) /* Multidrop mode */
#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits */ #define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits */
#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT) #define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT)
# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit */ # define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit */
# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ # define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */
# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits */ # define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits */
#define USART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */ #define USART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */
#define USART_MR_CHMODE_MASK (3 << USART_MR_CHMODE_SHIFT) #define USART_MR_CHMODE_MASK (3 << USART_MR_CHMODE_SHIFT)
# define USART_MR_CHMODE_NORMAL (0 << USART_MR_CHMODE_SHIFT) /* Normal Mode */ # define USART_MR_CHMODE_NORMAL (0 << USART_MR_CHMODE_SHIFT) /* Normal Mode */
# define USART_MR_CHMODE_AUTO (1 << USART_MR_CHMODE_SHIFT) /* Automatic Echo */ # define USART_MR_CHMODE_AUTO (1 << USART_MR_CHMODE_SHIFT) /* Automatic Echo */
# define USART_MR_CHMODE_LLPBK (2 << USART_MR_CHMODE_SHIFT) /* Local Loopback */ # define USART_MR_CHMODE_LLPBK (2 << USART_MR_CHMODE_SHIFT) /* Local Loopback */
# define USART_MR_CHMODE_RLPBK (3 << USART_MR_CHMODE_SHIFT) /* Remote Loopback */ # define USART_MR_CHMODE_RLPBK (3 << USART_MR_CHMODE_SHIFT) /* Remote Loopback */
#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order */ #define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order */
#define USART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity */ #define USART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity */
#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length */ #define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length */
@ -289,6 +295,7 @@
# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */ # define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */
# define USART_MAN_TXPP_ZER0ONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */ # define USART_MAN_TXPP_ZER0ONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */
# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */ # define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */
#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity */ #define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity */
#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length */ #define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length */
#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT) #define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT)
@ -298,6 +305,7 @@
# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */ # define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */
# define USART_MAN_RXPP_ZER0ONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */ # define USART_MAN_RXPP_ZER0ONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */
# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */ # define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */
#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity */ #define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity */
#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation */ #define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation */
@ -308,16 +316,16 @@
#define USART_VARIANT_SHIFT (16) /* Bits 16-19: (Reserved) */ #define USART_VARIANT_SHIFT (16) /* Bits 16-19: (Reserved) */
#define USART_VARIANT_MASK (15 << USART_VARIANT_SHIFT) #define USART_VARIANT_MASK (15 << USART_VARIANT_SHIFT)
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_USART_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_USART_H */

102
arch/avr/src/at32uc3/at32uc3_usbb.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_usbb.h * arch/avr/src/at32uc3/at32uc3_usbb.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_USBB_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_USBB_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_USBB_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_USBB_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
/* USB Device Registers */ /* USB Device Registers */
@ -293,7 +293,7 @@
#define AVR32_USBB_UNAME2_OFFSET 0x0828 /* IP Name Register 2 */ #define AVR32_USBB_UNAME2_OFFSET 0x0828 /* IP Name Register 2 */
#define AVR32_USBB_USBFSM_OFFSET 0x082c /* USB Finite State Machine Status Register */ #define AVR32_USBB_USBFSM_OFFSET 0x082c /* USB Finite State Machine Status Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
/* USB Device Registers */ /* USB Device Registers */
@ -550,8 +550,10 @@
#define AVR32_USBB_UNAME2 (AVR32_USB_BASE+AVR32_USBB_UNAME2_OFFSET) #define AVR32_USBB_UNAME2 (AVR32_USB_BASE+AVR32_USBB_UNAME2_OFFSET)
#define AVR32_USBB_USBFSM (AVR32_USB_BASE+AVR32_USBB_USBFSM_OFFSET) #define AVR32_USBB_USBFSM (AVR32_USB_BASE+AVR32_USBB_USBFSM_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* USB Device Registers Bit-field Definitions ***************************************/
/* USB Device Registers Bit-field Definitions *******************************/
/* Device General Control Register Bit-field Definitions */ /* Device General Control Register Bit-field Definitions */
#define USBB_UDCON_UADD_SHIFT (0) /* Bits 0-6: USB Address */ #define USBB_UDCON_UADD_SHIFT (0) /* Bits 0-6: USB Address */
@ -562,10 +564,15 @@
#define USBB_UDCON_LS (1 << 12) /* Bit 12: Low-Speed Mode Force */ #define USBB_UDCON_LS (1 << 12) /* Bit 12: Low-Speed Mode Force */
/* Device Global Interrupt Register Bit-field Definitions */ /* Device Global Interrupt Register Bit-field Definitions */
/* Device Global Interrupt Clear Register Bit-field Definitions */ /* Device Global Interrupt Clear Register Bit-field Definitions */
/* Device Global Interrupt Set Register Bit-field Definitions */ /* Device Global Interrupt Set Register Bit-field Definitions */
/* Device Global Interrupt Enable Register Bit-field Definitions */ /* Device Global Interrupt Enable Register Bit-field Definitions */
/* Device Global Interrupt Enable Clear Register Bit-field Definitions */ /* Device Global Interrupt Enable Clear Register Bit-field Definitions */
/* Device Global Interrupt Enable Set Register Bit-field Definitions */ /* Device Global Interrupt Enable Set Register Bit-field Definitions */
#define USBB_UDINT_SUSP (1 << 0) /* Bit 0: Suspend Interrupt */ #define USBB_UDINT_SUSP (1 << 0) /* Bit 0: Suspend Interrupt */
@ -574,7 +581,9 @@
#define USBB_UDINT_WAKEUP (1 << 4) /* Bit 4: Wake-Up Interrupt */ #define USBB_UDINT_WAKEUP (1 << 4) /* Bit 4: Wake-Up Interrupt */
#define USBB_UDINT_EORSM (1 << 5) /* Bit 5: End of Resume Interrupt */ #define USBB_UDINT_EORSM (1 << 5) /* Bit 5: End of Resume Interrupt */
#define USBB_UDINT_UPRSM (1 << 6) /* Bit 6: Upstream Resume Interrupt */ #define USBB_UDINT_UPRSM (1 << 6) /* Bit 6: Upstream Resume Interrupt */
#define USBB_UDINT_EPINT(n) (1 << ((n)+12)) /* Endpoint n Interrupt */ #define USBB_UDINT_EPINT(n) (1 << ((n)+12)) /* Endpoint n Interrupt */
#define USBB_UDINT_EP0INT (1 << 12) /* Bit 12: Endpoint n Interrupt */ #define USBB_UDINT_EP0INT (1 << 12) /* Bit 12: Endpoint n Interrupt */
#define USBB_UDINT_EP1INT (1 << 13) /* Bit 13: Endpoint n Interrupt */ #define USBB_UDINT_EP1INT (1 << 13) /* Bit 13: Endpoint n Interrupt */
#define USBB_UDINT_EP2INT (1 << 14) /* Bit 14: Endpoint n Interrupt */ #define USBB_UDINT_EP2INT (1 << 14) /* Bit 14: Endpoint n Interrupt */
@ -582,7 +591,9 @@
#define USBB_UDINT_EP4INT (1 << 16) /* Bit 16: Endpoint n Interrupt */ #define USBB_UDINT_EP4INT (1 << 16) /* Bit 16: Endpoint n Interrupt */
#define USBB_UDINT_EP5INT (1 << 17) /* Bit 17: Endpoint n Interrupt */ #define USBB_UDINT_EP5INT (1 << 17) /* Bit 17: Endpoint n Interrupt */
#define USBB_UDINT_EP6INT (1 << 18) /* Bit 18: Endpoint n Interrupt */ #define USBB_UDINT_EP6INT (1 << 18) /* Bit 18: Endpoint n Interrupt */
#define USBB_UDINT_DMAINT(n) (1 << ((n)+24)) /* DMA Channel n Interrupt */ #define USBB_UDINT_DMAINT(n) (1 << ((n)+24)) /* DMA Channel n Interrupt */
#define USBB_UDINT_DMA1INT (1 << 25) /* Bit 25: DMA Channel n Interrupt */ #define USBB_UDINT_DMA1INT (1 << 25) /* Bit 25: DMA Channel n Interrupt */
#define USBB_UDINT_DMA2INT (1 << 26) /* Bit 26: DMA Channel 1 Interrupt */ #define USBB_UDINT_DMA2INT (1 << 26) /* Bit 26: DMA Channel 1 Interrupt */
#define USBB_UDINT_DMA3INT (1 << 27) /* Bit 27: DMA Channel 2 Interrupt */ #define USBB_UDINT_DMA3INT (1 << 27) /* Bit 27: DMA Channel 2 Interrupt */
@ -593,6 +604,7 @@
/* Endpoint Enable/Reset Register Bit-field Definitions */ /* Endpoint Enable/Reset Register Bit-field Definitions */
#define USBB_UERST_EPRST(n) (1 << ((n)+16)) /* Endpoint n Reset */ #define USBB_UERST_EPRST(n) (1 << ((n)+16)) /* Endpoint n Reset */
#define USBB_UERST_EPRST0 (1 << 16) /* Bit 16: Endpoint 0 Reset */ #define USBB_UERST_EPRST0 (1 << 16) /* Bit 16: Endpoint 0 Reset */
#define USBB_UERST_EPRST1 (1 << 17) /* Bit 17: Endpoint 1 Reset */ #define USBB_UERST_EPRST1 (1 << 17) /* Bit 17: Endpoint 1 Reset */
#define USBB_UERST_EPRST2 (1 << 18) /* Bit 18: Endpoint 2 Reset */ #define USBB_UERST_EPRST2 (1 << 18) /* Bit 18: Endpoint 2 Reset */
@ -623,6 +635,7 @@
# define USBB_UECFG_EPBK_1 (0 << USBB_UECFG_EPBK_SHIFT) /* 1 (single-bank endpoint) */ # define USBB_UECFG_EPBK_1 (0 << USBB_UECFG_EPBK_SHIFT) /* 1 (single-bank endpoint) */
# define USBB_UECFG_EPBK_2 (1 << USBB_UECFG_EPBK_SHIFT) /* 2 (double-bank endpoint) */ # define USBB_UECFG_EPBK_2 (1 << USBB_UECFG_EPBK_SHIFT) /* 2 (double-bank endpoint) */
# define USBB_UECFG_EPBK_3 (2 << USBB_UECFG_EPBK_SHIFT) /* 3 (triple-bank endpoint) */ # define USBB_UECFG_EPBK_3 (2 << USBB_UECFG_EPBK_SHIFT) /* 3 (triple-bank endpoint) */
#define USBB_UECFG_EPSIZE_SHIFT (4) /* Bits 4-6: Endpoint Size */ #define USBB_UECFG_EPSIZE_SHIFT (4) /* Bits 4-6: Endpoint Size */
#define USBB_UECFG_EPSIZE_MASK (7 << USBB_UECFG_EPSIZE_SHIFT) #define USBB_UECFG_EPSIZE_MASK (7 << USBB_UECFG_EPSIZE_SHIFT)
# define USBB_UECFG_EPSIZE_8 (0 << USBB_UECFG_EPSIZE_SHIFT) /* 8 bytes */ # define USBB_UECFG_EPSIZE_8 (0 << USBB_UECFG_EPSIZE_SHIFT) /* 8 bytes */
@ -633,6 +646,7 @@
# define USBB_UECFG_EPSIZE_256 (5 << USBB_UECFG_EPSIZE_SHIFT) /* 256 bytes */ # define USBB_UECFG_EPSIZE_256 (5 << USBB_UECFG_EPSIZE_SHIFT) /* 256 bytes */
# define USBB_UECFG_EPSIZE_512 (6 << USBB_UECFG_EPSIZE_SHIFT) /* 512 bytes */ # define USBB_UECFG_EPSIZE_512 (6 << USBB_UECFG_EPSIZE_SHIFT) /* 512 bytes */
# define USBB_UECFG_EPSIZE_1024 (7 << USBB_UECFG_EPSIZE_SHIFT) /* 1024 bytes */ # define USBB_UECFG_EPSIZE_1024 (7 << USBB_UECFG_EPSIZE_SHIFT) /* 1024 bytes */
#define USBB_UECFG_EPDIR (1 << 8) /* Bit 8: Endpoint Direction */ #define USBB_UECFG_EPDIR (1 << 8) /* Bit 8: Endpoint Direction */
#define USBB_UECFG_AUTOSW (1 << 9) /* Bit 9: Automatic Switch */ #define USBB_UECFG_AUTOSW (1 << 9) /* Bit 9: Automatic Switch */
#define USBB_UECFG_EPTYPE_SHIFT (11) /* Bits 11-12: Endpoint Type */ #define USBB_UECFG_EPTYPE_SHIFT (11) /* Bits 11-12: Endpoint Type */
@ -643,7 +657,9 @@
# define USBB_UECFG_EPTYPE_INTR (3 << USBB_UECFG_EPTYPE_SHIFT) /* Interrupt */ # define USBB_UECFG_EPTYPE_INTR (3 << USBB_UECFG_EPTYPE_SHIFT) /* Interrupt */
/* Endpoint Status Register Bit-field Definitions (common fields) */ /* Endpoint Status Register Bit-field Definitions (common fields) */
/* Endpoint Status Clear Register Bit-field Definitions */ /* Endpoint Status Clear Register Bit-field Definitions */
/* Endpoint Status Set Register Bit-field Definitions (common fields) */ /* Endpoint Status Set Register Bit-field Definitions (common fields) */
#define USBB_UESTA_TXINI (1 << 0) /* Bit 0: Transmitted IN Data Interrupt */ #define USBB_UESTA_TXINI (1 << 0) /* Bit 0: Transmitted IN Data Interrupt */
@ -663,21 +679,24 @@
#define USBB_UESTA_DTSEQ_MASK (3 << USBB_UESTA_DTSEQ_SHIFT) #define USBB_UESTA_DTSEQ_MASK (3 << USBB_UESTA_DTSEQ_SHIFT)
# define USBB_UESTA_DTSEQ_DATA0 (0 << USBB_UESTA_DTSEQ_SHIFT) /* Data0 */ # define USBB_UESTA_DTSEQ_DATA0 (0 << USBB_UESTA_DTSEQ_SHIFT) /* Data0 */
# define USBB_UESTA_DTSEQ_DATA1 (1 << USBB_UESTA_DTSEQ_SHIFT) /* Data1 */ # define USBB_UESTA_DTSEQ_DATA1 (1 << USBB_UESTA_DTSEQ_SHIFT) /* Data1 */
#define USBB_UESTA_NBUSYBK_SHIFT (12) /* Bits 12-13: Number of Busy Banks */ #define USBB_UESTA_NBUSYBK_SHIFT (12) /* Bits 12-13: Number of Busy Banks */
#define USBB_UESTA_NBUSYBK_MASK (3 << USBB_UESTA_NBUSYBK_SHIFT) #define USBB_UESTA_NBUSYBK_MASK (3 << USBB_UESTA_NBUSYBK_SHIFT)
# define USBB_UESTA_NBUSYBK_NONE (0 << USBB_UESTA_NBUSYBK_SHIFT) /* 0 (all banks free) */ # define USBB_UESTA_NBUSYBK_NONE (0 << USBB_UESTA_NBUSYBK_SHIFT) /* 0 (all banks free) */
# define USBB_UESTA_NBUSYBK_1BANK (1 << USBB_UESTA_NBUSYBK_SHIFT) /* 1 */ # define USBB_UESTA_NBUSYBK_1BANK (1 << USBB_UESTA_NBUSYBK_SHIFT) /* 1 */
# define USBB_UESTA_NBUSYBK_2BANKS (2 << USBB_UESTA_NBUSYBK_SHIFT) /* 2 */ # define USBB_UESTA_NBUSYBK_2BANKS (2 << USBB_UESTA_NBUSYBK_SHIFT) /* 2 */
# define USBB_UESTA_NBUSYBK_3BANKS (3 << USBB_UESTA_NBUSYBK_SHIFT) /* 3 */ # define USBB_UESTA_NBUSYBK_3BANKS (3 << USBB_UESTA_NBUSYBK_SHIFT) /* 3 */
#define USBB_UESTA_CURRBK_SHIFT (14) /* Bits 14-15: Current Bank */ #define USBB_UESTA_CURRBK_SHIFT (14) /* Bits 14-15: Current Bank */
#define USBB_UESTA_CURRBK_MASK (3 << USBB_UESTA_CURRBK_SHIFT) #define USBB_UESTA_CURRBK_MASK (3 << USBB_UESTA_CURRBK_SHIFT)
# define USBB_UESTA_CURRBK_BANK0 (0 << USBB_UESTA_CURRBK_SHIFT) /* Bank0 */ # define USBB_UESTA_CURRBK_BANK0 (0 << USBB_UESTA_CURRBK_SHIFT) /* Bank0 */
# define USBB_UESTA_CURRBK_BANK1 (1 << USBB_UESTA_CURRBK_SHIFT) /* Bank1 */ # define USBB_UESTA_CURRBK_BANK1 (1 << USBB_UESTA_CURRBK_SHIFT) /* Bank1 */
# define USBB_UESTA_CURRBK_BANK2 (2 << USBB_UESTA_CURRBK_SHIFT) /* Bank2 */ # define USBB_UESTA_CURRBK_BANK2 (2 << USBB_UESTA_CURRBK_SHIFT) /* Bank2 */
#define USBB_UESTA_RWALL (1 << 16) /* Bit 16: Read/Write Allowed */ #define USBB_UESTA_RWALL (1 << 16) /* Bit 16: Read/Write Allowed */
#define USBB_UESTA_CTRLDIR (1 << 17) /* Bit 17: Control Direction */ #define USBB_UESTA_CTRLDIR (1 << 17) /* Bit 17: Control Direction */
#define USBB_UESTA_CFGOK (1 << 18) /* Bit 18: Configuration OK Status */ #define USBB_UESTA_CFGOK (1 << 18) /* Bit 18: Configuration OK Status */
#define USBB_UESTA_BYCT_SHIFT (20) /* Bits 20-30: Byte Count */ #define USBB_UESTA_BYCT_SHIFT (20) /* Bits 20-30: Byte Count */
#define USBB_UESTA_BYCT_MASK (0x7ff << USBB_UESTA_BYCT_SHIFT) #define USBB_UESTA_BYCT_MASK (0x7ff << USBB_UESTA_BYCT_SHIFT)
/* Endpoint Status Set Register Bit-field Definitions (only in UESTASET) */ /* Endpoint Status Set Register Bit-field Definitions (only in UESTASET) */
@ -685,7 +704,9 @@
#define USBB_UESTASET_NBUSYBKS (1 << 12) /* Bit 12 */ #define USBB_UESTASET_NBUSYBKS (1 << 12) /* Bit 12 */
/* Endpoint Control Register Bit-field Definitions */ /* Endpoint Control Register Bit-field Definitions */
/* Endpoint Control Set Register Bit-field Definitions */ /* Endpoint Control Set Register Bit-field Definitions */
/* Endpoint Control Clear Register Bit-field Definitions */ /* Endpoint Control Clear Register Bit-field Definitions */
#define USBB_UECON_TXINE (1 << 0) /* Bit 0: Transmitted IN Data Interrupt Enable */ #define USBB_UECON_TXINE (1 << 0) /* Bit 0: Transmitted IN Data Interrupt Enable */
@ -705,11 +726,14 @@
#define USBB_UECON_RSTDT (1 << 18) /* Bit 18: Reset Data Toggle (SET only) */ #define USBB_UECON_RSTDT (1 << 18) /* Bit 18: Reset Data Toggle (SET only) */
#define USBB_UECON_STALLRQ (1 << 19) /* Bit 19: STALL Request */ #define USBB_UECON_STALLRQ (1 << 19) /* Bit 19: STALL Request */
/* Device DMA Channel Next Descriptor Address Register Bit-field Definitions */ /* Device DMA Channel Next Descriptor Address Register Bit-field
* Definitions
*/
#define UDDMA_NEXTDESC_MASK (0xfffffff0) #define UDDMA_NEXTDESC_MASK (0xfffffff0)
/* Device DMA Channel HSB Address Register Bit-field Definitions */ /* Device DMA Channel HSB Address Register Bit-field Definitions */
/* This register holds a 32-bit address with internal bit fields */ /* This register holds a 32-bit address with internal bit fields */
/* Device DMA Channel Control Register Bit-field Definitions */ /* Device DMA Channel Control Register Bit-field Definitions */
@ -732,7 +756,7 @@
#define UDDMA_STATUS_EOTSTA (1 << 4) /* Bit 4: End of USB Transfer Status */ #define UDDMA_STATUS_EOTSTA (1 << 4) /* Bit 4: End of USB Transfer Status */
#define UDDMA_STATUS_EOCHBUFFSTA (1 << 5) /* Bit 5: End of Channel Buffer Status */ #define UDDMA_STATUS_EOCHBUFFSTA (1 << 5) /* Bit 5: End of Channel Buffer Status */
#define UDDMA_STATUS_DESCLDSTA (1 << 6) /* Bit 6: Descriptor Loaded Status */ #define UDDMA_STATUS_DESCLDSTA (1 << 6) /* Bit 6: Descriptor Loaded Status */
#define UDDMA_STATUS_CHBYTECNT_SHIFT (16) /* Bits 16-31: Channel Byte Count */ #define UDDMA_STATUS_CHBYTECNT_SHIFT (16) /* Bits 16-31: Channel Byte Count */
#define UDDMA_STATUS_CHBYTECNT_MASK (0xffff << UDDMA_STATUS_CHBYTECNT_SHIFT) #define UDDMA_STATUS_CHBYTECNT_MASK (0xffff << UDDMA_STATUS_CHBYTECNT_SHIFT)
/* USB Host Registers Bit-field Definitions *********************************/ /* USB Host Registers Bit-field Definitions *********************************/
@ -744,10 +768,19 @@
#define USBB_UHCON_RESUME (1 << 10) /* Bit 10: Send USB Resume */ #define USBB_UHCON_RESUME (1 << 10) /* Bit 10: Send USB Resume */
/* Host Global Interrupt Register Bit-field Definitions */ /* Host Global Interrupt Register Bit-field Definitions */
/* Host Global Interrupt Clear Register Bit-field Definitions (Except as noted 1) */
/* Host Global Interrupt Set Register Bit-field Definitions (Except as noted 2) */ /* Host Global Interrupt Clear Register Bit-field Definitions
* (Except as noted 1)
*/
/* Host Global Interrupt Set Register Bit-field Definitions
* (Except as noted 2)
*/
/* Host Global Interrupt Enable Register Bit-field Definitions */ /* Host Global Interrupt Enable Register Bit-field Definitions */
/* Host Global Interrupt Enable Clear Register Bit-field Definitions */ /* Host Global Interrupt Enable Clear Register Bit-field Definitions */
/* Host Global Interrupt Enable Set Register Bit-field Definitions */ /* Host Global Interrupt Enable Set Register Bit-field Definitions */
#define USBB_UHINT_DCONNI (1 << 0) /* Bit 0: Device Connection Interrupt (1) */ #define USBB_UHINT_DCONNI (1 << 0) /* Bit 0: Device Connection Interrupt (1) */
@ -827,6 +860,7 @@
# define USBB_UPCFG_PBK_1 (0 << USBB_UPCFG_PBK_SHIFT) /* 1 (single-bank pipe) */ # define USBB_UPCFG_PBK_1 (0 << USBB_UPCFG_PBK_SHIFT) /* 1 (single-bank pipe) */
# define USBB_UPCFG_PBK_2 (1 << USBB_UPCFG_PBK_SHIFT) /* 2 (double-bank pipe) */ # define USBB_UPCFG_PBK_2 (1 << USBB_UPCFG_PBK_SHIFT) /* 2 (double-bank pipe) */
# define USBB_UPCFG_PBK_3 (2 << USBB_UPCFG_PBK_SHIFT) /* 3 (triple-bank pipe) */ # define USBB_UPCFG_PBK_3 (2 << USBB_UPCFG_PBK_SHIFT) /* 3 (triple-bank pipe) */
#define USBB_UPCFG_PSIZE_SHIFT (4) /* Bits 4-6: Pipe Size */ #define USBB_UPCFG_PSIZE_SHIFT (4) /* Bits 4-6: Pipe Size */
#define USBB_UPCFG_PSIZE_MASK (7 << USBB_UPCFG_PSIZE_SHIFT) #define USBB_UPCFG_PSIZE_MASK (7 << USBB_UPCFG_PSIZE_SHIFT)
# define USBB_UPCFG_PSIZE_8 (0 << USBB_UPCFG_PSIZE_SHIFT) /* 8 bytes */ # define USBB_UPCFG_PSIZE_8 (0 << USBB_UPCFG_PSIZE_SHIFT) /* 8 bytes */
@ -837,11 +871,13 @@
# define USBB_UPCFG_PSIZE_256 (5 << USBB_UPCFG_PSIZE_SHIFT) /* 256 bytes */ # define USBB_UPCFG_PSIZE_256 (5 << USBB_UPCFG_PSIZE_SHIFT) /* 256 bytes */
# define USBB_UPCFG_PSIZE_512 (6 << USBB_UPCFG_PSIZE_SHIFT) /* 512 bytes */ # define USBB_UPCFG_PSIZE_512 (6 << USBB_UPCFG_PSIZE_SHIFT) /* 512 bytes */
# define USBB_UPCFG_PSIZE_1024 (7 << USBB_UPCFG_PSIZE_SHIFT) /* 1024 bytes */ # define USBB_UPCFG_PSIZE_1024 (7 << USBB_UPCFG_PSIZE_SHIFT) /* 1024 bytes */
#define USBB_UPCFG_PTOKEN_SHIFT (8) /* Bits 8-9: Pipe Token */ #define USBB_UPCFG_PTOKEN_SHIFT (8) /* Bits 8-9: Pipe Token */
#define USBB_UPCFG_PTOKEN_MASK (3 << USBB_UPCFG_PTOKEN_SHIFT) #define USBB_UPCFG_PTOKEN_MASK (3 << USBB_UPCFG_PTOKEN_SHIFT)
# define USBB_UPCFG_PTOKEN_SETUP (0 << USBB_UPCFG_PTOKEN_SHIFT) /* SETUP */ # define USBB_UPCFG_PTOKEN_SETUP (0 << USBB_UPCFG_PTOKEN_SHIFT) /* SETUP */
# define USBB_UPCFG_PTOKEN_IN (1 << USBB_UPCFG_PTOKEN_SHIFT) /* IN */ # define USBB_UPCFG_PTOKEN_IN (1 << USBB_UPCFG_PTOKEN_SHIFT) /* IN */
# define USBB_UPCFG_PTOKEN_OUT (2 << USBB_UPCFG_PTOKEN_SHIFT) /* OUT */ # define USBB_UPCFG_PTOKEN_OUT (2 << USBB_UPCFG_PTOKEN_SHIFT) /* OUT */
#define USBB_UPCFG_AUTOSW (1 << 10) /* Bit 10: Automatic Switch */ #define USBB_UPCFG_AUTOSW (1 << 10) /* Bit 10: Automatic Switch */
#define USBB_UPCFG_PTYPE_SHIFT (11) /* Bits 11-12: Pipe Type */ #define USBB_UPCFG_PTYPE_SHIFT (11) /* Bits 11-12: Pipe Type */
#define USBB_UPCFG_PTYPE_MASK (3 << USBB_UPCFG_PTYPE_SHIFT) #define USBB_UPCFG_PTYPE_MASK (3 << USBB_UPCFG_PTYPE_SHIFT)
@ -849,13 +885,16 @@
# define USBB_UPCFG_PTYPE_ISOC (1 << USBB_UPCFG_PTYPE_SHIFT) /* Isochronous */ # define USBB_UPCFG_PTYPE_ISOC (1 << USBB_UPCFG_PTYPE_SHIFT) /* Isochronous */
# define USBB_UPCFG_PTYPE_BULK (2 << USBB_UPCFG_PTYPE_SHIFT) /* Bulk */ # define USBB_UPCFG_PTYPE_BULK (2 << USBB_UPCFG_PTYPE_SHIFT) /* Bulk */
# define USBB_UPCFG_PTYPE_INTR (3 << USBB_UPCFG_PTYPE_SHIFT) /* Interrupt */ # define USBB_UPCFG_PTYPE_INTR (3 << USBB_UPCFG_PTYPE_SHIFT) /* Interrupt */
#define USBB_UPCFG_PEPNUM_SHIFT (16) /* Bits 16-19: Pipe Endpoint Number */ #define USBB_UPCFG_PEPNUM_SHIFT (16) /* Bits 16-19: Pipe Endpoint Number */
#define USBB_UPCFG_PEPNUM_MASK (15 << USBB_UPCFG_PEPNUM_SHIFT) #define USBB_UPCFG_PEPNUM_MASK (15 << USBB_UPCFG_PEPNUM_SHIFT)
#define USBB_UPCFG_INTFRQ_SHIFT (24) /* Bits 24-31: Pipe Interrupt Request Frequency */ #define USBB_UPCFG_INTFRQ_SHIFT (24) /* Bits 24-31: Pipe Interrupt Request Frequency */
#define USBB_UPCFG_INTFRQ_MASK (0xff << USBB_UPCFG_INTFRQ_SHIFT) #define USBB_UPCFG_INTFRQ_MASK (0xff << USBB_UPCFG_INTFRQ_SHIFT)
/* Pipe Status Register Bit-field Definitions (common) */ /* Pipe Status Register Bit-field Definitions (common) */
/* Pipe Status Clear Register Bit-field Definitions (common) */ /* Pipe Status Clear Register Bit-field Definitions (common) */
/* Pipe Status Set Register Bit-field Definitions (common) */ /* Pipe Status Set Register Bit-field Definitions (common) */
#define USBB_UPSTA_RXINI (1 << 0) /* Bit 0: Received IN Data Interrupt */ #define USBB_UPSTA_RXINI (1 << 0) /* Bit 0: Received IN Data Interrupt */
@ -875,19 +914,22 @@
#define USBB_UPSTA_DTSEQ_MASK (3 << USBB_UPSTA_DTSEQ_SHIFT) #define USBB_UPSTA_DTSEQ_MASK (3 << USBB_UPSTA_DTSEQ_SHIFT)
# define USBB_UPSTA_DTSEQ_DATA0 (0 << USBB_UPSTA_DTSEQ_SHIFT) /* Data0 */ # define USBB_UPSTA_DTSEQ_DATA0 (0 << USBB_UPSTA_DTSEQ_SHIFT) /* Data0 */
# define USBB_UPSTA_DTSEQ_DATA1 (1 << USBB_UPSTA_DTSEQ_SHIFT) /* Data1 */ # define USBB_UPSTA_DTSEQ_DATA1 (1 << USBB_UPSTA_DTSEQ_SHIFT) /* Data1 */
#define USBB_UPSTA_NBUSYBK_SHIFT (12) /* Bits 12-13: Number of Busy Banks */ #define USBB_UPSTA_NBUSYBK_SHIFT (12) /* Bits 12-13: Number of Busy Banks */
#define USBB_UPSTA_NBUSYBK_MASK (3 << USBB_UPSTA_NBUSYBK_SHIFT) #define USBB_UPSTA_NBUSYBK_MASK (3 << USBB_UPSTA_NBUSYBK_SHIFT)
# define USBB_UPSTA_NBUSYBK_NONE (0 << USBB_UPSTA_NBUSYBK_SHIFT) /* 0 (all banks free) */ # define USBB_UPSTA_NBUSYBK_NONE (0 << USBB_UPSTA_NBUSYBK_SHIFT) /* 0 (all banks free) */
# define USBB_UPSTA_NBUSYBK_1BANK (1 << USBB_UPSTA_NBUSYBK_SHIFT) /* 1 */ # define USBB_UPSTA_NBUSYBK_1BANK (1 << USBB_UPSTA_NBUSYBK_SHIFT) /* 1 */
# define USBB_UPSTA_NBUSYBK_2BANKS (2 << USBB_UPSTA_NBUSYBK_SHIFT) /* 2 */ # define USBB_UPSTA_NBUSYBK_2BANKS (2 << USBB_UPSTA_NBUSYBK_SHIFT) /* 2 */
#define USBB_UPSTA_CURRBK_SHIFT (14) /* Bits 14-15: Current Bank */ #define USBB_UPSTA_CURRBK_SHIFT (14) /* Bits 14-15: Current Bank */
#define USBB_UPSTA_CURRBK_MASK (3 << USBB_UPSTA_CURRBK_SHIFT) #define USBB_UPSTA_CURRBK_MASK (3 << USBB_UPSTA_CURRBK_SHIFT)
# define USBB_UPSTA_CURRBK_BANK0 (0 << USBB_UPSTA_CURRBK_SHIFT) /* Bank0 */ # define USBB_UPSTA_CURRBK_BANK0 (0 << USBB_UPSTA_CURRBK_SHIFT) /* Bank0 */
# define USBB_UPSTA_CURRBK_BANK1 (1 << USBB_UPSTA_CURRBK_SHIFT) /* Bank1 */ # define USBB_UPSTA_CURRBK_BANK1 (1 << USBB_UPSTA_CURRBK_SHIFT) /* Bank1 */
# define USBB_UPSTA_CURRBK_BANK2 (2 << USBB_UPSTA_CURRBK_SHIFT) /* Bank2 */ # define USBB_UPSTA_CURRBK_BANK2 (2 << USBB_UPSTA_CURRBK_SHIFT) /* Bank2 */
#define USBB_UPSTA_RWALL (1 << 16) /* Bit 16: Read/Write Allowed */ #define USBB_UPSTA_RWALL (1 << 16) /* Bit 16: Read/Write Allowed */
#define USBB_UPSTA_CFGOK (1 << 18) /* Bit 18: Configuration OK Status */ #define USBB_UPSTA_CFGOK (1 << 18) /* Bit 18: Configuration OK Status */
#define USBB_UPSTA_PBYCT_SHIFT (20) /* Bits 20-30: Pipe Byte Count */ #define USBB_UPSTA_PBYCT_SHIFT (20) /* Bits 20-30: Pipe Byte Count */
#define USBB_UPSTA_PBYCT_MASK (0x7ff << USBB_UPSTA_BYCT_SHIFT) #define USBB_UPSTA_PBYCT_MASK (0x7ff << USBB_UPSTA_BYCT_SHIFT)
/* Pipe Status Set Register Bit-field Definitions (only in UPSTASET) */ /* Pipe Status Set Register Bit-field Definitions (only in UPSTASET) */
@ -895,7 +937,9 @@
#define USBB_UPSTASET_NBUSYBKS (1 << 12) /* Bit 12 */ #define USBB_UPSTASET_NBUSYBKS (1 << 12) /* Bit 12 */
/* Pipe Control Register Bit-field Definitions */ /* Pipe Control Register Bit-field Definitions */
/* Pipe Control Clear Register Bit-field Definitions (except as noted 1) */ /* Pipe Control Clear Register Bit-field Definitions (except as noted 1) */
/* Pipe Control Set Register Bit-field Definitions (except as noted 2) */ /* Pipe Control Set Register Bit-field Definitions (except as noted 2) */
#define USBB_UPCON_RXINE (1 << 0) /* Bit 0: Received IN Data Interrupt Enable */ #define USBB_UPCON_RXINE (1 << 0) /* Bit 0: Received IN Data Interrupt Enable */
@ -935,6 +979,7 @@
#define UHDMA_NEXTDESC_MASK (0xfffffff0) #define UHDMA_NEXTDESC_MASK (0xfffffff0)
/* Host DMA Channel HSB Address Register Bit-field Definitions */ /* Host DMA Channel HSB Address Register Bit-field Definitions */
/* This register holds a 32-bit address with internal bit fields */ /* This register holds a 32-bit address with internal bit fields */
/* Host DMA Channel Control Register Bit-field Definitions */ /* Host DMA Channel Control Register Bit-field Definitions */
@ -957,7 +1002,7 @@
#define UHDMA_STATUS_EOTSTA (1 << 4) /* Bit 4: End of USB Transfer Status */ #define UHDMA_STATUS_EOTSTA (1 << 4) /* Bit 4: End of USB Transfer Status */
#define UHDMA_STATUS_EOCHBUFFSTA (1 << 5) /* Bit 5: End of Channel Buffer Status */ #define UHDMA_STATUS_EOCHBUFFSTA (1 << 5) /* Bit 5: End of Channel Buffer Status */
#define UHDMA_STATUS_DESCLDSTA (1 << 6) /* Bit 6: Descriptor Loaded Status */ #define UHDMA_STATUS_DESCLDSTA (1 << 6) /* Bit 6: Descriptor Loaded Status */
#define UHDMA_STATUS_CHBYTECNT_SHIFT (16) /* Bits 16-31: Channel Byte Count */ #define UHDMA_STATUS_CHBYTECNT_SHIFT (16) /* Bits 16-31: Channel Byte Count */
#define UHDMA_STATUS_CHBYTECNT_MASK (0xffff << UHDMA_STATUS_CHBYTECNT_SHIFT) #define UHDMA_STATUS_CHBYTECNT_MASK (0xffff << UHDMA_STATUS_CHBYTECNT_SHIFT)
/* USB General Registers Bit-field Definitions ******************************/ /* USB General Registers Bit-field Definitions ******************************/
@ -984,7 +1029,9 @@
#define USBB_USBCON_UIMOD (1 << 25) /* Bit 25: USBB Mode */ #define USBB_USBCON_UIMOD (1 << 25) /* Bit 25: USBB Mode */
/* General Status Register Bit-field Definitions */ /* General Status Register Bit-field Definitions */
/* General Status Clear Register Bit-field Definitions */ /* General Status Clear Register Bit-field Definitions */
/* General Status Set Register Bit-field Definitions */ /* General Status Set Register Bit-field Definitions */
#define USBB_USBSTA_IDTI (1 << 0) /* Bit 0: ID Transition Interrupt */ #define USBB_USBSTA_IDTI (1 << 0) /* Bit 0: ID Transition Interrupt */
@ -1013,12 +1060,14 @@
#define USBB_UFEAT_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Maximal Number of Pipes/Endpoints */ #define USBB_UFEAT_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Maximal Number of Pipes/Endpoints */
#define USBB_UFEAT_EPTNBRMAX_MASK (15 << USBB_UFEAT_EPTNBRMAX_SHIFT) #define USBB_UFEAT_EPTNBRMAX_MASK (15 << USBB_UFEAT_EPTNBRMAX_SHIFT)
# define USBB_UFEAT_EPTNBRMAX_16 (0 << USBB_UFEAT_EPTNBRMAX_SHIFT) /* 16 is a special case */ # define USBB_UFEAT_EPTNBRMAX_16 (0 << USBB_UFEAT_EPTNBRMAX_SHIFT) /* 16 is a special case */
#define USBB_UFEAT_DMACHANNBR_SHIFT (4) /* Bits 4-6: Number of DMA Channels */ #define USBB_UFEAT_DMACHANNBR_SHIFT (4) /* Bits 4-6: Number of DMA Channels */
#define USBB_UFEAT_DMACHANNBR_MASK (7 << USBB_UFEAT_DMACHANNBR_SHIFT) #define USBB_UFEAT_DMACHANNBR_MASK (7 << USBB_UFEAT_DMACHANNBR_SHIFT)
#define USBB_UFEAT_DMABUFFERSZ (1 << 7) /* Bit 7: DMA Buffer Size */ #define USBB_UFEAT_DMABUFFERSZ (1 << 7) /* Bit 7: DMA Buffer Size */
#define USBB_UFEAT_DMAWDDEPTH_SHIFT (8) /* Bits 8-11: DMA FIFO Depth in Words */ #define USBB_UFEAT_DMAWDDEPTH_SHIFT (8) /* Bits 8-11: DMA FIFO Depth in Words */
#define USBB_UFEAT_DMAWDDEPTH_MASK (15 << USBB_UFEAT_DMAWDDEPTH_SHIFT) #define USBB_UFEAT_DMAWDDEPTH_MASK (15 << USBB_UFEAT_DMAWDDEPTH_SHIFT)
# define USBB_UFEAT_DMAWDDEPTH_16 (0 << USBB_UFEAT_DMAWDDEPTH_SHIFT) /* 16 is a special case */ # define USBB_UFEAT_DMAWDDEPTH_16 (0 << USBB_UFEAT_DMAWDDEPTH_SHIFT) /* 16 is a special case */
#define USBB_UFEAT_FIFOMAXSZ_SHIFT (12) /* Bits 12-14: Maximal FIFO Size */ #define USBB_UFEAT_FIFOMAXSZ_SHIFT (12) /* Bits 12-14: Maximal FIFO Size */
#define USBB_UFEAT_FIFOMAXSZ_MASK (7 << USBB_UFEAT_FIFOMAXSZ_SHIFT) #define USBB_UFEAT_FIFOMAXSZ_MASK (7 << USBB_UFEAT_FIFOMAXSZ_SHIFT)
# define USBB_UFEAT_FIFOMAXSZ_LT256 (0 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* < 256 bytes */ # define USBB_UFEAT_FIFOMAXSZ_LT256 (0 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* < 256 bytes */
@ -1029,10 +1078,13 @@
# define USBB_UFEAT_FIFOMAXSZ_LT8K (5 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* < 8192 bytes */ # define USBB_UFEAT_FIFOMAXSZ_LT8K (5 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* < 8192 bytes */
# define USBB_UFEAT_FIFOMAXSZ_LT16K (6 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* < 16384 bytes */ # define USBB_UFEAT_FIFOMAXSZ_LT16K (6 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* < 16384 bytes */
# define USBB_UFEAT_FIFOMAXSZ_GE16K (7 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* >= 16384 bytes */ # define USBB_UFEAT_FIFOMAXSZ_GE16K (7 << USBB_UFEAT_FIFOMAXSZ_SHIFT) /* >= 16384 bytes */
#define USBB_UFEAT_BWRDPRAM (1 << 15) /* Bit 15: DPRAM Byte-Write Capability */ #define USBB_UFEAT_BWRDPRAM (1 << 15) /* Bit 15: DPRAM Byte-Write Capability */
/* IP PB Address Size Register Bit-field Definitions */ /* IP PB Address Size Register Bit-field Definitions */
/* IP Name Register 1 Bit-field Definitions */ /* IP Name Register 1 Bit-field Definitions */
/* IP Name Register 2 Bit-field Definitions */ /* IP Name Register 2 Bit-field Definitions */
/* These registers contain a 32-value and, hence, have no bit fields */ /* These registers contain a 32-value and, hence, have no bit fields */
@ -1057,7 +1109,7 @@
# define USBB_USBFSM_B_HOST (14) # define USBB_USBFSM_B_HOST (14)
# define USBB_USBFSM_B_SRPINIT (15) # define USBB_USBFSM_B_SRPINIT (15)
/* USB HSB Memory Map ***************************************************************/ /* USB HSB Memory Map *******************************************************/
#define USB_FIFO0_DATA_OFFSET 0x00000 /* Pipe/Endpoint 0 FIFO Data Register */ #define USB_FIFO0_DATA_OFFSET 0x00000 /* Pipe/Endpoint 0 FIFO Data Register */
#define USB_FIFO1_DATA_OFFSET 0x10000 /* Pipe/Endpoint 1 FIFO Data Register */ #define USB_FIFO1_DATA_OFFSET 0x10000 /* Pipe/Endpoint 1 FIFO Data Register */
@ -1067,16 +1119,16 @@
#define USB_FIFO5_DATA_OFFSET 0x50000 /* Pipe/Endpoint 5 FIFO Data Register */ #define USB_FIFO5_DATA_OFFSET 0x50000 /* Pipe/Endpoint 5 FIFO Data Register */
#define USB_FIFO6_DATA_OFFSET 0x60000 /* Pipe/Endpoint 6 FIFO Data Register */ #define USB_FIFO6_DATA_OFFSET 0x60000 /* Pipe/Endpoint 6 FIFO Data Register */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_USBB_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_USBB_H */

38
arch/avr/src/at32uc3/at32uc3_wdt.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3_wdt.h * arch/avr/src/at32uc3/at32uc3_wdt.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,32 +16,32 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_WDT_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3_WDT_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3_WDT_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3_WDT_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Register offsets *****************************************************************/ /* Register offsets *********************************************************/
#define AVR32_WDT_CTRL_OFFSET 0x00 /* Control Register */ #define AVR32_WDT_CTRL_OFFSET 0x00 /* Control Register */
#define AVR32_WDT_CLR_OFFSET 0x04 /* Clear Register */ #define AVR32_WDT_CLR_OFFSET 0x04 /* Clear Register */
/* Register Addresses ***************************************************************/ /* Register Addresses *******************************************************/
#define AVR32_WDT_CTRL (AVR32_WDT_BASE+AVR32_WDT_CTRL_OFFSET) #define AVR32_WDT_CTRL (AVR32_WDT_BASE+AVR32_WDT_CTRL_OFFSET)
#define AVR32_WDT_CLR (AVR32_WDT_BASE+AVR32_WDT_CLR_OFFSET) #define AVR32_WDT_CLR (AVR32_WDT_BASE+AVR32_WDT_CLR_OFFSET)
/* Register Bit-field Definitions ***************************************************/ /* Register Bit-field Definitions *******************************************/
/* Control Register Bit-field Definitions */ /* Control Register Bit-field Definitions */
@ -51,21 +51,21 @@
#define WDT_CTRL_KEY_SHIFT (24) /* Bits 24-31: Write protection key */ #define WDT_CTRL_KEY_SHIFT (24) /* Bits 24-31: Write protection key */
#define WDT_CTRL_KEY_MASK (0xff << WDT_CTRL_KEY_SHIFT) #define WDT_CTRL_KEY_MASK (0xff << WDT_CTRL_KEY_SHIFT)
/* Clear Register Bit-field Definitions. These registers have no bit fields: "Writing /* Clear Register Bit-field Definitions. These registers have no bit fields:
* periodically any value to this field when the WDT is enabled, within the watchdog * "Writing periodically any value to this field when the WDT is enabled,
* time-out period, will prevent a watchdog reset." * within the watchdog time-out period, will prevent a watchdog reset."
*/ */
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_WDT_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_WDT_H */

2
arch/avr/src/at32uc3/at32uc3a_pinmux.h
View File

@ -42,7 +42,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PINMUX_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3_PINMUX_H */

34
arch/avr/src/at32uc3/at32uc3b_pinmux.h
View File

@ -1,4 +1,5 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/at32uc3b_pinmux.h * arch/avr/src/at32uc3/at32uc3b_pinmux.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,27 +17,28 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PINMUX_H #ifndef __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PINMUX_H
#define __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PINMUX_H #define __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PINMUX_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* NOTES: /* NOTES:
* 1. No external pins for PA28-PA31, PB0-PB11 on 48-pin packages (UC3B1). * 1. No external pins for PA28-PA31, PB0-PB11 on 48-pin packages (UC3B1).
* 2. Function D is available only on UC3Bx12. * 2. Function D is available only on UC3Bx12.
* 3. In the cases where there are multiple alternatives (such as PINMUX_USART0_RXD_1 * 3. In the cases where there are multiple alternatives (such as
* and PINMUX_USART0_RXD_2) the correct multiplexing must be selected in the board.h * PINMUX_USART0_RXD_1 and PINMUX_USART0_RXD_2) the correct multiplexing
* file (by defining PINMUX_USART0_RXD to be INMUX_USART0_RXD_1, for example). * must be selected in the board.h file (by defining PINMUX_USART0_RXD to
* be INMUX_USART0_RXD_1, for example).
*/ */
#define PINMUX_GPIO0 (GPIO_ENABLE | GPIO_PORTA | 0) #define PINMUX_GPIO0 (GPIO_ENABLE | GPIO_PORTA | 0)
@ -232,16 +234,16 @@
#define PINMUX_TC_B2_2 (GPIO_PERIPH | GPIO_FUNCB | GPIO_PORTB | 11) #define PINMUX_TC_B2_2 (GPIO_PERIPH | GPIO_FUNCB | GPIO_PORTB | 11)
#define PINMUX_USART0_TXD_2 (GPIO_PERIPH | GPIO_FUNCC | GPIO_PORTB | 11) #define PINMUX_USART0_TXD_2 (GPIO_PERIPH | GPIO_FUNCC | GPIO_PORTB | 11)
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PINMUX_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_AT32UC3B_PINMUX_H */

31
arch/avr/src/at32uc3/chip.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at32uc3/chip.h * arch/avr/src/at32uc3/chip.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,25 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_AT32UC3_CHIP_H #ifndef __ARCH_AVR_SRC_AT32UC3_CHIP_H
#define __ARCH_AVR_SRC_AT32UC3_CHIP_H #define __ARCH_AVR_SRC_AT32UC3_CHIP_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* Get customizations for each supported chip */ /* Get customizations for each supported chip */
/* UC3 A0/A1 Series */ /* UC3 A0/A1 Series */
/* UC3 A2/A3 Series */ /* UC3 A2/A3 Series */
/* UC3 B0 (64-pin) / B1 (48-pin, no USB host) Series */ /* UC3 B0 (64-pin) / B1 (48-pin, no USB host) Series */
@ -186,22 +187,22 @@
# error "Unsupported AVR32 chip" # error "Unsupported AVR32 chip"
#endif #endif
/* Include only the memory map. Other chip hardware files should then include this /* Include only the memory map. Other chip hardware files should then
* file for the proper setup * include this file for the proper setup
*/ */
#include "at32uc3_memorymap.h" #include "at32uc3_memorymap.h"
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_AT32UC3_CHIP_H */ #endif /* __ARCH_AVR_SRC_AT32UC3_CHIP_H */

29
arch/avr/src/at90usb/at90usb_config.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/at90usb/at90usb_config.h * arch/avr/src/at90usb/at90usb_config.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,22 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H #ifndef __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H
#define __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H #define __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* USARTs ***************************************************************************/
/* USARTs *******************************************************************/
#undef HAVE_USART_DEVICE #undef HAVE_USART_DEVICE
#if defined(CONFIG_AVR_USART1) #if defined(CONFIG_AVR_USART1)
@ -79,16 +80,16 @@
# define USE_SERIALDRIVER 1 # define USE_SERIALDRIVER 1
#endif #endif
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H */ #endif /* __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H */

17
arch/avr/src/at90usb/at90usb_lowconsole.c
View File

@ -49,8 +49,8 @@
#define AVR_DBLSPEED_UBRR1 \ #define AVR_DBLSPEED_UBRR1 \
((((BOARD_CPU_CLOCK / 8) + (CONFIG_USART1_BAUD / 2)) / (CONFIG_USART1_BAUD)) - 1) ((((BOARD_CPU_CLOCK / 8) + (CONFIG_USART1_BAUD / 2)) / (CONFIG_USART1_BAUD)) - 1)
/* Select normal or double speed baud settings. This is a trade-off between the /* Select normal or double speed baud settings. This is a trade-off between
* sampling rate and the accuracy of the divisor for high baud rates. * the sampling rate and the accuracy of the divisor for high baud rates.
* *
* As examples, consider: * As examples, consider:
* *
@ -216,10 +216,11 @@ void usart1_configure(void)
/* Pin Configuration: None necessary, Port D bits 2&3 are automatically /* Pin Configuration: None necessary, Port D bits 2&3 are automatically
* configured: * configured:
* *
* Port D, Bit 2: RXD1, Receive Data (Data input pin for the USART1). When * Port D, Bit 2: RXD1, Receive Data (Data input pin for the USART1).
* the USART1 receiver is enabled this pin is configured as an input * When the USART1 receiver is enabled this pin is configured as an
* regardless of the value of DDD2. When the USART forces this pin to * input regardless of the value of DDD2. When the USART forces this
* be an input, the pull-up can still be controlled by the PORTD2 bit. * pin to be an input, the pull-up can still be controlled by the
* PORTD2 bit.
* Port D, Bit 3: TXD1, Transmit Data (Data output pin for the USART1). * Port D, Bit 3: TXD1, Transmit Data (Data output pin for the USART1).
* When the USART1 Transmitter is enabled, this pin is configured as * When the USART1 Transmitter is enabled, this pin is configured as
* an output regardless of the value of DDD3. * an output regardless of the value of DDD3.
@ -239,8 +240,8 @@ void usart1_configure(void)
* *
* Description: * Description:
* Initialize a console for debug output. This function is called very * Initialize a console for debug output. This function is called very
* early in the initialization sequence to configure the serial console uart * early in the initialization sequence to configure the serial console
* (only). * uart (only).
* *
****************************************************************************/ ****************************************************************************/

2
arch/avr/src/at90usb/at90usb_memorymap.h
View File

@ -40,7 +40,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_ATMEGA_ATMEGA_MEMORYMAP_H */ #endif /* __ARCH_AVR_SRC_ATMEGA_ATMEGA_MEMORYMAP_H */

47
arch/avr/src/at90usb/at90usb_serial.c
View File

@ -126,7 +126,7 @@ static uart_dev_t g_usart1port =
{ {
.size = CONFIG_USART1_TXBUFSIZE, .size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer, .buffer = g_usart1txbuffer,
}, },
.ops = &g_uart1_ops, .ops = &g_uart1_ops,
}; };
@ -204,14 +204,15 @@ static void usart1_shutdown(struct uart_dev_s *dev)
* Name: usart1_attach * Name: usart1_attach
* *
* Description: * Description:
* Configure the USART to operation in interrupt driven mode. This method is * Configure the USART to operation in interrupt driven mode. This method
* called when the serial port is opened. Normally, this is just after the * is called when the serial port is opened. Normally, this is just after
* the setup() method is called, however, the serial console may operate in * the the setup() method is called, however, the serial console may
* a non-interrupt driven mode during the boot phase. * operate in a non-interrupt driven mode during the boot phase.
* *
* RX and TX interrupts are not enabled when by the attach method (unless the * RX and TX interrupts are not enabled when by the attach method (unless
* hardware supports multiple levels of interrupt enabling). The RX and TX * the hardware supports multiple levels of interrupt enabling). The RX
* interrupts are not enabled until the txint() and rxint() methods are called. * and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
* *
****************************************************************************/ ****************************************************************************/
@ -224,14 +225,16 @@ static int usart1_attach(struct uart_dev_s *dev)
* TX: USART Transmit Complete. Set when the entire frame in the Transmit * TX: USART Transmit Complete. Set when the entire frame in the Transmit
* Shift Register has been shifted out and there are no new data * Shift Register has been shifted out and there are no new data
* currently present in the transmit buffer. * currently present in the transmit buffer.
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready * DRE: USART Data Register Empty. Indicates if the transmit buffer is
* to receive new data: The buffer is empty, and therefore ready to be * ready to receive new data: The buffer is empty, and therefore ready
* written. * to be written.
*/ */
irq_attach(AT90USB_IRQ_U1RX, usart1_rxinterrupt, NULL); irq_attach(AT90USB_IRQ_U1RX, usart1_rxinterrupt, NULL);
irq_attach(AT90USB_IRQ_U1DRE, usart1_txinterrupt, NULL); irq_attach(AT90USB_IRQ_U1DRE, usart1_txinterrupt, NULL);
//(void)irq_attach(AT90USB_IRQ_U1TX, usart1_txinterrupt, NULL);
/* (void)irq_attach(AT90USB_IRQ_U1TX, usart1_txinterrupt, NULL); */
return OK; return OK;
} }
@ -240,8 +243,8 @@ static int usart1_attach(struct uart_dev_s *dev)
* *
* Description: * Description:
* Detach USART interrupts. This method is called when the serial port is * Detach USART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception * closed normally just before the shutdown method is called. The
* is the serial console which is never shutdown. * exception is the serial console which is never shutdown.
* *
****************************************************************************/ ****************************************************************************/
@ -255,7 +258,8 @@ static void usart1_detach(struct uart_dev_s *dev)
irq_detach(AT90USB_IRQ_U1RX); irq_detach(AT90USB_IRQ_U1RX);
irq_detach(AT90USB_IRQ_U1DRE); irq_detach(AT90USB_IRQ_U1DRE);
//(void)irq_detach(AT90USB_IRQ_U1TX);
/* (void)irq_detach(AT90USB_IRQ_U1TX); */
} }
/**************************************************************************** /****************************************************************************
@ -353,7 +357,9 @@ static int usart1_ioctl(struct file *filep, int cmd, unsigned long arg)
static int usart1_receive(struct uart_dev_s *dev, FAR unsigned int *status) static int usart1_receive(struct uart_dev_s *dev, FAR unsigned int *status)
{ {
/* Return status information (error bits will be cleared after reading UDR1) */ /* Return status information
* (error bits will be cleared after reading UDR1)
*/
if (status) if (status)
{ {
@ -436,9 +442,9 @@ static void usart1_txint(struct uart_dev_s *dev, bool enable)
* TX: USART Transmit Complete. Set when the entire frame in the Transmit * TX: USART Transmit Complete. Set when the entire frame in the Transmit
* Shift Register has been shifted out and there are no new data * Shift Register has been shifted out and there are no new data
* currently present in the transmit buffer. * currently present in the transmit buffer.
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready * DRE: USART Data Register Empty. Indicates if the transmit buffer is
* to receive new data: The buffer is empty, and therefore ready to be * ready to receive new data: The buffer is empty, and therefore ready
* written. * to be written.
*/ */
flags = enter_critical_section(); flags = enter_critical_section();
@ -448,7 +454,8 @@ static void usart1_txint(struct uart_dev_s *dev, bool enable)
#ifndef CONFIG_SUPPRESS_SERIAL_INTS #ifndef CONFIG_SUPPRESS_SERIAL_INTS
UCSR1B |= (1 << UDRIE1); UCSR1B |= (1 << UDRIE1);
// UCSR1B |= (1 << TXCIE1);
/* UCSR1B |= (1 << TXCIE1); */
/* Fake a TX interrupt here by just calling uart_xmitchars() with /* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse). * interrupts disabled (note this may recurse).

298
arch/avr/src/at90usb/at90usb_usbdev.c
View File

@ -52,9 +52,11 @@
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* Configuration ***************************************************************/ /* Configuration ************************************************************/
/* PLL Settings are based on F_CPU frequency which is defined in the board.h file */ /* PLL Settings are based on F_CPU frequency which is defined in the board.h
* file
*/
#if (BOARD_CPU_CLOCK == 8000000) #if (BOARD_CPU_CLOCK == 8000000)
# define USB_PLL_PSC ((1 << PLLP1) | (1 << PLLP0)) # define USB_PLL_PSC ((1 << PLLP1) | (1 << PLLP0))
@ -68,7 +70,7 @@
# error "Unsupported CPU clock" # error "Unsupported CPU clock"
#endif #endif
/* Debug ***********************************************************************/ /* Debug ********************************************************************/
/* Trace error codes */ /* Trace error codes */
@ -130,9 +132,9 @@
#define AVR_TRACEINTID_SETFEATURE 0x0015 #define AVR_TRACEINTID_SETFEATURE 0x0015
#define AVR_TRACEINTID_SYNCHFRAME 0x0016 #define AVR_TRACEINTID_SYNCHFRAME 0x0016
/* Hardware interface **********************************************************/ /* Hardware interface *******************************************************/
/* Endpoints ******************************************************************/ /* Endpoints ****************************************************************/
/* Number of endpoints */ /* Number of endpoints */
@ -140,7 +142,7 @@
/* Endpoint 0 is special... */ /* Endpoint 0 is special... */
#define AVR_EP0 (0) #define AVR_EP0 (0)
#define AVR_CTRLEP_SIZE (8) #define AVR_CTRLEP_SIZE (8)
/* Bit encoded ep0-6 */ /* Bit encoded ep0-6 */
@ -177,7 +179,7 @@
#define AVR_TIMEOUT_SHORT (32) #define AVR_TIMEOUT_SHORT (32)
#define AVR_TIMEOUT_NONE (0) #define AVR_TIMEOUT_NONE (0)
/* Request queue operations ****************************************************/ /* Request queue operations *************************************************/
#define avr_rqempty(ep) ((ep)->head == NULL) #define avr_rqempty(ep) ((ep)->head == NULL)
#define avr_rqpeek(ep) ((ep)->head) #define avr_rqpeek(ep) ((ep)->head)
@ -254,13 +256,13 @@ struct avr_usbdev_s
* Private Function Prototypes * Private Function Prototypes
****************************************************************************/ ****************************************************************************/
/* Request queue operations ****************************************************/ /* Request queue operations *************************************************/
static FAR struct avr_req_s *avr_rqdequeue(FAR struct avr_ep_s *privep); static FAR struct avr_req_s *avr_rqdequeue(FAR struct avr_ep_s *privep);
static inline void avr_rqenqueue(FAR struct avr_ep_s *privep, static inline void avr_rqenqueue(FAR struct avr_ep_s *privep,
FAR struct avr_req_s *req); FAR struct avr_req_s *req);
/* Low level data transfers and request operations *****************************/ /* Low level data transfers and request operations **************************/
static void avr_txready(void); static void avr_txready(void);
static int avr_fifoready(int timeout); static int avr_fifoready(int timeout);
@ -271,12 +273,13 @@ static inline int avr_ep_nrecv(FAR struct avr_ep_s *privep,
FAR struct usbdev_req_s *req); FAR struct usbdev_req_s *req);
static int avr_ep_in_queue(FAR struct avr_ep_s *privep); static int avr_ep_in_queue(FAR struct avr_ep_s *privep);
static int avr_ep_out_queue(FAR struct avr_ep_s *privep); static int avr_ep_out_queue(FAR struct avr_ep_s *privep);
static void avr_reqcomplete(FAR struct avr_ep_s *privep, FAR struct avr_req_s *privreq, static void avr_reqcomplete(FAR struct avr_ep_s *privep,
FAR struct avr_req_s *privreq,
int result); int result);
static void avr_cancelrequests(FAR struct avr_ep_s *privep, int status); static void avr_cancelrequests(FAR struct avr_ep_s *privep, int status);
static void avr_cancelall(int status); static void avr_cancelall(int status);
/* Endpoint interrupt handling *************************************************/ /* Endpoint interrupt handling **********************************************/
static struct avr_ep_s *avr_epfindbyaddr(uint8_t epno); static struct avr_ep_s *avr_epfindbyaddr(uint8_t epno);
static void avr_dispatchrequest(FAR const struct usb_ctrlreq_s *ctrl); static void avr_dispatchrequest(FAR const struct usb_ctrlreq_s *ctrl);
@ -285,7 +288,7 @@ static void avr_setaddress(uint8_t address);
static void avr_ep0setup(void); static void avr_ep0setup(void);
static int avr_epinterrupt(int irq, FAR void *context, FAR void *arg); static int avr_epinterrupt(int irq, FAR void *context, FAR void *arg);
/* General interrupt handling **************************************************/ /* General interrupt handling ***********************************************/
static void avr_epreset(FAR struct avr_ep_s *privep, int status); static void avr_epreset(FAR struct avr_ep_s *privep, int status);
static void avr_usbreset(void); static void avr_usbreset(void);
@ -295,7 +298,7 @@ static void avr_genwakeup(void);
static inline void avr_geneor(void); static inline void avr_geneor(void);
static int avr_geninterrupt(int irq, FAR void *context, FAR void *arg); static int avr_geninterrupt(int irq, FAR void *context, FAR void *arg);
/* USB device controller operations ********************************************/ /* USB device controller operations *****************************************/
static int avr_epconfigure(FAR struct usbdev_ep_s *ep, static int avr_epconfigure(FAR struct usbdev_ep_s *ep,
const struct usb_epdesc_s *desc, bool last); const struct usb_epdesc_s *desc, bool last);
@ -307,8 +310,10 @@ static void avr_epfreereq(FAR struct usbdev_ep_s *ep,
static void *avr_epallocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes); static void *avr_epallocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes);
static void avr_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf); static void avr_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf);
#endif #endif
static int avr_epsubmit(FAR struct usbdev_ep_s *ep, struct usbdev_req_s *req); static int avr_epsubmit(FAR struct usbdev_ep_s *ep,
static int avr_epcancel(FAR struct usbdev_ep_s *ep, struct usbdev_req_s *req); struct usbdev_req_s *req);
static int avr_epcancel(FAR struct usbdev_ep_s *ep,
struct usbdev_req_s *req);
static int avr_epstall(FAR struct usbdev_ep_s *ep, bool resume); static int avr_epstall(FAR struct usbdev_ep_s *ep, bool resume);
static FAR struct usbdev_ep_s *avr_allocep(FAR struct usbdev_s *dev, static FAR struct usbdev_ep_s *avr_allocep(FAR struct usbdev_s *dev,
@ -441,12 +446,12 @@ static int avr_fifoready(int timeout)
for (; ; ) for (; ; )
{ {
/* Check if the FIFO is ready by testing RWAL (read/write allowed). The /* Check if the FIFO is ready by testing RWAL (read/write allowed).
* meaning of this bigtdepends on the direction of the endpoint: For an * The meaning of this bigtdepends on the direction of the endpoint:
* OUT endpoint, the RWAL bit is set if the firmware can read data from * For an OUT endpoint, the RWAL bit is set if the firmware can read
* the bank, and cleared by hardware when the bank is empty; For an IN * data from the bank, and cleared by hardware when the bank is empty;
* endpoint, the RWAL bit is set if the firmware can write data to the * For an IN endpoint, the RWAL bit is set if the firmware can write
* bank, and cleared by hardware when the bank is full. * data to the bank, and cleared by hardware when the bank is full.
*/ */
if ((UEINTX & (1 << RWAL)) != 0) if ((UEINTX & (1 << RWAL)) != 0)
@ -510,7 +515,8 @@ static void avr_ep0send(FAR const uint8_t *buffer, uint16_t buflen)
while (buflen) while (buflen)
{ {
/* Verify that RXOUTI is clear. RXOUTI is set when a new OUT data is /* Verify that RXOUTI is clear. RXOUTI is set when a new OUT data is
* received. In this case, we have not option but to abort the transfer. * received. In this case, we have not option but to abort the
* transfer.
*/ */
regval = UEINTX; regval = UEINTX;
@ -520,7 +526,9 @@ static void avr_ep0send(FAR const uint8_t *buffer, uint16_t buflen)
return; return;
} }
/* Okay... wait for the selected endpoint to be ready for an TX transfer */ /* Okay...
* wait for the selected endpoint to be ready for an TX transfer
*/
avr_txready(); avr_txready();
@ -555,9 +563,9 @@ static void avr_ep0send(FAR const uint8_t *buffer, uint16_t buflen)
buflen--; buflen--;
} }
/* Clearing FIFOCON frees the current bank and switches to the following /* Clearing FIFOCON frees the current bank and switches to the
* bank. TXINI must be cleared to acknowledge the interrupt. TXINI must * following bank. TXINI must be cleared to acknowledge the interrupt.
* always be cleared BEFORE clearing FIFOCON. * TXINI must always be cleared BEFORE clearing FIFOCON.
*/ */
regval = UEINTX; regval = UEINTX;
@ -643,7 +651,8 @@ static inline int avr_ep_nsend(FAR struct avr_ep_s *privep,
UEINT &= ~(1 << privep->ep.eplog); UEINT &= ~(1 << privep->ep.eplog);
/* Clear TXINI and send what is in the transmit FIFO (could be a zero /* Clear TXINI and send what is in the transmit FIFO (could be a zero
* length packet). TXINI must always be cleared BEFORE clearing FIFOCON. * length packet). TXINI must always be cleared BEFORE clearing
* FIFOCON.
*/ */
regval = UEINTX; regval = UEINTX;
@ -663,8 +672,8 @@ static inline int avr_ep_nsend(FAR struct avr_ep_s *privep,
/* Check if we need to send a zero length packet (ZLP); We need to send /* Check if we need to send a zero length packet (ZLP); We need to send
* a ZLP if the last packet sent was exactly equal to the packet length * a ZLP if the last packet sent was exactly equal to the packet length
* AND if the endpoint is configuration to send ZLPs. However, in dual * AND if the endpoint is configuration to send ZLPs. However, in dual
* buffer mode, we may have actually just sent two packets so the actual * buffer mode, we may have actually just sent two packets so the
* check is for a non-zero, transfer of a multiple of the packet * actual check is for a non-zero, transfer of a multiple of the packet
*/ */
if (buflen > 0) if (buflen > 0)
@ -675,8 +684,8 @@ static inline int avr_ep_nsend(FAR struct avr_ep_s *privep,
} }
else if (zlp) else if (zlp)
{ {
/* All of the data has been sent. A ZLP might be needed if the last /* All of the data has been sent. A ZLP might be needed if the
* transfer was an exact multiple of the packet size. * last transfer was an exact multiple of the packet size.
*/ */
if (len && (len & pktmask) == 0) if (len && (len & pktmask) == 0)
@ -704,10 +713,10 @@ static inline int avr_ep_nsend(FAR struct avr_ep_s *privep,
} }
/* RWAL will be de-asserted when there is no more space in the transmit /* RWAL will be de-asserted when there is no more space in the transmit
* FIFO. We care only if we have more data (or a zero-length-packet) to * FIFO. We care only if we have more data (or a zero-length-packet)
* send. Try a short inline wait to see if the FIFO becomes write ready. * to send. Try a short inline wait to see if the FIFO becomes write
* This saves handling an interrupt most of the time (really depends on * ready. This saves handling an interrupt most of the time (really
* how fast the host takes the data from the transmit FIFO). * depends on how fast the host takes the data from the transmit FIFO).
*/ */
if (more && (ret = avr_fifoready(AVR_TIMEOUT_SHORT))) if (more && (ret = avr_fifoready(AVR_TIMEOUT_SHORT)))
@ -775,8 +784,8 @@ static inline int avr_ep_nrecv(FAR struct avr_ep_s *privep,
if (((UEINTX & (1 << RWAL)) == 0)) if (((UEINTX & (1 << RWAL)) == 0))
{ {
/* The FIFO is empty.. Acknowledge receipt of the packet. RXOUTI must /* The FIFO is empty.. Acknowledge receipt of the packet.
* always be cleared BEFORE clearing FIFOCON. * RXOUTI must always be cleared BEFORE clearing FIFOCON.
*/ */
regval = UEINTX; regval = UEINTX;
@ -802,11 +811,11 @@ static inline int avr_ep_nrecv(FAR struct avr_ep_s *privep,
} }
} }
/* We get here if the request buffer is full. There could be more bytes /* We get here if the request buffer is full. There could be more
* pending in the FIFO? * bytes pending in the FIFO?
* *
* Finalize the OUT stream transfer. RXOUTI must always be cleared BEFORE * Finalize the OUT stream transfer. RXOUTI must always be cleared
* clearing FIFOCON. * BEFORE clearing FIFOCON.
*/ */
regval = UEINTX; regval = UEINTX;
@ -825,8 +834,8 @@ static inline int avr_ep_nrecv(FAR struct avr_ep_s *privep,
* Description: * Description:
* This is part of the IN endpoint interrupt handling logic. It is called * This is part of the IN endpoint interrupt handling logic. It is called
* from interrupt handling logic for an endpoint when the TXIN endpoint * from interrupt handling logic for an endpoint when the TXIN endpoint
* interrupt occurs. Thus function is also called from the requeust enqueuing * interrupt occurs. Thus function is also called from the requeust
* logic BUT with interrupts disabled. * enqueuing logic BUT with interrupts disabled.
* *
****************************************************************************/ ****************************************************************************/
@ -868,8 +877,8 @@ static int avr_ep_in_queue(FAR struct avr_ep_s *privep)
if (ret == OK || ret != -ETIME) if (ret == OK || ret != -ETIME)
{ {
/* The transfer has completed, perhaps with an error. Return the request /* The transfer has completed, perhaps with an error.
* to the class driver. * Return the request to the class driver.
*/ */
usbtrace(TRACE_COMPLETE(privep->ep.eplog), privreq->req.xfrd); usbtrace(TRACE_COMPLETE(privep->ep.eplog), privreq->req.xfrd);
@ -885,9 +894,9 @@ static int avr_ep_in_queue(FAR struct avr_ep_s *privep)
* Name: avr_ep_out_queue * Name: avr_ep_out_queue
* *
* Description: * Description:
* This is part of the OUT endpointeinterrupt handling logic. It is called * This is part of the OUT endpointeinterrupt handling logic. It is
* from interrupt handling logic for an endpoint when the RXOUT endpoint * called from interrupt handling logic for an endpoint when the RXOUT
* interrupt occurs. * endpoint interrupt occurs.
* *
****************************************************************************/ ****************************************************************************/
@ -910,8 +919,8 @@ static int avr_ep_out_queue(FAR struct avr_ep_s *privep)
ret = avr_ep_nrecv(privep, &privreq->req); ret = avr_ep_nrecv(privep, &privreq->req);
/* The transfer has completed, perhaps with an error. Return the request /* The transfer has completed, perhaps with an error. Return the
* to the class driver. * request to the class driver.
*/ */
usbtrace(TRACE_COMPLETE(privep->ep.eplog), privreq->req.xfrd); usbtrace(TRACE_COMPLETE(privep->ep.eplog), privreq->req.xfrd);
@ -925,15 +934,17 @@ static int avr_ep_out_queue(FAR struct avr_ep_s *privep)
* Name: avr_reqcomplete * Name: avr_reqcomplete
* *
* Description: * Description:
* Handle termination of the request at the head of the endpoint request queue. * Handle termination of the request at the head of the endpoint request
* queue.
* *
****************************************************************************/ ****************************************************************************/
static void avr_reqcomplete(FAR struct avr_ep_s *privep, FAR struct avr_req_s *privreq, static void avr_reqcomplete(FAR struct avr_ep_s *privep,
FAR struct avr_req_s *privreq,
int result) int result)
{ {
/* If endpoint 0, temporarily reflect the state of protocol stalled in the /* If endpoint 0, temporarily reflect the state of protocol stalled in
* callback. * the callback.
*/ */
bool stalled = privep->stalled; bool stalled = privep->stalled;
@ -989,7 +1000,8 @@ static void avr_cancelrequests(FAR struct avr_ep_s *privep, int status)
while (!avr_rqempty(privep)) while (!avr_rqempty(privep))
{ {
usbtrace(TRACE_COMPLETE(privep->ep.eplog), (avr_rqpeek(privep))->req.xfrd); usbtrace(TRACE_COMPLETE(privep->ep.eplog),
(avr_rqpeek(privep))->req.xfrd);
avr_reqcomplete(privep, avr_rqdequeue(privep), status); avr_reqcomplete(privep, avr_rqdequeue(privep), status);
} }
} }
@ -1063,8 +1075,8 @@ static struct avr_ep_s *avr_epfindbyaddr(uint8_t epno)
* Name: avr_dispatchrequest * Name: avr_dispatchrequest
* *
* Description: * Description:
* Provide unhandled setup actions to the class driver. This is logically part * Provide unhandled setup actions to the class driver. This is logically
* of the USB interrupt handler. * part of the USB interrupt handler.
* *
****************************************************************************/ ****************************************************************************/
@ -1257,10 +1269,10 @@ static void avr_usbreset(void)
USBCON |= (1 << VBUSTE); USBCON |= (1 << VBUSTE);
/* Attach the device to the USB bus. This announces the device's presence to /* Attach the device to the USB bus. This announces the device's presence
* any attached USB host, starting the enumeration process. If no host is * to any attached USB host, starting the enumeration process. If no host
* present, attaching the device will allow for enumeration once a host is * is present, attaching the device will allow for enumeration once a host
* connected to the device. * is connected to the device.
*/ */
UDCON &= ~(1 << DETACH); UDCON &= ~(1 << DETACH);
@ -1430,11 +1442,13 @@ static inline void avr_ep0setup(void)
{ {
case USB_REQ_RECIPIENT_ENDPOINT: case USB_REQ_RECIPIENT_ENDPOINT:
{ {
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_EPGETSTATUS), 0); usbtrace(TRACE_INTDECODE(
AVR_TRACEINTID_EPGETSTATUS), 0);
privep = avr_epfindbyaddr(index); privep = avr_epfindbyaddr(index);
if (!privep) if (!privep)
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADEPGETSTATUS), 0); usbtrace(TRACE_DEVERROR(
AVR_TRACEERR_BADEPGETSTATUS), 0);
g_usbdev.stalled = true; g_usbdev.stalled = true;
} }
else else
@ -1443,7 +1457,8 @@ static inline void avr_ep0setup(void)
if (privep->stalled) if (privep->stalled)
{ {
g_usbdev.ep0buf[0] = (1 << USB_FEATURE_ENDPOINTHALT); /* Stalled */ g_usbdev.ep0buf[0] =
(1 << USB_FEATURE_ENDPOINTHALT); /* Stalled */
} }
else else
{ {
@ -1463,14 +1478,16 @@ static inline void avr_ep0setup(void)
{ {
if (index == 0) if (index == 0)
{ {
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_DEVGETSTATUS), 0); usbtrace(TRACE_INTDECODE(
AVR_TRACEINTID_DEVGETSTATUS), 0);
/* Features: Remote Wakeup=YES; selfpowered=? */ /* Features: Remote Wakeup=YES; selfpowered=? */
/* Return self-powered status */ /* Return self-powered status */
#ifdef CONFIG_USBDEV_SELFPOWERED #ifdef CONFIG_USBDEV_SELFPOWERED
g_usbdev.ep0buf[0] = (1 << USB_FEATURE_SELFPOWERED); g_usbdev.ep0buf[0] =
(1 << USB_FEATURE_SELFPOWERED);
#else #else
g_usbdev.ep0buf[0] = 0; g_usbdev.ep0buf[0] = 0;
#endif #endif
@ -1491,7 +1508,8 @@ static inline void avr_ep0setup(void)
} }
else else
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADDEVGETSTATUS), 0); usbtrace(TRACE_DEVERROR(
AVR_TRACEERR_BADDEVGETSTATUS), 0);
g_usbdev.stalled = true; g_usbdev.stalled = true;
} }
} }
@ -1499,7 +1517,8 @@ static inline void avr_ep0setup(void)
case USB_REQ_RECIPIENT_INTERFACE: case USB_REQ_RECIPIENT_INTERFACE:
{ {
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_IFGETSTATUS), 0); usbtrace(TRACE_INTDECODE(
AVR_TRACEINTID_IFGETSTATUS), 0);
g_usbdev.ep0buf[0] = 0; g_usbdev.ep0buf[0] = 0;
g_usbdev.ep0buf[1] = 0; g_usbdev.ep0buf[1] = 0;
@ -1509,7 +1528,8 @@ static inline void avr_ep0setup(void)
default: default:
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADGETSTATUS), 0); usbtrace(TRACE_DEVERROR(
AVR_TRACEERR_BADGETSTATUS), 0);
g_usbdev.stalled = true; g_usbdev.stalled = true;
} }
break; break;
@ -1520,9 +1540,10 @@ static inline void avr_ep0setup(void)
case USB_REQ_CLEARFEATURE: case USB_REQ_CLEARFEATURE:
{ {
/* type: host-to-device; recipient = device, interface or endpoint /* type: host-to-device; recipient = device, interface or
* value: feature selector index: zero interface endpoint; len: * endpoint
* zero, data = none * value: feature selector index: zero interface endpoint;
* len: zero, data = none
*/ */
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_CLEARFEATURE), 0); usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_CLEARFEATURE), 0);
@ -1538,7 +1559,8 @@ static inline void avr_ep0setup(void)
} }
else else
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADCLREPFEATURE), value); usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADCLREPFEATURE),
value);
g_usbdev.stalled = true; g_usbdev.stalled = true;
} }
break; break;
@ -1553,7 +1575,8 @@ static inline void avr_ep0setup(void)
} }
else else
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADCLRDEVFEATURE), value); usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADCLRDEVFEATURE),
value);
g_usbdev.stalled = true; g_usbdev.stalled = true;
} }
break; break;
@ -1569,7 +1592,8 @@ static inline void avr_ep0setup(void)
case USB_REQ_SETFEATURE: case USB_REQ_SETFEATURE:
{ {
/* type: host-to-device; recipient = device, interface, endpoint /* type: host-to-device; recipient = device, interface, endpoint
* value: feature selector index: zero interface endpoint; len: 0; * value: feature selector index: zero interface endpoint;
* len: 0;
* data = none * data = none
*/ */
@ -1586,7 +1610,8 @@ static inline void avr_ep0setup(void)
} }
else else
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADSETEPFEATURE), value); usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADSETEPFEATURE),
value);
g_usbdev.stalled = true; g_usbdev.stalled = true;
} }
break; break;
@ -1603,7 +1628,8 @@ static inline void avr_ep0setup(void)
} }
else else
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADSETDEVFEATURE), value); usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BADSETDEVFEATURE),
value);
g_usbdev.stalled = true; g_usbdev.stalled = true;
} }
break; break;
@ -1622,8 +1648,10 @@ static inline void avr_ep0setup(void)
* index: 0 len: 0; data = none * index: 0 len: 0; data = none
*/ */
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_EP0SETUPSETADDRESS), value); usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_EP0SETUPSETADDRESS),
if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && value);
if ((ctrl.type & USB_REQ_RECIPIENT_MASK) ==
USB_REQ_RECIPIENT_DEVICE &&
index == 0 && index == 0 &&
len == 0 && len == 0 &&
value < 128) value < 128)
@ -1648,13 +1676,14 @@ static inline void avr_ep0setup(void)
case USB_REQ_SETDESCRIPTOR: case USB_REQ_SETDESCRIPTOR:
{ {
/* type: host-to-device; recipient = device value: descriptor type /* type: host-to-device; recipient = device value: descriptor
* and index index: 0 or language ID; len: descriptor len; data = * type and index index: 0 or language ID; len: descriptor len;
* descriptor * data = descriptor
*/ */
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_GETSETDESC), 0); usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_GETSETDESC), 0);
if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) if ((ctrl.type & USB_REQ_RECIPIENT_MASK) ==
USB_REQ_RECIPIENT_DEVICE)
{ {
avr_dispatchrequest(&ctrl); avr_dispatchrequest(&ctrl);
} }
@ -1668,16 +1697,17 @@ static inline void avr_ep0setup(void)
case USB_REQ_GETCONFIGURATION: case USB_REQ_GETCONFIGURATION:
{ {
/* type: device-to-host; recipient = device value: 0; index: 0; len: /* type: device-to-host; recipient = device value: 0; index: 0;
* 1; data = configuration value * len: 1; data = configuration value
*/ */
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_GETCONFIG), 0); usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_GETCONFIG), 0);
if (g_usbdev.paddrset && if (g_usbdev.paddrset &&
(ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && (ctrl.type & USB_REQ_RECIPIENT_MASK) ==
value == 0 && USB_REQ_RECIPIENT_DEVICE &&
index == 0 && value == 0 &&
len == 1) index == 0 &&
len == 1)
{ {
avr_dispatchrequest(&ctrl); avr_dispatchrequest(&ctrl);
} }
@ -1696,9 +1726,10 @@ static inline void avr_ep0setup(void)
*/ */
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_SETCONFIG), 0); usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_SETCONFIG), 0);
if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && if ((ctrl.type & USB_REQ_RECIPIENT_MASK) ==
index == 0 && USB_REQ_RECIPIENT_DEVICE &&
len == 0) index == 0 &&
len == 0)
{ {
avr_dispatchrequest(&ctrl); avr_dispatchrequest(&ctrl);
} }
@ -1813,7 +1844,8 @@ static inline void avr_ep_ninterrupt(void)
/* Check if any endpoint interrupt is pending */ /* Check if any endpoint interrupt is pending */
for (epno = 1, mask = 2; epno < AVR_NENDPOINTS && ueint != 0; epno++, mask <<= 1) for (epno = 1, mask = 2; epno < AVR_NENDPOINTS &&
ueint != 0; epno++, mask <<= 1)
{ {
/* Is there an interrupt pending on this endpoint? */ /* Is there an interrupt pending on this endpoint? */
@ -1930,7 +1962,8 @@ static void avr_genvbus(void)
UDCON |= (1 << DETACH); UDCON |= (1 << DETACH);
/* Disable the clock inputs (the ”Resume Detection” is still active). /* Disable the clock inputs (the ”Resume Detection” is still active).
* This reduces the power consumption. Clear to enable the clock inputs. * This reduces the power consumption. Clear to enable the clock
* inputs.
*/ */
USBCON |= (1 << FRZCLK); USBCON |= (1 << FRZCLK);
@ -2400,7 +2433,8 @@ static int avr_epsubmit(FAR struct usbdev_ep_s *ep,
if (!g_usbdev.driver || g_usbdev.usbdev.speed == USB_SPEED_UNKNOWN) if (!g_usbdev.driver || g_usbdev.usbdev.speed == USB_SPEED_UNKNOWN)
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_NOTCONFIGURED), g_usbdev.usbdev.speed); usbtrace(TRACE_DEVERROR(AVR_TRACEERR_NOTCONFIGURED),
g_usbdev.usbdev.speed);
return -ESHUTDOWN; return -ESHUTDOWN;
} }
@ -2433,8 +2467,8 @@ static int avr_epsubmit(FAR struct usbdev_ep_s *ep,
avr_rqenqueue(privep, privreq); avr_rqenqueue(privep, privreq);
/* Some special operations have to be performed for IN requests. For /* Some special operations have to be performed for IN requests.
* these, we may have to initiate the next transfer. * For these, we may have to initiate the next transfer.
*/ */
if (privep->epin) if (privep->epin)
@ -2461,7 +2495,9 @@ static int avr_epsubmit(FAR struct usbdev_ep_s *ep,
usbtrace(TRACE_OUTREQQUEUED(privep->ep.eplog), privreq->req.len); usbtrace(TRACE_OUTREQQUEUED(privep->ep.eplog), privreq->req.len);
/* If there is something available in the fifo now, then go get it */ /* If there is something available in the fifo now,
* then go get it
*/
if (avr_fifoready(AVR_TIMEOUT_NONE) == OK) if (avr_fifoready(AVR_TIMEOUT_NONE) == OK)
{ {
@ -2498,9 +2534,10 @@ static int avr_epcancel(FAR struct usbdev_ep_s *ep,
usbtrace(TRACE_EPCANCEL, privep->ep.eplog); usbtrace(TRACE_EPCANCEL, privep->ep.eplog);
/* FIXME: if the request is the first, then we need to flush the EP otherwise /* FIXME:
* just remove it from the list but ... all other implementations cancel all * if the request is the first, then we need to flush the EP otherwise
* requests ... * just remove it from the list but ... all other implementations cancel
* all requests ...
*/ */
flags = enter_critical_section(); flags = enter_critical_section();
@ -2555,12 +2592,13 @@ static int avr_epstall(FAR struct usbdev_ep_s *ep, bool resume)
* Allocate an endpoint matching the parameters. * Allocate an endpoint matching the parameters.
* *
* Input Parameters: * Input Parameters:
* eplog - 7-bit logical endpoint number (direction bit ignored). Zero means * eplog - 7-bit logical endpoint number (direction bit ignored). Zero
* that any endpoint matching the other requirements will suffice. The * means that any endpoint matching the other requirements will
* assigned endpoint can be found in the eplog field. * suffice. The assigned endpoint can be found in the eplog
* field.
* in - true: IN (device-to-host) endpoint requested * in - true: IN (device-to-host) endpoint requested
* eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK, * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC,
* USB_EP_ATTR_XFER_INT} * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT}
* *
****************************************************************************/ ****************************************************************************/
@ -2771,9 +2809,9 @@ static int avr_pullup(struct usbdev_s *dev, bool enable)
* Assumptions: * Assumptions:
* - This function is called very early in the initialization sequence * - This function is called very early in the initialization sequence
* - PLL and GIO pin initialization is not performed here but should been in * - PLL and GIO pin initialization is not performed here but should been in
* the low-level boot logic: PLL1 must be configured for operation at 48MHz * the low-level boot logic: PLL1 must be configured for operation at
* and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB connect * 48MHz and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB
* LED. * connect LED.
* *
****************************************************************************/ ****************************************************************************/
@ -2792,7 +2830,8 @@ void up_usbinitialize(void)
if (irq_attach(AT90USB_IRQ_USBGEN, avr_geninterrupt, NULL) != 0) if (irq_attach(AT90USB_IRQ_USBGEN, avr_geninterrupt, NULL) != 0)
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_IRQREGISTRATION), AT90USB_IRQ_USBGEN); usbtrace(TRACE_DEVERROR(AVR_TRACEERR_IRQREGISTRATION),
AT90USB_IRQ_USBGEN);
goto errout; goto errout;
} }
@ -2800,7 +2839,8 @@ void up_usbinitialize(void)
if (irq_attach(AT90USB_IRQ_USBEP, avr_epinterrupt, NULL) != 0) if (irq_attach(AT90USB_IRQ_USBEP, avr_epinterrupt, NULL) != 0)
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_IRQREGISTRATION), AT90USB_IRQ_USBEP); usbtrace(TRACE_DEVERROR(AVR_TRACEERR_IRQREGISTRATION),
AT90USB_IRQ_USBEP);
goto errout; goto errout;
} }
@ -2868,8 +2908,8 @@ void up_usbuninitialize(void)
* Name: usbdev_register * Name: usbdev_register
* *
* Description: * Description:
* Register a USB device class driver. The class driver's bind() method will be * Register a USB device class driver. The class driver's bind() method
* called to bind it to a USB device driver. * will be called to bind it to a USB device driver.
* *
****************************************************************************/ ****************************************************************************/
@ -2903,17 +2943,19 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
ret = CLASS_BIND(driver, &g_usbdev.usbdev); ret = CLASS_BIND(driver, &g_usbdev.usbdev);
if (ret) if (ret)
{ {
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BINDFAILED), (uint16_t) - ret); usbtrace(TRACE_DEVERROR(AVR_TRACEERR_BINDFAILED),
(uint16_t) - ret);
g_usbdev.driver = NULL; g_usbdev.driver = NULL;
} }
else else
{ {
/* FIXME: nothing seems to call DEV_CONNECT(), but we need to set the RS /* FIXME:
* nothing seems to call DEV_CONNECT(), but we need to set the RS
* bit to enable the controller. It kind of makes sense to do this * bit to enable the controller. It kind of makes sense to do this
* after the class has bound to us... GEN: This bug is really in the * after the class has bound to us... GEN: This bug is really in the
* class driver. It should make the soft connect when it is ready to be * class driver. It should make the soft connect when it is ready to
* enumerated. I have added that logic to the class drivers but left * be enumerated. I have added that logic to the class drivers but
* this logic here. * left this logic here.
*/ */
avr_pullup(&g_usbdev.usbdev, true); avr_pullup(&g_usbdev.usbdev, true);
@ -2926,9 +2968,10 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
* Name: usbdev_unregister * Name: usbdev_unregister
* *
* Description: * Description:
* Un-register usbdev class driver.If the USB device is connected to a USB host, * Un-register usbdev class driver.If the USB device is connected to a USB
* it will first disconnect(). The driver is also requested to unbind() and clean * host, it will first disconnect(). The driver is also requested to
* up any device state, before this procedure finally returns. * unbind() and clean up any device state, before this procedure finally
* returns.
* *
****************************************************************************/ ****************************************************************************/
@ -2958,12 +3001,13 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
* Name: avr_pollvbus * Name: avr_pollvbus
* *
* Description: * Description:
* Sample VBUS to see if there are changes in our connection status. There * Sample VBUS to see if there are changes in our connection status.
* is actually an interrupt to signal this case so it should not be necessary * There is actually an interrupt to signal this case so it should not be
* to poll our connection status. However, on certain "noisy" systems, VBUS * necessary to poll our connection status. However, on certain "noisy"
* may bounce and provide inaccurate information in the interrupt handler * systems, VBUS may bounce and provide inaccurate information in the
* (especially if a relay is used to switch VBUS!). This poll is, then, * interrupt handler (especially if a relay is used to switch VBUS!).
* simply a failsafe to assure that VBUS connection events are never missed. * This poll is, then, simply a failsafe to assure that VBUS connection
* events are never missed.
* *
****************************************************************************/ ****************************************************************************/

2
arch/avr/src/at90usb/chip.h
View File

@ -80,7 +80,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_ATMEGA_CHIP_H */ #endif /* __ARCH_AVR_SRC_ATMEGA_CHIP_H */

30
arch/avr/src/atmega/atmega_config.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/atmega/atmega_config.h * arch/avr/src/atmega/atmega_config.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,23 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H #ifndef __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H
#define __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H #define __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* USARTs ***************************************************************************/
/* USARTs *******************************************************************/
/* Check if any USART is selected */ /* Check if any USART is selected */
#undef HAVE_USART_DEVICE #undef HAVE_USART_DEVICE
@ -85,16 +87,16 @@
# define USE_SERIALDRIVER 1 # define USE_SERIALDRIVER 1
#endif #endif
/************************************************************************************ /****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H */ #endif /* __ARCH_AVR_SRC_ATMEGA_ATMEGA_CONFIG_H */

21
arch/avr/src/atmega/atmega_lowconsole.c
View File

@ -48,8 +48,8 @@
#define AVR_DBLSPEED_UBRR0 \ #define AVR_DBLSPEED_UBRR0 \
((((BOARD_CPU_CLOCK / 8) + (CONFIG_USART0_BAUD / 2)) / (CONFIG_USART0_BAUD)) - 1) ((((BOARD_CPU_CLOCK / 8) + (CONFIG_USART0_BAUD / 2)) / (CONFIG_USART0_BAUD)) - 1)
/* Select normal or double speed baud settings. This is a trade-off between the /* Select normal or double speed baud settings. This is a trade-off between
* sampling rate and the accuracy of the divisor for high baud rates. * the sampling rate and the accuracy of the divisor for high baud rates.
* *
* As examples, consider: * As examples, consider:
* *
@ -110,8 +110,8 @@
#define AVR_DBLSPEED_UBRR1 \ #define AVR_DBLSPEED_UBRR1 \
((((BOARD_CPU_CLOCK / 8) + (CONFIG_USART1_BAUD / 2)) / (CONFIG_USART1_BAUD)) - 1) ((((BOARD_CPU_CLOCK / 8) + (CONFIG_USART1_BAUD / 2)) / (CONFIG_USART1_BAUD)) - 1)
/* Select normal or double speed baud settings. This is a trade-off between the /* Select normal or double speed baud settings. This is a trade-off between
* sampling rate and the accuracy of the divisor for high baud rates. * the sampling rate and the accuracy of the divisor for high baud rates.
* *
* As examples, consider: * As examples, consider:
* *
@ -401,10 +401,11 @@ void usart1_configure(void)
/* Pin Configuration: None necessary, Port D bits 2&3 are automatically /* Pin Configuration: None necessary, Port D bits 2&3 are automatically
* configured: * configured:
* *
* Port D, Bit 2: RXD1, Receive Data (Data input pin for the USART1). When * Port D, Bit 2: RXD1, Receive Data (Data input pin for the USART1).
* the USART1 receiver is enabled this pin is configured as an input * When the USART1 receiver is enabled this pin is configured as an
* regardless of the value of DDD2. When the USART forces this pin to * input regardless of the value of DDD2. When the USART forces this
* be an input, the pull-up can still be controlled by the PORTD2 bit. * pin to be an input, the pull-up can still be controlled by the
* PORTD2 bit.
* Port D, Bit 3: TXD1, Transmit Data (Data output pin for the USART1). * Port D, Bit 3: TXD1, Transmit Data (Data output pin for the USART1).
* When the USART1 Transmitter is enabled, this pin is configured as * When the USART1 Transmitter is enabled, this pin is configured as
* an output regardless of the value of DDD3. * an output regardless of the value of DDD3.
@ -425,8 +426,8 @@ void usart1_configure(void)
* *
* Description: * Description:
* Initialize a console for debug output. This function is called very * Initialize a console for debug output. This function is called very
* early in the initialization sequence to configure the serial console uart * early in the initialization sequence to configure the serial console
* (only). * uart (only).
* *
****************************************************************************/ ****************************************************************************/

2
arch/avr/src/atmega/atmega_memorymap.h
View File

@ -40,7 +40,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions Prototypes
************************************************************************************/ ************************************************************************************/
#endif /* __ARCH_AVR_SRC_ATMEGA_ATMEGA_MEMORYMAP_H */ #endif /* __ARCH_AVR_SRC_ATMEGA_ATMEGA_MEMORYMAP_H */

65
arch/avr/src/atmega/atmega_serial.c
View File

@ -213,7 +213,7 @@ static uart_dev_t g_usart1port =
{ {
.size = CONFIG_USART1_TXBUFSIZE, .size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer, .buffer = g_usart1txbuffer,
}, },
.ops = &g_usart1_ops, .ops = &g_usart1_ops,
}; };
#endif #endif
@ -346,14 +346,15 @@ static void usart1_shutdown(struct uart_dev_s *dev)
* Name: usart0/1_attach * Name: usart0/1_attach
* *
* Description: * Description:
* Configure the USART to operation in interrupt driven mode. This method is * Configure the USART to operation in interrupt driven mode. This method
* called when the serial port is opened. Normally, this is just after the * is called when the serial port is opened. Normally, this is just after
* the setup() method is called, however, the serial console may operate in * the the setup() method is called, however, the serial console may
* a non-interrupt driven mode during the boot phase. * operate in a non-interrupt driven mode during the boot phase.
* *
* RX and TX interrupts are not enabled when by the attach method (unless the * RX and TX interrupts are not enabled when by the attach method (unless
* hardware supports multiple levels of interrupt enabling). The RX and TX * the hardware supports multiple levels of interrupt enabling). The RX
* interrupts are not enabled until the txint() and rxint() methods are called. * and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
* *
****************************************************************************/ ****************************************************************************/
@ -367,14 +368,16 @@ static int usart0_attach(struct uart_dev_s *dev)
* TX: USART Transmit Complete. Set when the entire frame in the Transmit * TX: USART Transmit Complete. Set when the entire frame in the Transmit
* Shift Register has been shifted out and there are no new data * Shift Register has been shifted out and there are no new data
* currently present in the transmit buffer. * currently present in the transmit buffer.
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready * DRE: USART Data Register Empty. Indicates if the transmit buffer is
* to receive new data: The buffer is empty, and therefore ready to be * ready to receive new data: The buffer is empty, and therefore ready
* written. * to be written.
*/ */
irq_attach(ATMEGA_IRQ_U0RX, usart0_rxinterrupt, NULL); irq_attach(ATMEGA_IRQ_U0RX, usart0_rxinterrupt, NULL);
irq_attach(ATMEGA_IRQ_U0DRE, usart0_txinterrupt, NULL); irq_attach(ATMEGA_IRQ_U0DRE, usart0_txinterrupt, NULL);
//(void)irq_attach(ATMEGA_IRQ_U0TX, usart0_txinterrupt, NULL);
/* (void)irq_attach(ATMEGA_IRQ_U0TX, usart0_txinterrupt, NULL); */
return OK; return OK;
} }
#endif #endif
@ -389,14 +392,16 @@ static int usart1_attach(struct uart_dev_s *dev)
* TX: USART Transmit Complete. Set when the entire frame in the Transmit * TX: USART Transmit Complete. Set when the entire frame in the Transmit
* Shift Register has been shifted out and there are no new data * Shift Register has been shifted out and there are no new data
* currently present in the transmit buffer. * currently present in the transmit buffer.
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready * DRE: USART Data Register Empty. Indicates if the transmit buffer is
* to receive new data: The buffer is empty, and therefore ready to be * ready to receive new data: The buffer is empty, and therefore ready
* written. * to be written.
*/ */
irq_attach(ATMEGA_IRQ_U1RX, usart1_rxinterrupt, NULL); irq_attach(ATMEGA_IRQ_U1RX, usart1_rxinterrupt, NULL);
irq_attach(ATMEGA_IRQ_U1DRE, usart1_txinterrupt, NULL); irq_attach(ATMEGA_IRQ_U1DRE, usart1_txinterrupt, NULL);
//(void)irq_attach(ATMEGA_IRQ_U1TX, usart1_txinterrupt, NULL);
/* (void)irq_attach(ATMEGA_IRQ_U1TX, usart1_txinterrupt, NULL); */
return OK; return OK;
} }
#endif #endif
@ -406,8 +411,8 @@ static int usart1_attach(struct uart_dev_s *dev)
* *
* Description: * Description:
* Detach USART interrupts. This method is called when the serial port is * Detach USART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception * closed normally just before the shutdown method is called. The
* is the serial console which is never shutdown. * exception is the serial console which is never shutdown.
* *
****************************************************************************/ ****************************************************************************/
@ -422,7 +427,8 @@ static void usart0_detach(struct uart_dev_s *dev)
irq_detach(ATMEGA_IRQ_U0RX); irq_detach(ATMEGA_IRQ_U0RX);
irq_detach(ATMEGA_IRQ_U0DRE); irq_detach(ATMEGA_IRQ_U0DRE);
// (void)irq_detach(ATMEGA_IRQ_U0TX);
/* (void)irq_detach(ATMEGA_IRQ_U0TX); */
} }
#endif #endif
@ -437,7 +443,8 @@ static void usart1_detach(struct uart_dev_s *dev)
irq_detach(ATMEGA_IRQ_U1RX); irq_detach(ATMEGA_IRQ_U1RX);
irq_detach(ATMEGA_IRQ_U1DRE); irq_detach(ATMEGA_IRQ_U1DRE);
//(void)irq_detach(ATMEGA_IRQ_U1TX);
/* (void)irq_detach(ATMEGA_IRQ_U1TX); */
} }
#endif #endif
@ -749,9 +756,9 @@ static void usart0_txint(struct uart_dev_s *dev, bool enable)
* TX: USART Transmit Complete. Set when the entire frame in the Transmit * TX: USART Transmit Complete. Set when the entire frame in the Transmit
* Shift Register has been shifted out and there are no new data * Shift Register has been shifted out and there are no new data
* currently present in the transmit buffer. * currently present in the transmit buffer.
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready * DRE: USART Data Register Empty. Indicates if the transmit buffer is
* to receive new data: The buffer is empty, and therefore ready to be * ready to receive new data: The buffer is empty, and therefore ready
* written. * to be written.
*/ */
flags = enter_critical_section(); flags = enter_critical_section();
@ -761,7 +768,8 @@ static void usart0_txint(struct uart_dev_s *dev, bool enable)
#ifndef CONFIG_SUPPRESS_SERIAL_INTS #ifndef CONFIG_SUPPRESS_SERIAL_INTS
UCSR0B |= (1 << UDRIE0); UCSR0B |= (1 << UDRIE0);
// UCSR0B |= (1 << TXCIE0);
/* UCSR0B |= (1 << TXCIE0); */
/* Fake a TX interrupt here by just calling uart_xmitchars() with /* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse). * interrupts disabled (note this may recurse).
@ -791,9 +799,9 @@ static void usart1_txint(struct uart_dev_s *dev, bool enable)
* TX: USART Transmit Complete. Set when the entire frame in the Transmit * TX: USART Transmit Complete. Set when the entire frame in the Transmit
* Shift Register has been shifted out and there are no new data * Shift Register has been shifted out and there are no new data
* currently present in the transmit buffer. * currently present in the transmit buffer.
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready * DRE: USART Data Register Empty. Indicates if the transmit buffer is
* to receive new data: The buffer is empty, and therefore ready to be * ready to receive new data: The buffer is empty, and therefore ready
* written. * to be written.
*/ */
flags = enter_critical_section(); flags = enter_critical_section();
@ -803,7 +811,8 @@ static void usart1_txint(struct uart_dev_s *dev, bool enable)
#ifndef CONFIG_SUPPRESS_SERIAL_INTS #ifndef CONFIG_SUPPRESS_SERIAL_INTS
UCSR1B |= (1 << UDRIE1); UCSR1B |= (1 << UDRIE1);
// UCSR1B |= (1 << TXCIE1);
/* UCSR1B |= (1 << TXCIE1); */
/* Fake a TX interrupt here by just calling uart_xmitchars() with /* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse). * interrupts disabled (note this may recurse).

36
arch/avr/src/atmega/chip.h
View File

@ -1,4 +1,4 @@
/************************************************************************************ /****************************************************************************
* arch/avr/src/atmega/chip.h * arch/avr/src/atmega/chip.h
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,17 @@
* License for the specific language governing permissions and limitations * License for the specific language governing permissions and limitations
* under the License. * under the License.
* *
************************************************************************************/ ****************************************************************************/
#ifndef __ARCH_AVR_SRC_ATMEGA_CHIP_H #ifndef __ARCH_AVR_SRC_ATMEGA_CHIP_H
#define __ARCH_AVR_SRC_ATMEGA_CHIP_H #define __ARCH_AVR_SRC_ATMEGA_CHIP_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Define features for supported chip in the ATMEGA family */ /* Define features for supported chip in the ATMEGA family */
#if 1 #if 1
@ -38,22 +34,28 @@
# error "Unsupported AVR chip" # error "Unsupported AVR chip"
#endif #endif
/* Include only the memory map. Other chip hardware files should then include this /* Include only the memory map.
* file for the proper setup * Other chip hardware files should then include this file for the proper
* setup
*
*/ */
#include "atmega_memorymap.h" #include "atmega_memorymap.h"
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types * Public Types
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Data * Public Data
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions Prototypes Prototypes
************************************************************************************/ ****************************************************************************/
#endif /* __ARCH_AVR_SRC_ATMEGA_CHIP_H */ #endif /* __ARCH_AVR_SRC_ATMEGA_CHIP_H */

69
arch/avr/src/avr/avr.h
View File

@ -61,9 +61,9 @@
extern volatile uint8_t *g_current_regs; extern volatile uint8_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S. This is the first /* This is the beginning of heap as provided from up_head.S. This is the
* address in DRAM after the loaded program+bss+idle stack. The end of the * first address in DRAM after the loaded program+bss+idle stack. The end
* heap is CONFIG_RAM_END * of the heap is CONFIG_RAM_END
*/ */
extern uint16_t g_idle_topstack; extern uint16_t g_idle_topstack;
@ -75,51 +75,51 @@ extern uint16_t g_idle_topstack;
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions Prototypes
****************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct spi_dev_s; /* Forward references */ struct spi_dev_s; /* Forward references */
/************************************************************************************ /****************************************************************************
* Name: up_copystate * Name: up_copystate
* *
* Description: * Description:
* Copy the contents of a register state save structure from one location to * Copy the contents of a register state save structure from one location
* another. * to another.
* *
************************************************************************************/ ****************************************************************************/
void up_copystate(uint8_t *dest, uint8_t *src); void up_copystate(uint8_t *dest, uint8_t *src);
/************************************************************************************ /****************************************************************************
* Name: up_fullcontextrestore * Name: up_fullcontextrestore
* *
* Description: * Description:
* Restore the full context of a saved thread/task. * Restore the full context of a saved thread/task.
* *
************************************************************************************/ ****************************************************************************/
void up_fullcontextrestore(uint8_t *restoreregs) noreturn_function; void up_fullcontextrestore(uint8_t *restoreregs) noreturn_function;
/************************************************************************************ /****************************************************************************
* Name: up_switchcontext * Name: up_switchcontext
* *
* Description: * Description:
* Switch from one thread/task context to another. * Switch from one thread/task context to another.
* *
************************************************************************************/ ****************************************************************************/
void up_switchcontext(uint8_t *saveregs, uint8_t *restoreregs); void up_switchcontext(uint8_t *saveregs, uint8_t *restoreregs);
/************************************************************************************ /****************************************************************************
* Name: up_doirq * Name: up_doirq
* *
* Description: * Description:
* Dispatch an interrupt. * Dispatch an interrupt.
* *
************************************************************************************/ ****************************************************************************/
uint8_t *up_doirq(uint8_t irq, uint8_t *regs); uint8_t *up_doirq(uint8_t irq, uint8_t *regs);
@ -139,35 +139,38 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs);
FAR struct spi_dev_s *avr_spibus_initialize(int port); FAR struct spi_dev_s *avr_spibus_initialize(int port);
/************************************************************************************ /****************************************************************************
* Name: avr_spiselect, avr_spitatus, and avr_spicmddata * Name: avr_spiselect, avr_spitatus, and avr_spicmddata
* *
* Description: * Description:
* These external functions must be provided by board-specific logic. They are * These external functions must be provided by board-specific logic. They
* implementations of the select, status, and cmddata methods of the SPI interface * are implementations of the select, status, and cmddata methods of the
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods * SPI interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
* including avr_spibus_initialize()) are provided by common AVR logic. To use * All other methods including avr_spibus_initialize()) are provided by
* this common SPI logic on your board: * common AVR logic. To use this common SPI logic on your board:
* *
* 1. Provide logic in <arch>_boardinitialize() to configure SPI chip select * 1. Provide logic in <arch>_boardinitialize() to configure SPI chip
* pins. * select pins.
* 2. Provide avr_spiselect() and avr_spistatus() functions in your board-specific * 2. Provide avr_spiselect() and avr_spistatus() functions in your
* logic. These functions will perform chip selection and status operations * board-specific logic. These functions will perform chip selection
* using GPIOs in the way your board is configured. * and status operations using GPIOs in the way your board is
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide the
* avr_spicmddata() function in your board-specific logic. This functions will
* perform cmd/data selection operations using GPIOs in the way your board is
* configured. * configured.
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
* the avr_spicmddata() function in your board-specific logic. This
* functions will perform cmd/data selection operations using GPIOs in
* the way your board is configured.
* 3. Add a call to at90usb_spiinitialize() in your low level application * 3. Add a call to at90usb_spiinitialize() in your low level application
* initialization logic * initialization logic
* 4. The handle returned by avr_spibus_initialize() may then be used to bind the * 4. The handle returned by avr_spibus_initialize() may then be used to
* SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), * bind the SPI driver to higher level logic (e.g., calling
* for example, will bind the SPI driver to the SPI MMC/SD driver). * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_AVR_SPI #ifdef CONFIG_AVR_SPI
void avr_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); void avr_spiselect(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t avr_spistatus(FAR struct spi_dev_s *dev, uint32_t devid); uint8_t avr_spistatus(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_SPI_CMDDATA
int avr_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); int avr_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);

802
arch/avr/src/avr/excptmacros.h
View File

File diff suppressed because it is too large Load Diff

3
arch/avr/src/avr/up_checkstack.c
View File

@ -167,7 +167,8 @@ ssize_t up_check_stack_remain(void)
#if CONFIG_ARCH_INTERRUPTSTACK > 3 #if CONFIG_ARCH_INTERRUPTSTACK > 3
size_t up_check_intstack(void) size_t up_check_intstack(void)
{ {
uintptr_t start = (uintptr_t)g_intstackbase - (CONFIG_ARCH_INTERRUPTSTACK & ~3); uintptr_t start = (uintptr_t)g_intstackbase -
(CONFIG_ARCH_INTERRUPTSTACK & ~3);
return do_stackcheck(start, (CONFIG_ARCH_INTERRUPTSTACK & ~3)); return do_stackcheck(start, (CONFIG_ARCH_INTERRUPTSTACK & ~3));
} }

4
arch/avr/src/avr/up_doirq.c
View File

@ -64,8 +64,8 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs)
uint8_t *savestate; uint8_t *savestate;
/* Nested interrupts are not supported in this implementation. If you want /* Nested interrupts are not supported in this implementation. If you want
* to implement nested interrupts, you would have to (1) change the way that * to implement nested interrupts, you would have to (1) change the way
* g_current_regs is handled and (2) the design associated with * that g_current_regs is handled and (2) the design associated with
* CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for
* that purpose as implemented here because only the outermost nested * that purpose as implemented here because only the outermost nested
* interrupt can result in a context switch (it can probably be deleted). * interrupt can result in a context switch (it can probably be deleted).

4
arch/avr/src/avr/up_romgetc.c
View File

@ -73,8 +73,8 @@
* lie in FLASH (string arguments for %s are still assumed to reside in * lie in FLASH (string arguments for %s are still assumed to reside in
* SRAM). And (2), the string argument to puts and fputs is assumed to * SRAM). And (2), the string argument to puts and fputs is assumed to
* reside in FLASH. Clearly, these assumptions may have to modified for * reside in FLASH. Clearly, these assumptions may have to modified for
* the particular needs of your environment. There is no "one-size-fits-all" * the particular needs of your environment.
* solution for this problem. * There is no "one-size-fits-all" solution for this problem.
* *
* Additional AVR Assumptions: * Additional AVR Assumptions:
* *

26
arch/avr/src/avr32/avr32.h
View File

@ -59,9 +59,9 @@
extern volatile uint32_t *g_current_regs; extern volatile uint32_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S. This is the first /* This is the beginning of heap as provided from up_head.S. This is the
* address in DRAM after the loaded program+bss+idle stack. The end of the * first address in DRAM after the loaded program+bss+idle stack.
* heap is CONFIG_RAM_END * The end of the heap is CONFIG_RAM_END
*/ */
extern uint32_t g_idle_topstack; extern uint32_t g_idle_topstack;
@ -78,44 +78,44 @@ extern uint32_t g_idle_topstack;
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/************************************************************************************ /****************************************************************************
* Name: up_copystate * Name: up_copystate
* *
* Description: * Description:
* Copy the contents of a register state save structure from one location to * Copy the contents of a register state save structure from one location
* another. * to another.
* *
************************************************************************************/ ****************************************************************************/
void up_copystate(uint32_t *dest, uint32_t *src); void up_copystate(uint32_t *dest, uint32_t *src);
/************************************************************************************ /****************************************************************************
* Name: up_fullcontextrestore * Name: up_fullcontextrestore
* *
* Description: * Description:
* Restore the full context of a saved thread/task. * Restore the full context of a saved thread/task.
* *
************************************************************************************/ ****************************************************************************/
void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
/************************************************************************************ /****************************************************************************
* Name: up_switchcontext * Name: up_switchcontext
* *
* Description: * Description:
* Switch from one thread/task context to another. * Switch from one thread/task context to another.
* *
************************************************************************************/ ****************************************************************************/
void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
/************************************************************************************ /****************************************************************************
* Name: up_doirq * Name: up_doirq
* *
* Description: * Description:
* Dispatch an interrupt. * Dispatch an interrupt.
* *
************************************************************************************/ ****************************************************************************/
uint32_t *up_doirq(int irq, uint32_t *regs); uint32_t *up_doirq(int irq, uint32_t *regs);

4
arch/avr/src/common/up_udelay.c
View File

@ -85,6 +85,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++) for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++)
{ {
} }
microseconds -= 1000; microseconds -= 1000;
} }
@ -93,6 +94,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++) for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++)
{ {
} }
microseconds -= 100; microseconds -= 100;
} }
@ -101,6 +103,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++) for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++)
{ {
} }
microseconds -= 10; microseconds -= 10;
} }
@ -109,6 +112,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++) for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++)
{ {
} }
microseconds--; microseconds--;
} }
} }