sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fix some MIPS software interrupt enabling issues

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4067 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-10-29 02:29:13 +00:00
parent 004a4420fa
commit b8ebda1ae6
4 changed files with 583 additions and 578 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/mips/include/mips32/cp0.h
View File

@ -278,7 +278,7 @@
# define CP0_CAUSE_IP5 (0x13 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 3 */ # define CP0_CAUSE_IP5 (0x13 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 3 */
# define CP0_CAUSE_IP6 (0x14 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 4 */ # define CP0_CAUSE_IP6 (0x14 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 4 */
# define CP0_CAUSE_IP7 (0x15 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 5, timer or performance counter interrupt */ # define CP0_CAUSE_IP7 (0x15 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 5, timer or performance counter interrupt */
#define CP0_CAUSE_WP (1 << 22 Watch exception was deferred #define CP0_CAUSE_WP (1 << 22) /* Watch exception was deferred
#define CP0_CAUSE_IV (1 << 23) /* Bit 23: Interrupt exception uses special interrupt vector */ #define CP0_CAUSE_IV (1 << 23) /* Bit 23: Interrupt exception uses special interrupt vector */
#define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number fo Coprocessor Unusable exception */ #define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number fo Coprocessor Unusable exception */
#define CP0_CAUSE_CE_MASK (3 << CP0_CAUSE_CE_SHIFT) #define CP0_CAUSE_CE_MASK (3 << CP0_CAUSE_CE_SHIFT)

2
arch/mips/src/mips32/up_irq.c
View File

@ -83,7 +83,7 @@ irqstate_t irqsave(void)
status &= ~CP0_STATUS_IM_MASK; /* Clear all interrupt mask bits */ status &= ~CP0_STATUS_IM_MASK; /* Clear all interrupt mask bits */
status |= CP0_STATUS_IM_SWINTS; /* Keep S/W interrupts enabled */ status |= CP0_STATUS_IM_SWINTS; /* Keep S/W interrupts enabled */
cp0_putstatus(status); /* Disable interrupts */ cp0_putstatus(status); /* Disable interrupts */
return ret; /* Return status before interrtupts disabled */ return ret; /* Return status before interrupts disabled */
} }
/**************************************************************************** /****************************************************************************

7
arch/mips/src/pic32mx/pic32mx-irq.c
View File

@ -136,16 +136,19 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */ /* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Interrupts are enabled by setting the IE bit in the CP0 status register */ /* Interrupts are enabled by setting the IE bit in the CP0 status register */
regval = 0; regval = 0;
asm volatile("ei %0" : "=r"(regval)); asm volatile("ei %0" : "=r"(regval));
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Then enable all interrupt levels */ /* Then enable all interrupt levels */
irqrestore(CP0_STATUS_IM_ALL); irqrestore(CP0_STATUS_IM_ALL);
#else
/* Enable only software interrupts */
irqrestore(CP0_STATUS_IM_SWINTS);
#endif #endif
} }

2
include/cxx/cstring
View File

@ -52,8 +52,10 @@ namespace std
using ::size_t; using ::size_t;
using ::strchr; using ::strchr;
using ::strdup; using ::strdup;
using ::strndup;
using ::strerror; using ::strerror;
using ::strlen; using ::strlen;
using ::strnlen;
using ::strcat; using ::strcat;
using ::strncat; using ::strncat;
using ::strcmp; using ::strcmp;