A few fixes for LPC1788 compilation (more needed)
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5649 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
c74cfe3838
commit
b92f43793f
@ -218,8 +218,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
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# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
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# define LPC17_CPUSRAM_SIZE (8*1024)
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# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
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# define LPC17_CPUSRAM_SIZE (32*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
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# undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
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# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
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@ -234,8 +234,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
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# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
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# define LPC17_CPUSRAM_SIZE (8*1024)
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# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
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# define LPC17_CPUSRAM_SIZE (32*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
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# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
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# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
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@ -250,8 +250,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
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# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
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# define LPC17_CPUSRAM_SIZE (16*1024)
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# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
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# define LPC17_CPUSRAM_SIZE (64*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
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# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
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# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
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@ -266,8 +266,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
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# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
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# define LPC17_CPUSRAM_SIZE (32*1024)
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# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
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# define LPC17_CPUSRAM_SIZE (64*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
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# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
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# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
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@ -282,8 +282,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
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# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
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# define LPC17_CPUSRAM_SIZE (32*1024)
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# define LPC17_SRAM_SIZE (96*1024) /* 64Kb */
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# define LPC17_CPUSRAM_SIZE (64*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
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# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
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# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
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@ -298,8 +298,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
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# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
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# define LPC17_CPUSRAM_SIZE (16*1024)
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# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
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# define LPC17_CPUSRAM_SIZE (64*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
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# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
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# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
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@ -314,8 +314,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
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# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
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# define LPC17_CPUSRAM_SIZE (16*1024)
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# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
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# define LPC17_CPUSRAM_SIZE (64*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
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# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
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# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
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@ -330,8 +330,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
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# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
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# define LPC17_CPUSRAM_SIZE (32*1024)
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# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
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# define LPC17_CPUSRAM_SIZE (64*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
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# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
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# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
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@ -346,8 +346,8 @@
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# undef LPC176x /* Not LPC175/6 family */
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# define LPC178x 1 /* LPC177/8 family */
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# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
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# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
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# define LPC17_CPUSRAM_SIZE (32*1024)
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# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
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# define LPC17_CPUSRAM_SIZE (64*1024)
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# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
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# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
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# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
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@ -276,7 +276,7 @@
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#define SYSCON_EMCDIV (1 << 0) /* Bit 0: EMC Clock rate relative to CPU */
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/* 0: EMC uses same clock as CPU */
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/* 1: EMC uses half the rate of CPU */
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/* Bits 1-31: Reserved
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/* Bits 1-31: Reserved */
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/* CPU Clock Configuration register */
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#define SYSCON_CCLKCFG_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */
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@ -387,7 +387,7 @@
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#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */
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#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */
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#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */
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#define SYSCON_PCONP_PCSSP0 (1 << 20) /* Bit 20: SSP2 power/clock control */
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#define SYSCON_PCONP_PCSSP2 (1 << 20) /* Bit 20: SSP2 power/clock control */
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#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */
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#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */
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#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */
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@ -77,6 +77,9 @@ CONFIG_ARCH_CHIP_LPC17XX=y
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CONFIG_ARCH_CORTEXM3=y
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CONFIG_ARCH_FAMILY="armv7-m"
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CONFIG_ARCH_CHIP="lpc17xx"
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# CONFIG_ARMV7M_USEBASEPRI is not set
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CONFIG_ARCH_HAVE_CMNVECTOR=y
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# CONFIG_ARMV7M_CMNVECTOR is not set
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CONFIG_ARCH_HAVE_MPU=y
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# CONFIG_ARMV7M_MPU is not set
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CONFIG_BOARD_LOOPSPERMSEC=8079
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@ -123,6 +126,7 @@ CONFIG_ARCH_FAMILY_LPC178X=y
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CONFIG_LPC17_MAINOSC=y
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CONFIG_LPC17_PLL0=y
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CONFIG_LPC17_PLL1=y
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# CONFIG_LPC17_EMC is not set
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# CONFIG_LPC17_ETHERNET is not set
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# CONFIG_LPC17_USBHOST is not set
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# CONFIG_LPC17_USBDEV is not set
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@ -269,6 +273,7 @@ CONFIG_DEV_CONSOLE=y
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CONFIG_SDCLONE_DISABLE=y
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# CONFIG_SCHED_WORKQUEUE is not set
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# CONFIG_SCHED_WAITPID is not set
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# CONFIG_SCHED_STARTHOOK is not set
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# CONFIG_SCHED_ATEXIT is not set
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# CONFIG_SCHED_ONEXIT is not set
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CONFIG_USER_ENTRYPOINT="ostest_main"
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@ -278,9 +283,7 @@ CONFIG_DISABLE_OS_API=y
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# CONFIG_DISABLE_PTHREAD is not set
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# CONFIG_DISABLE_SIGNALS is not set
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# CONFIG_DISABLE_MQUEUE is not set
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CONFIG_DISABLE_MOUNTPOINT=y
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CONFIG_DISABLE_ENVIRON=y
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CONFIG_DISABLE_POLL=y
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#
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# Signal Numbers
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@ -316,6 +319,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048
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#
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# Device Drivers
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#
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CONFIG_DISABLE_POLL=y
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CONFIG_DEV_NULL=y
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# CONFIG_DEV_ZERO is not set
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# CONFIG_LOOP is not set
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@ -379,11 +383,13 @@ CONFIG_UART0_2STOP=0
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#
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# File system configuration
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#
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CONFIG_DISABLE_MOUNTPOINT=y
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# CONFIG_FS_RAMMAP is not set
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#
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# System Logging
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#
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# CONFIG_SYSLOG_ENABLE is not set
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# CONFIG_SYSLOG is not set
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#
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@ -426,6 +432,8 @@ CONFIG_NUNGET_CHARS=2
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# CONFIG_EOL_IS_BOTH_CRLF is not set
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CONFIG_EOL_IS_EITHER_CRLF=y
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# CONFIG_LIBC_EXECFUNCS is not set
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CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
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CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
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# CONFIG_LIBC_STRERROR is not set
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# CONFIG_LIBC_PERROR_STDOUT is not set
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CONFIG_ARCH_LOWPUTC=y
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@ -457,7 +465,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
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#
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# CONFIG_EXAMPLES_BUTTONS is not set
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# CONFIG_EXAMPLES_CAN is not set
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# CONFIG_EXAMPLES_CDCACM is not set
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# CONFIG_EXAMPLES_COMPOSITE is not set
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# CONFIG_EXAMPLES_DHCPD is not set
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# CONFIG_EXAMPLES_ELF is not set
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@ -473,7 +480,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
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# CONFIG_EXAMPLES_MM is not set
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# CONFIG_EXAMPLES_MOUNT is not set
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# CONFIG_EXAMPLES_MODBUS is not set
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# CONFIG_EXAMPLES_NETTEST is not set
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# CONFIG_EXAMPLES_NSH is not set
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# CONFIG_EXAMPLES_NULL is not set
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# CONFIG_EXAMPLES_NX is not set
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@ -602,3 +608,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10
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# Sysinfo
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#
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# CONFIG_SYSTEM_SYSINFO is not set
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#
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# USB Monitor
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#
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329
configs/open1788/src/lpc17_nsh.c
Normal file
329
configs/open1788/src/lpc17_nsh.c
Normal file
@ -0,0 +1,329 @@
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/****************************************************************************
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* config/open1788/src/lpc17_nsh.c
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* arch/arm/src/board/lpc17_nsh.c
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*
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* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <debug.h>
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#include <errno.h>
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#include <nuttx/spi.h>
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#include <nuttx/mmcsd.h>
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#include <nuttx/usb/usbhost.h>
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#include "lpc17_gpio.h"
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#include "open1788.h"
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* PORT and SLOT number probably depend on the board configuration */
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#ifdef CONFIG_ARCH_BOARD_OPEN1788
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# define NSH_HAVEMMCSD 1
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# define NSH_HAVEUSBHOST 1
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# if !defined(CONFIG_NSH_MMCSDSPIPORTNO) || CONFIG_NSH_MMCSDSPIPORTNO != 1
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# error "The Open1788 MMC/SD is on SSP1"
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# undef CONFIG_NSH_MMCSDSPIPORTNO
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# define CONFIG_NSH_MMCSDSPIPORTNO 1
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# endif
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# if !defined(CONFIG_NSH_MMCSDSLOTNO) || CONFIG_NSH_MMCSDSLOTNO != 0
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# error "The Open1788 MMC/SD is only one slot (0)"
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# undef CONFIG_NSH_MMCSDSLOTNO
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# define CONFIG_NSH_MMCSDSLOTNO 0
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# endif
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# ifndef CONFIG_LPC17_SSP1
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# warning "CONFIG_LPC17_SSP1 is not enabled"
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# undef NSH_HAVEMMCSD
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# endif
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#else
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# error "Unrecognized board"
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# undef NSH_HAVEMMCSD
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# undef NSH_HAVEUSBHOST
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#endif
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/* Can't support MMC/SD features if mountpoints are disabled */
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#if defined(CONFIG_DISABLE_MOUNTPOINT)
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# undef NSH_HAVEMMCSD
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#endif
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#ifndef CONFIG_NSH_MMCSDMINOR
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# define CONFIG_NSH_MMCSDMINOR 0
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#endif
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/* USB Host */
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#ifdef CONFIG_USBHOST
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# ifndef CONFIG_LPC17_USBHOST
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# error "CONFIG_LPC17_USBHOST is not selected"
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# endif
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#endif
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#ifdef CONFIG_LPC17_USBHOST
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# ifndef CONFIG_USBHOST
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# warning "CONFIG_USBHOST is not selected"
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# endif
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#endif
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#if !defined(CONFIG_USBHOST) || !defined(CONFIG_LPC17_USBHOST)
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# undef NSH_HAVEUSBHOST
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#endif
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#ifdef NSH_HAVEUSBHOST
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# ifndef CONFIG_USBHOST_DEFPRIO
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# define CONFIG_USBHOST_DEFPRIO 50
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# endif
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# ifndef CONFIG_USBHOST_STACKSIZE
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# define CONFIG_USBHOST_STACKSIZE 1024
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# endif
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#endif
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/* Debug ********************************************************************/
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#ifdef CONFIG_CPP_HAVE_VARARGS
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# ifdef CONFIG_DEBUG
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# define message(...) lowsyslog(__VA_ARGS__)
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# else
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# define message(...) printf(__VA_ARGS__)
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# endif
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#else
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# ifdef CONFIG_DEBUG
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# define message lowsyslog
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# else
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# define message printf
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# endif
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef NSH_HAVEUSBHOST
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static struct usbhost_driver_s *g_drvr;
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nsh_waiter
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*
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* Description:
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* Wait for USB devices to be connected.
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*
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****************************************************************************/
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#ifdef NSH_HAVEUSBHOST
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static int nsh_waiter(int argc, char *argv[])
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{
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bool connected = false;
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int ret;
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message("nsh_waiter: Running\n");
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for (;;)
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{
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/* Wait for the device to change state */
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ret = DRVR_WAIT(g_drvr, connected);
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DEBUGASSERT(ret == OK);
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connected = !connected;
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message("nsh_waiter: %s\n", connected ? "connected" : "disconnected");
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/* Did we just become connected? */
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if (connected)
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{
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/* Yes.. enumerate the newly connected device */
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(void)DRVR_ENUMERATE(g_drvr);
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}
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}
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/* Keep the compiler from complaining */
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return 0;
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}
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#endif
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/****************************************************************************
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* Name: nsh_sdinitialize
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*
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* Description:
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* Initialize SPI-based microSD.
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*
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****************************************************************************/
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#ifdef NSH_HAVEMMCSD
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static int nsh_sdinitialize(void)
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{
|
||||
FAR struct spi_dev_s *ssp;
|
||||
int ret;
|
||||
|
||||
/* Enable power to the SD/MMC via a GPIO. LOW enables SD/MMC. */
|
||||
|
||||
lpc17_gpiowrite(OPEN1788_MMC_PWR, false);
|
||||
|
||||
/* Get the SSP port */
|
||||
|
||||
ssp = up_spiinitialize(CONFIG_NSH_MMCSDSPIPORTNO);
|
||||
if (!ssp)
|
||||
{
|
||||
message("nsh_archinitialize: Failed to initialize SSP port %d\n",
|
||||
CONFIG_NSH_MMCSDSPIPORTNO);
|
||||
ret = -ENODEV;
|
||||
goto errout;
|
||||
}
|
||||
|
||||
message("Successfully initialized SSP port %d\n",
|
||||
CONFIG_NSH_MMCSDSPIPORTNO);
|
||||
|
||||
/* Bind the SSP port to the slot */
|
||||
|
||||
ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR,
|
||||
CONFIG_NSH_MMCSDSLOTNO, ssp);
|
||||
if (ret < 0)
|
||||
{
|
||||
message("nsh_sdinitialize: "
|
||||
"Failed to bind SSP port %d to MMC/SD slot %d: %d\n",
|
||||
CONFIG_NSH_MMCSDSPIPORTNO,
|
||||
CONFIG_NSH_MMCSDSLOTNO, ret);
|
||||
goto errout;
|
||||
}
|
||||
|
||||
message("Successfuly bound SSP port %d to MMC/SD slot %d\n",
|
||||
CONFIG_NSH_MMCSDSPIPORTNO,
|
||||
CONFIG_NSH_MMCSDSLOTNO);
|
||||
return OK;
|
||||
|
||||
/* Disable power to the SD/MMC via a GPIO. HIGH disables SD/MMC. */
|
||||
|
||||
errout:
|
||||
lpc17_gpiowrite(OPEN1788_MMC_PWR, true);
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
# define nsh_sdinitialize() (OK)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nsh_usbhostinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SPI-based microSD.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef NSH_HAVEUSBHOST
|
||||
static int nsh_usbhostinitialize(void)
|
||||
{
|
||||
int pid;
|
||||
int ret;
|
||||
|
||||
/* First, register all of the class drivers needed to support the drivers
|
||||
* that we care about:
|
||||
*/
|
||||
|
||||
message("nsh_usbhostinitialize: Register class drivers\n");
|
||||
ret = usbhost_storageinit();
|
||||
if (ret != OK)
|
||||
{
|
||||
message("nsh_usbhostinitialize: Failed to register the mass storage class\n");
|
||||
}
|
||||
|
||||
/* Then get an instance of the USB host interface */
|
||||
|
||||
message("nsh_usbhostinitialize: Initialize USB host\n");
|
||||
g_drvr = usbhost_initialize(0);
|
||||
if (g_drvr)
|
||||
{
|
||||
/* Start a thread to handle device connection. */
|
||||
|
||||
message("nsh_usbhostinitialize: Start nsh_waiter\n");
|
||||
|
||||
#ifndef CONFIG_CUSTOM_STACK
|
||||
pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO,
|
||||
CONFIG_USBHOST_STACKSIZE,
|
||||
(main_t)nsh_waiter, (FAR char * const *)NULL);
|
||||
#else
|
||||
pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO,
|
||||
(main_t)nsh_waiter, (FAR char * const *)NULL);
|
||||
#endif
|
||||
return pid < 0 ? -ENOEXEC : OK;
|
||||
}
|
||||
return -ENODEV;
|
||||
}
|
||||
#else
|
||||
# define nsh_usbhostinitialize() (OK)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nsh_archinitialize
|
||||
*
|
||||
* Description:
|
||||
* Perform architecture specific initialization
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int nsh_archinitialize(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Initialize SPI-based microSD */
|
||||
|
||||
ret = nsh_sdinitialize();
|
||||
if (ret == OK)
|
||||
{
|
||||
/* Initialize USB host */
|
||||
|
||||
ret = nsh_usbhostinitialize();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user