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risv-v/esp32c6: disable custom optimize level temporary

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This is a workaround commit to temporarily reduce the flash usage of
esp32c6 to avoid ci failure, Since I am not familiar with esptool,
and this issue cannot be reproduced in the local environment,
so I temporarily turn off related optimizations to save flash size.

esptool error log:
-----------------------------------------
| MKIMAGE: ESP32-C6 binary
| esptool.py --chip esp32c6 elf2image --flash_mode dio --flash_size "4MB" -o nuttx.bin nuttx
| esptool.py v4.5.1
| Creating esp32c6 image...
| Merged 1 ELF section
|
| A fatal error occurred: Segment loaded at 0x42010c08 lands in same 64KB flash mapping as segment loaded at 0x42010020. Can't generate binary. Suggest changing linker script or ELF to merge sections.
| make: *** [tools/Unix.mk:527: nuttx] Error 2
| make: Target 'all' not remade because of errors.
-----------------------------------------

Signed-off-by: chao an <anchao@xiaomi.com>
This commit is contained in:
chao an 2023-04-13 18:27:53 +08:00 committed by Xiang Xiao
parent 8df0a4d9ef
commit b94cc5ff92
1 changed files with 0 additions and 2 deletions
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boards/risc-v/esp32c6/esp32c6-devkit/configs/coremark/defconfig
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@ -17,8 +17,6 @@ CONFIG_ARCH_INTERRUPTSTACK=1536
CONFIG_ARCH_RISCV=y
CONFIG_BENCHMARK_COREMARK=y
CONFIG_BOARD_LOOPSPERMSEC=15000
CONFIG_DEBUG_CUSTOMOPT=y
CONFIG_DEBUG_OPTLEVEL="-O3"
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=3072
CONFIG_INIT_ENTRYPOINT="coremark_main"