Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/imxrt/: Fix complaints from tools/nxstyle in new LCD files.
Use tools/lowhex to convert hexadecimal constants to lower case.
Use tools/rmcr to review white space at the end of lines.
Author: Johannes <nivus.entwicklung@gmail.com>
arch/arm/src/imxrt and configs/imxrt1050-evk: Adds framebuffer support for thje i.MXRT 1050. Includdd DCD initialization for SDRAM to provide space for the framebufer. External code I used/ported is from NXP and is BSD 3-clause license.
This commit is contained in:
Johannes
Gregory Nutt
parent
6409641ab4
commit
b95fadcaa6
@ -25,7 +25,7 @@ config ARCH_CHIP_MIMXRT1052DVL6A
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select ARCH_FAMILY_MXRT105xDVL6A
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config ARCH_CHIP_MIMXRT1052CVL5A
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bool "MIMXRT1052DVL6A"
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bool "MIMXRT1052DVL5A"
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select ARCH_FAMILY_MIMXRT1052CVL5A
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config ARCH_CHIP_MIMXRT1061DVL6A
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@ -71,6 +71,7 @@ config ARCH_FAMILY_IMXRT105x
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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select ARMV7M_HAVE_DTCM
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select IMXRT_HAVE_LCD
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config ARCH_FAMILY_MXRT106xDVL6A
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bool
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@ -96,6 +97,7 @@ config ARCH_FAMILY_IMXRT106x
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select ARMV7M_HAVE_ITCM
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select ARMV7M_HAVE_DTCM
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select IMXRT_HIGHSPEED_GPIO
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select IMXRT_HAVE_LCD
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# Peripheral support
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@ -115,6 +117,10 @@ config IMXRT_HIGHSPEED_GPIO
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bool
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default n
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config IMXRT_HAVE_LCD
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bool
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default n
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menu "i.MX RT Peripheral Selection"
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config IMXRT_EDMA
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@ -129,6 +135,11 @@ config IMXRT_ENET
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select ARCH_PHY_INTERRUPT
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select ARCH_HAVE_NETDEV_STATISTICS
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config IMXRT_LCD
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bool "LCD controller"
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default n
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depends on IMXRT_HAVE_LCD
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menu "FlexIO Peripherals"
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endmenu # FlexIO Peripherals
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@ -730,5 +741,151 @@ config IMXRT_RTC_MAGIC
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Value used as Magic to determine if the RTC is already setup
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endmenu
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menu "LCD Configuration"
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depends on IMXRT_LCD
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config IMXRT_LCD_VIDEO_PLL_FREQ
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int "Video PLL Frequency"
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default 92000000
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range 41500000 1300000000
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---help---
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Frequency of Video PLL.
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config IMXRT_LCD_VRAMBASE
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hex "Video RAM base address"
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default 0x80000000
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---help---
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Base address of the video RAM frame buffer.
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Default: SDRAM
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config IMXRT_LCD_REFRESH_FREQ
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int "LCD refesh rate (Hz)"
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default 60
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---help---
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LCD refesh rate (Hz)
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config IMXRT_LCD_BACKLIGHT
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bool "Enable backlight"
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default y
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---help---
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Enable backlight support. If IMXRT_LCD_BACKLIGHT is selected, then
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the board-specific logic must provide this IMXRT_backlight()
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interface so that the LCD driver can turn the backlight on and off
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as necessary. You should select this option and implement
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IMXRT_backlight() if your board provides GPIO control over the
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backlight. This interface provides only ON/OFF control of the
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backlight. If you want finer control over the backlight level (for
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example, using PWM), then this interface would need to be extended.
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choice
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prompt "Input Bits per pixel"
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default IMXRT_LCD_INPUT_BPP16
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config IMXRT_LCD_INPUT_BPP8_LUT
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bool "8 BPP Color Map"
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select FB_CMAP
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config IMXRT_LCD_INPUT_BPP8
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bool "8 BPP RGB_332"
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config IMXRT_LCD_INPUT_BPP15
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bool "16 BPP RGB_555"
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config IMXRT_LCD_INPUT_BPP16
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bool "16 BPP RGB_565"
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config IMXRT_LCD_INPUT_BPP24
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bool "24 BPP RGB_888"
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config IMXRT_LCD_INPUT_BPP32
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bool "32 BPP RGB_0888"
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endchoice
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config IMXRT_LCD_BGR
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bool "Blue-Green-Red color order"
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default n
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---help---
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This option selects BGR color order vs. default RGB
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choice
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prompt "Output Bus width"
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default IMXRT_LCD_OUTPUT_16
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config IMXRT_LCD_OUTPUT_8
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bool "8 Bit LCD Bus"
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config IMXRT_LCD_OUTPUT_16
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bool "16 Bit LCD Bus"
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config IMXRT_LCD_OUTPUT_18
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bool "18 Bit LCD Bus"
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config IMXRT_LCD_OUTPUT_24
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bool "24 Bit LCD Bus"
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endchoice
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config IMXRT_LCD_BACKCOLOR
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hex "Initial background color"
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default 0x0
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---help---
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Initial background color
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config IMXRT_LCD_HWIDTH
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int "Display width (pixels)"
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default 480
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---help---
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Horizontal width the display in pixels
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config IMXRT_LCD_HPULSE
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int "Horizontal pulse"
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default 41
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config IMXRT_LCD_HFRONTPORCH
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int "Horizontal front porch"
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default 4
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config IMXRT_LCD_HBACKPORCH
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int "Horizontal back porch"
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default 8
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config IMXRT_LCD_VHEIGHT
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int "Display height (rows)"
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default 272
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---help---
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Vertical height of the display in rows
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config IMXRT_LCD_VPULSE
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int "Vertical pulse"
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default 10
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config IMXRT_LCD_VFRONTPORCH
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int "Vertical front porch"
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default 4
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config IMXRT_LCD_VBACKPORCH
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int "Vertical back porch"
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default 2
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config IMXRT_VSYNC_ACTIVE_HIGH
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bool "V-sync active high"
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default n
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config IMXRT_HSYNC_ACTIVE_HIGH
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bool "H-sync active high"
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default n
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config IMXRT_DATAEN_ACTIVE_HIGH
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bool "Data enable active high"
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default y
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config IMXRT_DATA_RISING_EDGE
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bool "Data clock rising edge"
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default y
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endmenu # LCD Configuration
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endif # ARCH_CHIP_IMXRT
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@ -130,6 +130,10 @@ ifdef CONFIG_IMXRT_USDHC
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CHIP_CSRCS += imxrt_usdhc.c
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endif
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ifeq ($(CONFIG_IMXRT_LCD),y)
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CHIP_CSRCS += imxrt_lcd.c
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endif
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ifeq ($(CONFIG_IMXRT_SNVS_LPSRTC),y)
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CHIP_CSRCS += imxrt_lpsrtc.c
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CHIP_CSRCS += imxrt_hprtc.c
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@ -574,34 +574,37 @@
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/* LCD */
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#define GPIO_LCD_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX))
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#define GPIO_LCD_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX))
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#define GPIO_LCD_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX))
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#define GPIO_LCD_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX))
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#define GPIO_LCD_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX))
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#define GPIO_LCD_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX))
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#define GPIO_LCD_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX))
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#define GPIO_LCD_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX))
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#define GPIO_LCD_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX))
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#define GPIO_LCD_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX))
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#define GPIO_LCD_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX))
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#define GPIO_LCD_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX))
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#define GPIO_LCD_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX))
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#define GPIO_LCD_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX))
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#define GPIO_LCD_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX))
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#define GPIO_LCD_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX))
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#define GPIO_LCD_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX))
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#define GPIO_LCD_DATA16 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX))
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#define GPIO_LCD_DATA17 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX))
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#define GPIO_LCD_DATA18 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX))
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#define GPIO_LCD_DATA19 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX))
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#define GPIO_LCD_DATA20 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX))
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#define GPIO_LCD_DATA21 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX))
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#define GPIO_LCD_DATA22 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX))
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#define GPIO_LCD_DATA23 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX))
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#define GPIO_LCD_ENABLE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX))
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#define GPIO_LCD_HSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX))
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#define GPIO_LCD_VSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX))
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#define IOMUX_LCD (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \
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IOMUX_SLEW_SLOW | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER)
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#define GPIO_LCD_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA16 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA17 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA18 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA19 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA20 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA21 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA22 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_DATA23 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_ENABLE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_HSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX) | IOMUX_LCD)
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#define GPIO_LCD_VSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX) | IOMUX_LCD)
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/* Low Power Inter-Integrated Circuit (LPI2C) */
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@ -1089,55 +1089,55 @@
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/* Miscellaneous Register 2 */
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#define CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */
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#define CCM_ANALOG_MISC1_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT)
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# define CCM_ANALOG_MISC1_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT)
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# define CCM_ANALOG_MISC1_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT)
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#define CCM_ANALOG_MISC1_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */
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#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */
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#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)
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# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)
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# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)
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#define CCM_ANALOG_MISC2_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */
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/* Bit 4: Reserved */
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#define CCM_ANALOG_MISC1_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */
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#define CCM_ANALOG_MISC1_REG0_OK (1 << 6) /* Bit 6: ARM supply */
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#define CCM_ANALOG_MISC1_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */
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#define CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */
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#define CCM_ANALOG_MISC1_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT)
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# define CCM_ANALOG_MISC1_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT)
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# define CCM_ANALOG_MISC1_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT)
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#define CCM_ANALOG_MISC1_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */
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#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */
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#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */
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#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */
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#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */
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#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
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# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
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# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
|
||||
#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */
|
||||
/* Bit 12: Reserved */
|
||||
#define CCM_ANALOG_MISC1_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */
|
||||
#define CCM_ANALOG_MISC1_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */
|
||||
#define CCM_ANALOG_MISC1_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */
|
||||
#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */
|
||||
#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */
|
||||
#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */
|
||||
|
||||
#define CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */
|
||||
#define CCM_ANALOG_MISC1_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT)
|
||||
#define CCM_ANALOG_MISC1_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */
|
||||
#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */
|
||||
#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
|
||||
#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */
|
||||
/* Bit 20: Reserved */
|
||||
#define CCM_ANALOG_MISC1_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */
|
||||
#define CCM_ANALOG_MISC1_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */
|
||||
#define CCM_ANALOG_MISC1_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */
|
||||
#define CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */
|
||||
#define CCM_ANALOG_MISC1_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT)
|
||||
#define CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */
|
||||
#define CCM_ANALOG_MISC1_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT)
|
||||
#define CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */
|
||||
#define CCM_ANALOG_MISC1_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT)
|
||||
#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */
|
||||
#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */
|
||||
#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */
|
||||
#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */
|
||||
#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
|
||||
#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */
|
||||
#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
|
||||
#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */
|
||||
#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
|
||||
|
||||
#define CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */
|
||||
#define CCM_ANALOG_MISC1_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT)
|
||||
# define CCM_ANALOG_MISC1_VIDEO_DIV(n) ((uint32_t)(0) << CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT)
|
||||
#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */
|
||||
#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)
|
||||
# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H */
|
||||
|
||||
1709
arch/arm/src/imxrt/chip/imxrt_lcd.h
Normal file
1709
arch/arm/src/imxrt/chip/imxrt_lcd.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -46,8 +46,182 @@
|
||||
#include "chip/imxrt_ccm.h"
|
||||
#include "chip/imxrt_dcdc.h"
|
||||
#include "imxrt_clockconfig.h"
|
||||
#include "imxrt_lcd.h"
|
||||
#include "chip/imxrt_memorymap.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define VIDEO_PLL_MIN_FREQ 650000000
|
||||
#define OSC24_FREQ 24000000
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lcd_clockconfig
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LCD
|
||||
static void imxrt_lcd_clockconfig(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t reg2;
|
||||
|
||||
int post;
|
||||
int pre;
|
||||
|
||||
uint32_t numerator;
|
||||
uint32_t denominator;
|
||||
uint32_t post_divider;
|
||||
uint32_t pre_divider;
|
||||
uint32_t loop_divider;
|
||||
uint32_t target_freq;
|
||||
uint32_t freq_error;
|
||||
|
||||
target_freq = (CONFIG_IMXRT_LCD_HWIDTH +
|
||||
CONFIG_IMXRT_LCD_HPULSE +
|
||||
CONFIG_IMXRT_LCD_HFRONTPORCH +
|
||||
CONFIG_IMXRT_LCD_HBACKPORCH) *
|
||||
(CONFIG_IMXRT_LCD_VHEIGHT +
|
||||
CONFIG_IMXRT_LCD_VPULSE +
|
||||
CONFIG_IMXRT_LCD_VFRONTPORCH +
|
||||
CONFIG_IMXRT_LCD_VBACKPORCH) *
|
||||
CONFIG_IMXRT_LCD_REFRESH_FREQ;
|
||||
|
||||
for (post_divider = 1; post_divider < 16; post_divider <<= 1)
|
||||
{
|
||||
if (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider >= VIDEO_PLL_MIN_FREQ)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
loop_divider = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) / OSC24_FREQ;
|
||||
numerator = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) -
|
||||
(loop_divider * OSC24_FREQ);
|
||||
denominator = OSC24_FREQ;
|
||||
|
||||
/* Bypass PLL first */
|
||||
|
||||
modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO,
|
||||
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK,
|
||||
CCM_ANALOG_PLL_VIDEO_BYPASS |
|
||||
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M);
|
||||
|
||||
putreg32(CCM_ANALOG_PLL_VIDEO_NUM_A(numerator),
|
||||
IMXRT_CCM_ANALOG_PLL_VIDEO_NUM);
|
||||
putreg32(CCM_ANALOG_PLL_VIDEO_DENOM_B(denominator),
|
||||
IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM);
|
||||
|
||||
/* Set post divider:
|
||||
*
|
||||
* ------------------------------------------------------------------------
|
||||
* | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 1 | 2 | 0 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 2 | 1 | 0 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 4 | 2 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 8 | 1 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 16 | 0 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
reg = getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO);
|
||||
reg &= ~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK |
|
||||
CCM_ANALOG_PLL_VIDEO_POWERDOWN);
|
||||
reg |= CCM_ANALOG_PLL_VIDEO_ENABLE |
|
||||
CCM_ANALOG_PLL_VIDEO_DIV_SELECT(loop_divider);
|
||||
|
||||
reg2 = getreg32(IMXRT_CCM_ANALOG_MISC2);
|
||||
reg2 &= ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK;
|
||||
|
||||
switch (post_divider)
|
||||
{
|
||||
case 16:
|
||||
reg |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4;
|
||||
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2;
|
||||
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1;
|
||||
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2;
|
||||
reg2 |= 0;
|
||||
break;
|
||||
|
||||
default:
|
||||
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1;
|
||||
reg2 |= 0;
|
||||
break;
|
||||
}
|
||||
|
||||
putreg32(reg, IMXRT_CCM_ANALOG_PLL_VIDEO);
|
||||
|
||||
putreg32(reg2, IMXRT_CCM_ANALOG_MISC2);
|
||||
|
||||
while ((getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO) &
|
||||
CCM_ANALOG_PLL_VIDEO_LOCK) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Disable Bypass */
|
||||
|
||||
modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO,
|
||||
CCM_ANALOG_PLL_VIDEO_BYPASS,
|
||||
0);
|
||||
|
||||
freq_error = IMXRT_LCD_VIDEO_PLL_FREQ;
|
||||
pre_divider = 0;
|
||||
post_divider = 0;
|
||||
|
||||
for (post = 0; post < 8; post++)
|
||||
{
|
||||
for (pre = 0; pre < 8; pre++)
|
||||
{
|
||||
int32_t temp_error;
|
||||
temp_error = labs((post + 1) * (pre + 1) * target_freq -
|
||||
IMXRT_LCD_VIDEO_PLL_FREQ);
|
||||
if (temp_error < freq_error)
|
||||
{
|
||||
pre_divider = pre;
|
||||
post_divider = post;
|
||||
freq_error = temp_error;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Select PLL5 as LCD Clock and set Pre divider. */
|
||||
|
||||
modifyreg32(IMXRT_CCM_CSCDR2,
|
||||
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK | CCM_CSCDR2_LCDIF_PRED_MASK,
|
||||
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 | CCM_CSCDR2_LCDIF_PRED(pre_divider));
|
||||
|
||||
/* Set Post divider. */
|
||||
|
||||
modifyreg32(IMXRT_CCM_CBCMR, CCM_CBCMR_LCDIF_PODF_MASK,
|
||||
CCM_CBCMR_LCDIF_PODF(post_divider));
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -91,7 +265,7 @@ void imxrt_clockconfig(void)
|
||||
|
||||
/* Wait handshake */
|
||||
|
||||
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) == 1)
|
||||
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
@ -104,7 +278,8 @@ void imxrt_clockconfig(void)
|
||||
|
||||
/* Init Arm PLL1 */
|
||||
|
||||
reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) | CCM_ANALOG_PLL_ARM_ENABLE;
|
||||
reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) |
|
||||
CCM_ANALOG_PLL_ARM_ENABLE;
|
||||
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
|
||||
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
|
||||
{
|
||||
@ -112,12 +287,19 @@ void imxrt_clockconfig(void)
|
||||
|
||||
/* Init Sys PLL2 */
|
||||
|
||||
reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) | CCM_ANALOG_PLL_SYS_ENABLE;
|
||||
reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) |
|
||||
CCM_ANALOG_PLL_SYS_ENABLE;
|
||||
putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
|
||||
while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IMXRT_LCD
|
||||
/* Init Video PLL5 */
|
||||
|
||||
imxrt_lcd_clockconfig();
|
||||
#endif
|
||||
|
||||
/* TODO: other pll configs */
|
||||
|
||||
/* Set Dividers */
|
||||
@ -163,7 +345,7 @@ void imxrt_clockconfig(void)
|
||||
|
||||
/* Wait handshake */
|
||||
|
||||
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) == 1)
|
||||
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
@ -196,7 +378,7 @@ void imxrt_clockconfig(void)
|
||||
reg |= CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M;
|
||||
putreg32(reg, IMXRT_CCM_CSCDR2);
|
||||
|
||||
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) == 1)
|
||||
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
@ -207,7 +389,7 @@ void imxrt_clockconfig(void)
|
||||
reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5);
|
||||
putreg32(reg, IMXRT_CCM_CSCDR2);
|
||||
|
||||
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) == 1)
|
||||
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
742
arch/arm/src/imxrt/imxrt_lcd.c
Normal file
742
arch/arm/src/imxrt/imxrt_lcd.c
Normal file
@ -0,0 +1,742 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/imxrt/imxrt_lcd.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017, NXP Semiconductors, Inc.
|
||||
* Author: Johannes Schock (Port)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "imxrt_lcd.h"
|
||||
#include "imxrt_periphclks.h"
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/video/fb.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "imxrt_gpio.h"
|
||||
#include "imxrt_iomuxc.h"
|
||||
|
||||
#include "chip/imxrt_pinmux.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define IMXRT_LCD_CLK_PER_LINE \
|
||||
(CONFIG_IMXRT_LCD_HWIDTH + CONFIG_IMXRT_LCD_HPULSE + \
|
||||
CONFIG_IMXRT_LCD_HFRONTPORCH + CONFIG_IMXRT_LCD_HBACKPORCH)
|
||||
#define IMXRT_LCD_LINES_PER_FRAME \
|
||||
(CONFIG_IMXRT_LCD_VHEIGHT + CONFIG_IMXRT_LCD_VPULSE + \
|
||||
CONFIG_IMXRT_LCD_VFRONTPORCH + CONFIG_IMXRT_LCD_VBACKPORCH)
|
||||
#define IMXRT_LCD_PIXEL_CLOCK \
|
||||
(IMXRT_LCD_CLK_PER_LINE * IMXRT_LCD_LINES_PER_FRAME * \
|
||||
CONFIG_IMXRT_LCD_REFRESH_FREQ)
|
||||
|
||||
/* Framebuffer characteristics in bytes */
|
||||
|
||||
#define IMXRT_STRIDE ((CONFIG_IMXRT_LCD_HWIDTH * IMXRT_BPP + 7) / 8)
|
||||
#define IMXRT_FBSIZE (IMXRT_STRIDE * CONFIG_IMXRT_LCD_VHEIGHT)
|
||||
|
||||
/* Delays */
|
||||
|
||||
#define IMXRT_LCD_RESET_DELAY (0x100)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/* Get information about the video controller configuration and the
|
||||
* configuration of each color plane.
|
||||
*/
|
||||
|
||||
static int imxrt_getvideoinfo(FAR struct fb_vtable_s *vtable,
|
||||
FAR struct fb_videoinfo_s *vinfo);
|
||||
static int imxrt_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno,
|
||||
FAR struct fb_planeinfo_s *pinfo);
|
||||
|
||||
/* The following is provided only if the video hardware supports RGB color
|
||||
* mapping
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_FB_CMAP
|
||||
static int imxrt_getcmap(FAR struct fb_vtable_s *vtable,
|
||||
FAR struct fb_cmap_s *cmap);
|
||||
static int imxrt_putcmap(FAR struct fb_vtable_s *vtable,
|
||||
FAR const struct fb_cmap_s *cmap);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FB_HWCURSOR
|
||||
# error "Cursor control not supported by this driver"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This structure describes the video controller */
|
||||
|
||||
static const struct fb_videoinfo_s g_videoinfo =
|
||||
{
|
||||
.fmt = IMXRT_COLOR_FMT,
|
||||
.xres = CONFIG_IMXRT_LCD_HWIDTH,
|
||||
.yres = CONFIG_IMXRT_LCD_VHEIGHT,
|
||||
.nplanes = 1,
|
||||
};
|
||||
|
||||
/* This structure describes the single color plane */
|
||||
|
||||
static const struct fb_planeinfo_s g_planeinfo =
|
||||
{
|
||||
.fbmem = (FAR void *)CONFIG_IMXRT_LCD_VRAMBASE,
|
||||
.fblen = IMXRT_FBSIZE,
|
||||
.stride = IMXRT_STRIDE,
|
||||
.display = 0,
|
||||
.bpp = IMXRT_BPP,
|
||||
};
|
||||
|
||||
struct pixel_format_reg
|
||||
{
|
||||
uint32_t regCtrl; /* Value of register CTRL. */
|
||||
uint32_t regCtrl1; /* Value of register CTRL1. */
|
||||
};
|
||||
|
||||
#if defined (CONFIG_IMXRT_LCD_INPUT_BPP8) || defined (CONFIG_IMXRT_LCD_INPUT_BPP8_LUT)
|
||||
static const struct pixel_format_reg pixelFormat =
|
||||
{
|
||||
/* Register CTRL. */
|
||||
|
||||
LCDIF_CTRL_WORD_LENGTH(1U),
|
||||
|
||||
/* Register CTRL1. */
|
||||
|
||||
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0fU)
|
||||
};
|
||||
const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(1);
|
||||
|
||||
#else
|
||||
|
||||
# if defined (CONFIG_IMXRT_LCD_INPUT_BPP15)
|
||||
static const struct pixel_format_reg pixelFormat =
|
||||
{
|
||||
/* Register CTRL. */
|
||||
|
||||
LCDIF_CTRL_WORD_LENGTH(0U) | LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK,
|
||||
|
||||
/* Register CTRL1. */
|
||||
|
||||
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0fU)
|
||||
};
|
||||
# elif defined (CONFIG_IMXRT_LCD_INPUT_BPP16)
|
||||
static const struct pixel_format_reg pixelFormat =
|
||||
{
|
||||
/* Register CTRL. */
|
||||
|
||||
LCDIF_CTRL_WORD_LENGTH(0U),
|
||||
|
||||
/* Register CTRL1. */
|
||||
|
||||
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0fU)
|
||||
};
|
||||
# elif defined (CONFIG_IMXRT_LCD_INPUT_BPP24)
|
||||
static const struct pixel_format_reg pixelFormat =
|
||||
{
|
||||
/* Register CTRL. 24-bit. */
|
||||
|
||||
LCDIF_CTRL_WORD_LENGTH(3U),
|
||||
|
||||
/* Register CTRL1. */
|
||||
|
||||
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0fU)
|
||||
};
|
||||
# elif defined (CONFIG_IMXRT_LCD_INPUT_BPP32)
|
||||
static const struct pixel_format_reg pixelFormat =
|
||||
{
|
||||
/* Register CTRL. 24-bit. */
|
||||
|
||||
LCDIF_CTRL_WORD_LENGTH(3U),
|
||||
|
||||
/* Register CTRL1. */
|
||||
|
||||
LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U)
|
||||
};
|
||||
# endif
|
||||
|
||||
# if defined (CONFIG_IMXRT_LCD_OUTPUT_8)
|
||||
const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(1);
|
||||
# elif defined (CONFIG_IMXRT_LCD_OUTPUT_16)
|
||||
const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(0);
|
||||
# elif defined (CONFIG_IMXRT_LCD_OUTPUT_18)
|
||||
const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(2);
|
||||
# elif defined (CONFIG_IMXRT_LCD_OUTPUT_24)
|
||||
const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(3);
|
||||
# endif
|
||||
|
||||
#endif
|
||||
|
||||
/* The framebuffer object -- There is no private state information in this
|
||||
* framebuffer driver.
|
||||
*/
|
||||
|
||||
struct fb_vtable_s g_fbobject =
|
||||
{
|
||||
.getvideoinfo = imxrt_getvideoinfo,
|
||||
.getplaneinfo = imxrt_getplaneinfo,
|
||||
#ifdef CONFIG_FB_CMAP
|
||||
.getcmap = imxrt_getcmap,
|
||||
.putcmap = imxrt_putcmap,
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_getvideoinfo
|
||||
****************************************************************************/
|
||||
|
||||
static int imxrt_getvideoinfo(FAR struct fb_vtable_s *vtable,
|
||||
FAR struct fb_videoinfo_s *vinfo)
|
||||
{
|
||||
lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo);
|
||||
if (vtable && vinfo)
|
||||
{
|
||||
memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s));
|
||||
return OK;
|
||||
}
|
||||
|
||||
lcderr("ERROR: Returning EINVAL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_getplaneinfo
|
||||
****************************************************************************/
|
||||
|
||||
static int imxrt_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno,
|
||||
FAR struct fb_planeinfo_s *pinfo)
|
||||
{
|
||||
lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo);
|
||||
if (vtable && planeno == 0 && pinfo)
|
||||
{
|
||||
memcpy(pinfo, &g_planeinfo, sizeof(struct fb_planeinfo_s));
|
||||
return OK;
|
||||
}
|
||||
|
||||
lcderr("ERROR: Returning EINVAL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_getcmap
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_FB_CMAP
|
||||
static int imxrt_getcmap(FAR struct fb_vtable_s *vtable,
|
||||
FAR struct fb_cmap_s *cmap)
|
||||
{
|
||||
uint32_t n;
|
||||
uint32_t reg;
|
||||
|
||||
lcdinfo("vtable=%p cmap=%p first=%d len=%d\n",
|
||||
vtable, cmap, cmap->first, cmap->len);
|
||||
|
||||
DEBUGASSERT(vtable && cmap);
|
||||
|
||||
/* Only has 256 entries. */
|
||||
|
||||
if (cmap->first + cmap->len > IMXRT_LCDIF_LUT_ENTRY_NUM)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
putreg32(cmap->first, IMXRT_LCDIF_LUT0_ADDR);
|
||||
|
||||
for (n = 0; n < cmap->len; n++)
|
||||
{
|
||||
reg = getreg32(IMXRT_LCDIF_LUT0_DATA);
|
||||
|
||||
#if defined (CONFIG_IMXRT_LCD_OUTPUT_24)
|
||||
cmap->red[n] = (reg >> 16) & 0xff;
|
||||
cmap->green[n] = (reg >> 8) & 0xff;
|
||||
cmap->blue[n] = (reg >> 0) & 0xff;
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_18)
|
||||
cmap->red[n] = (reg >> 10) & 0xfc;
|
||||
cmap->green[n] = (reg >> 4) & 0xfc;
|
||||
cmap->blue[n] = (reg << 2) & 0xfc;
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_16)
|
||||
cmap->red[n] = (reg >> 8) & 0xf8;
|
||||
cmap->green[n] = (reg >> 3) & 0xfc;
|
||||
cmap->blue[n] = (reg << 3) & 0xf8;
|
||||
#endif
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_putcmap
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_FB_CMAP
|
||||
static int imxrt_putcmap(FAR struct fb_vtable_s *vtable,
|
||||
FAR const struct fb_cmap_s *cmap)
|
||||
{
|
||||
uint32_t n;
|
||||
|
||||
lcdinfo("vtable=%p cmap=%p first=%d len=%d\n",
|
||||
vtable, cmap, cmap->first, cmap->len);
|
||||
|
||||
DEBUGASSERT(vtable && cmap);
|
||||
|
||||
/* Only has 256 entries. */
|
||||
|
||||
if (cmap->first + cmap->len > IMXRT_LCDIF_LUT_ENTRY_NUM)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
putreg32(cmap->first, IMXRT_LCDIF_LUT0_ADDR);
|
||||
|
||||
for (n = 0; n < cmap->len; n++)
|
||||
{
|
||||
|
||||
#if defined (CONFIG_IMXRT_LCD_OUTPUT_24)
|
||||
putreg32((uint32_t)0xff000000 |
|
||||
((uint32_t)cmap->red[n] << 16) |
|
||||
((uint32_t)cmap->green[n] << 8) |
|
||||
((uint32_t)cmap->blue[n] << 0),
|
||||
IMXRT_LCDIF_LUT0_DATA);
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_18)
|
||||
putreg32((uint32_t)0xfffc0000 |
|
||||
(((uint32_t)cmap->red[n] & 0xfc) << 10) |
|
||||
(((uint32_t)cmap->green[n] & 0xfc) << 4) |
|
||||
(((uint32_t)cmap->blue[n] & 0xfc) >> 2),
|
||||
IMXRT_LCDIF_LUT0_DATA);
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_16)
|
||||
putreg32((uint32_t)0xffff0000 |
|
||||
(((uint32_t)cmap->red[n] & 0xf8) << 8) |
|
||||
(((uint32_t)cmap->green[n] & 0xfc) << 3) |
|
||||
(((uint32_t)cmap->blue[n] & 0xf8) >> 3),
|
||||
IMXRT_LCDIF_LUT0_DATA);
|
||||
#endif
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lcd_reset
|
||||
****************************************************************************/
|
||||
|
||||
static void imxrt_lcdreset(void)
|
||||
{
|
||||
volatile uint32_t i = IMXRT_LCD_RESET_DELAY;
|
||||
|
||||
/* Disable the clock gate. */
|
||||
|
||||
putreg32(LCDIF_CTRL_CLKGATE_MASK, IMXRT_LCDIF_CTRL_CLR);
|
||||
|
||||
/* Confirm the clock gate is disabled. */
|
||||
|
||||
while ((getreg32(IMXRT_LCDIF_CTRL) & LCDIF_CTRL_CLKGATE_MASK) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Reset the block. */
|
||||
|
||||
putreg32(LCDIF_CTRL_SFTRST_MASK, IMXRT_LCDIF_CTRL_SET);
|
||||
|
||||
/* Confirm the reset bit is set. */
|
||||
|
||||
while ((getreg32(IMXRT_LCDIF_CTRL) & LCDIF_CTRL_SFTRST_MASK) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Delay for the reset. */
|
||||
|
||||
while (i--)
|
||||
{
|
||||
}
|
||||
|
||||
/* Bring the module out of reset. */
|
||||
|
||||
putreg32(LCDIF_CTRL_SFTRST_MASK, IMXRT_LCDIF_CTRL_CLR);
|
||||
|
||||
/* Disable the clock gate. */
|
||||
|
||||
putreg32(LCDIF_CTRL_CLKGATE_MASK, IMXRT_LCDIF_CTRL_CLR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_fbinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the framebuffer video hardware associated with the display.
|
||||
*
|
||||
* Input Parameters:
|
||||
* display - In the case of hardware with multiple displays, this
|
||||
* specifies the display. Normally this is zero.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero is returned on success; a negated errno value is returned on any
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_fbinitialize(int display)
|
||||
{
|
||||
|
||||
#if defined (CONFIG_IMXRT_LCD_INPUT_BPP8_LUT) || defined (CONFIG_IMXRT_LCD_INPUT_BPP8)
|
||||
uint32_t n;
|
||||
#endif
|
||||
|
||||
/* Configure pins
|
||||
*
|
||||
* LCD panel data. Pins used depend on the panel configuration:
|
||||
*/
|
||||
|
||||
lcdinfo("Configuring pins\n");
|
||||
|
||||
#if defined(CONFIG_IMXRT_LCD_OUTPUT_24)
|
||||
|
||||
imxrt_config_gpio(GPIO_LCD_DATA23);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA22);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA21);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA20);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA19);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA18);
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LCD_OUTPUT_24) || \
|
||||
defined(CONFIG_IMXRT_LCD_OUTPUT_18)
|
||||
|
||||
imxrt_config_gpio(GPIO_LCD_DATA17);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA16);
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LCD_OUTPUT_24) || \
|
||||
defined(CONFIG_IMXRT_LCD_OUTPUT_18) || \
|
||||
defined(CONFIG_IMXRT_LCD_OUTPUT_16)
|
||||
|
||||
imxrt_config_gpio(GPIO_LCD_DATA15);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA14);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA13);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA12);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA11);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA10);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA09);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA08);
|
||||
|
||||
#endif
|
||||
|
||||
imxrt_config_gpio(GPIO_LCD_DATA07);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA06);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA05);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA04);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA03);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA02);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA01);
|
||||
imxrt_config_gpio(GPIO_LCD_DATA00);
|
||||
|
||||
/* Other pins */
|
||||
|
||||
imxrt_config_gpio(GPIO_LCD_ENABLE);
|
||||
imxrt_config_gpio(GPIO_LCD_HSYNC);
|
||||
imxrt_config_gpio(GPIO_LCD_VSYNC);
|
||||
imxrt_config_gpio(GPIO_LCD_CLK);
|
||||
|
||||
lcdinfo("Enable clocking to the LCD controller\n");
|
||||
|
||||
/* Enable clocking to the LCD peripheral */
|
||||
|
||||
imxrt_clockall_pxp();
|
||||
|
||||
imxrt_clockall_lcd();
|
||||
|
||||
imxrt_clockall_lcdif_pix();
|
||||
|
||||
/* Reset the LCD */
|
||||
|
||||
imxrt_lcdinitialize();
|
||||
|
||||
imxrt_lcdreset();
|
||||
|
||||
lcdinfo("Configuring the LCD controller\n");
|
||||
|
||||
putreg32(pixelFormat.regCtrl | dataBus |
|
||||
LCDIF_CTRL_DOTCLK_MODE_MASK |
|
||||
LCDIF_CTRL_BYPASS_COUNT_MASK |
|
||||
LCDIF_CTRL_MASTER_MASK, IMXRT_LCDIF_CTRL);
|
||||
|
||||
putreg32(pixelFormat.regCtrl1, IMXRT_LCDIF_CTRL1);
|
||||
|
||||
putreg32((CONFIG_IMXRT_LCD_VHEIGHT << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) |
|
||||
(CONFIG_IMXRT_LCD_HWIDTH << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT),
|
||||
IMXRT_LCDIF_TRANSFER_COUNT);
|
||||
|
||||
putreg32(LCDIF_VDCTRL0_ENABLE_PRESENT_MASK |
|
||||
LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK |
|
||||
LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK |
|
||||
VSYNC_POL | HSYNC_POL | DATAEN_POL | DATA_EDGE |
|
||||
CONFIG_IMXRT_LCD_VPULSE,
|
||||
IMXRT_LCDIF_VDCTRL0);
|
||||
|
||||
putreg32(CONFIG_IMXRT_LCD_VPULSE + CONFIG_IMXRT_LCD_VHEIGHT +
|
||||
CONFIG_IMXRT_LCD_VFRONTPORCH + CONFIG_IMXRT_LCD_VBACKPORCH,
|
||||
IMXRT_LCDIF_VDCTRL1);
|
||||
|
||||
putreg32((CONFIG_IMXRT_LCD_HPULSE << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) |
|
||||
((CONFIG_IMXRT_LCD_HFRONTPORCH + CONFIG_IMXRT_LCD_HBACKPORCH +
|
||||
CONFIG_IMXRT_LCD_HWIDTH + CONFIG_IMXRT_LCD_HPULSE)
|
||||
<< LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT),
|
||||
IMXRT_LCDIF_VDCTRL2);
|
||||
|
||||
putreg32(((CONFIG_IMXRT_LCD_HBACKPORCH + CONFIG_IMXRT_LCD_HPULSE)
|
||||
<< LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) |
|
||||
((CONFIG_IMXRT_LCD_VBACKPORCH + CONFIG_IMXRT_LCD_VPULSE)
|
||||
<< LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT),
|
||||
IMXRT_LCDIF_VDCTRL3);
|
||||
|
||||
putreg32(LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK |
|
||||
(CONFIG_IMXRT_LCD_HWIDTH << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT),
|
||||
IMXRT_LCDIF_VDCTRL4);
|
||||
|
||||
#ifdef CONFIG_IMXRT_LCD_BGR
|
||||
/* Swap red and blue. The colors will be 0x00RRGGBB, not 0x00bbGGRR. */
|
||||
|
||||
/* TODO */
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_IMXRT_LCD_INPUT_BPP8_LUT) || defined (CONFIG_IMXRT_LCD_INPUT_BPP8)
|
||||
|
||||
putreg32(0, IMXRT_LCDIF_LUT0_ADDR);
|
||||
|
||||
for (n = 0; n < IMXRT_LCDIF_LUT_ENTRY_NUM; n++)
|
||||
{
|
||||
uint8_t red;
|
||||
uint8_t green;
|
||||
uint8_t blue;
|
||||
|
||||
red = (n << 0) & 0xe0;
|
||||
green = (n << 3) & 0xe0;
|
||||
blue = (n << 6) & 0xc0;
|
||||
|
||||
#if defined (CONFIG_IMXRT_LCD_OUTPUT_24)
|
||||
putreg32((uint32_t)0xff000000 |
|
||||
((uint32_t)red << 16) |
|
||||
((uint32_t)green << 8) |
|
||||
((uint32_t)blue << 0),
|
||||
IMXRT_LCDIF_LUT0_DATA);
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_18)
|
||||
putreg32((uint32_t)0xfffc0000 |
|
||||
(((uint32_t)red & 0xfc) << 10) |
|
||||
(((uint32_t)green & 0xfc) << 4) |
|
||||
(((uint32_t)blue & 0xfc) >> 2),
|
||||
IMXRT_LCDIF_LUT0_DATA);
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_16)
|
||||
putreg32((uint32_t)0xffff0000 |
|
||||
(((uint32_t)red & 0xf8) << 8) |
|
||||
(((uint32_t)green & 0xfc) << 3) |
|
||||
(((uint32_t)blue & 0xf8) >> 3),
|
||||
IMXRT_LCDIF_LUT0_DATA);
|
||||
#endif
|
||||
}
|
||||
|
||||
putreg32(0, IMXRT_LCDIF_LUT_CTRL);
|
||||
|
||||
#endif
|
||||
|
||||
putreg32(CONFIG_IMXRT_LCD_VRAMBASE, IMXRT_LCDIF_CUR_BUF);
|
||||
putreg32(CONFIG_IMXRT_LCD_VRAMBASE, IMXRT_LCDIF_NEXT_BUF);
|
||||
|
||||
/* Clear the display */
|
||||
|
||||
imxrt_lcdclear(CONFIG_IMXRT_LCD_BACKCOLOR);
|
||||
|
||||
#ifdef CONFIG_IMXRT_LCD_BACKLIGHT
|
||||
|
||||
/* Turn on the back light */
|
||||
|
||||
imxrt_backlight(true);
|
||||
|
||||
#endif
|
||||
|
||||
putreg32(LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK,
|
||||
IMXRT_LCDIF_CTRL_SET);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_fbgetvplane
|
||||
*
|
||||
* Description:
|
||||
* Return a a reference to the framebuffer object for the specified video
|
||||
* plane of the specified plane. Many OSDs support multiple planes of
|
||||
* video.
|
||||
*
|
||||
* Input Parameters:
|
||||
* display - In the case of hardware with multiple displays, this
|
||||
* specifies the display. Normally this is zero.
|
||||
* vplane - Identifies the plane being queried.
|
||||
*
|
||||
* Returned Value:
|
||||
* A non-NULL pointer to the frame buffer access structure is returned on
|
||||
* success; NULL is returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane)
|
||||
{
|
||||
lcdinfo("vplane: %d\n", vplane);
|
||||
if (vplane == 0)
|
||||
{
|
||||
return &g_fbobject;
|
||||
}
|
||||
else
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_fbuninitialize
|
||||
*
|
||||
* Description:
|
||||
* Uninitialize the framebuffer support for the specified display.
|
||||
*
|
||||
* Input Parameters:
|
||||
* display - In the case of hardware with multiple displays, this
|
||||
* specifies the display. Normally this is zero.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_fbuninitialize(int display)
|
||||
{
|
||||
/* We assume there is only one use of the LCD and so we do not need to
|
||||
* worry about mutually exclusive access to the LCD hardware.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LCD_BACKLIGHT
|
||||
/* Turn off the back light */
|
||||
|
||||
imxrt_backlight(false);
|
||||
#endif
|
||||
|
||||
/* Disable the clock gate. */
|
||||
|
||||
putreg32(LCDIF_CTRL_CLKGATE_MASK, IMXRT_LCDIF_CTRL_CLR);
|
||||
|
||||
/* Disable clocking to the LCD peripheral */
|
||||
|
||||
imxrt_clockoff_lcdif_pix();
|
||||
|
||||
imxrt_clockoff_lcd();
|
||||
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lcdclear
|
||||
*
|
||||
* Description:
|
||||
* This is a non-standard LCD interface just for the IMXRT. Clearing
|
||||
* the display in the normal way by writing a sequences of runs that
|
||||
* covers the entire display can be slow. Here the dispaly is cleared by
|
||||
* simply setting all VRAM memory to the specified color.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imxrt_lcdclear(nxgl_mxpixel_t color)
|
||||
{
|
||||
int i;
|
||||
int size;
|
||||
|
||||
size = CONFIG_IMXRT_LCD_HWIDTH * CONFIG_IMXRT_LCD_VHEIGHT;
|
||||
|
||||
#if IMXRT_BPP > 24
|
||||
uint32_t *dest = (uint32_t *)CONFIG_IMXRT_LCD_VRAMBASE;
|
||||
|
||||
lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n",
|
||||
color, CONFIG_IMXRT_LCD_VRAMBASE,
|
||||
size * sizeof(uint32_t));
|
||||
|
||||
#elif IMXRT_BPP > 16
|
||||
uint32_t *dest = (uint32_t *)CONFIG_IMXRT_LCD_VRAMBASE;
|
||||
|
||||
size = (size * 3) >> 2;
|
||||
|
||||
lcdinfo("Clearing display: color=%06x VRAM=%08x size=%d\n",
|
||||
color, CONFIG_IMXRT_LCD_VRAMBASE,
|
||||
size * sizeof(uint32_t));
|
||||
|
||||
#elif IMXRT_BPP > 8
|
||||
uint16_t *dest = (uint16_t *)CONFIG_IMXRT_LCD_VRAMBASE;
|
||||
|
||||
lcdinfo("Clearing display: color=%04x VRAM=%08x size=%d\n",
|
||||
color, CONFIG_IMXRT_LCD_VRAMBASE,
|
||||
size * sizeof(uint16_t));
|
||||
#else
|
||||
uint8_t *dest = (uint8_t *)CONFIG_IMXRT_LCD_VRAMBASE;
|
||||
|
||||
lcdinfo("Clearing display: color=%02x VRAM=%08x size=%d\n",
|
||||
color, CONFIG_IMXRT_LCD_VRAMBASE,
|
||||
size * sizeof(uint8_t));
|
||||
#endif
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
{
|
||||
*dest++ = color;
|
||||
}
|
||||
}
|
||||
214
arch/arm/src/imxrt/imxrt_lcd.h
Normal file
214
arch/arm/src/imxrt/imxrt_lcd.h
Normal file
@ -0,0 +1,214 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/imxrt/imxrt_lcd.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Johannes Schock
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* The I.MX RT LCD driver uses the common framebuffer interfaces declared in
|
||||
* include/nuttx/video/fb.h.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_LCD_H
|
||||
#define __ARCH_ARM_SRC_IMXRT_IMXRT_LCD_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "chip/imxrt_lcd.h"
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <nuttx/nx/nxglib.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration */
|
||||
|
||||
#ifndef IMXRT_LCD_VIDEO_PLL_FREQ
|
||||
# define IMXRT_LCD_VIDEO_PLL_FREQ 92000000
|
||||
#endif
|
||||
|
||||
/* Base address of the video RAM frame buffer */
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_VRAMBASE
|
||||
# define CONFIG_IMXRT_LCD_VRAMBASE (0x20240000)
|
||||
#endif
|
||||
|
||||
/* LCD refresh rate */
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_REFRESH_FREQ
|
||||
# define CONFIG_IMXRT_LCD_REFRESH_FREQ (60) /* Hz */
|
||||
#endif
|
||||
|
||||
#undef IMXRT_BPP
|
||||
#undef IMXRT_COLOR_FMT
|
||||
|
||||
/* Bits per pixel / color format */
|
||||
|
||||
#if defined (CONFIG_IMXRT_LCD_INPUT_BPP8_LUT)
|
||||
# define IMXRT_BPP 8
|
||||
# define IMXRT_COLOR_FMT FB_FMT_RGB8
|
||||
#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP8)
|
||||
# define IMXRT_BPP 8
|
||||
# define IMXRT_COLOR_FMT FB_FMT_RGB8_332
|
||||
#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP15)
|
||||
# define IMXRT_BPP 16
|
||||
# define IMXRT_COLOR_FMT FB_FMT_RGB16_555
|
||||
#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP16)
|
||||
# define IMXRT_BPP 16
|
||||
# define IMXRT_COLOR_FMT FB_FMT_RGB16_565
|
||||
#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP24)
|
||||
# define IMXRT_BPP 24
|
||||
# define IMXRT_COLOR_FMT FB_FMT_RGB24
|
||||
#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP32)
|
||||
# define IMXRT_BPP 32
|
||||
# define IMXRT_COLOR_FMT FB_FMT_RGB32
|
||||
#else
|
||||
# define CONFIG_IMXRT_LCD_INPUT_BPP16
|
||||
# define IMXRT_BPP 16
|
||||
# define IMXRT_COLOR_FMT FB_FMT_RGB16_565
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_IMXRT_LCD_OUTPUT_8)
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_16)
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_18)
|
||||
#elif defined (CONFIG_IMXRT_LCD_OUTPUT_24)
|
||||
#else
|
||||
# define CONFIG_IMXRT_LCD_OUTPUT_24
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_BACKCOLOR
|
||||
# define CONFIG_IMXRT_LCD_BACKCOLOR 0x0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_HWIDTH
|
||||
# define CONFIG_IMXRT_LCD_HWIDTH 480
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_HPULSE
|
||||
# define CONFIG_IMXRT_LCD_HPULSE 41
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_HFRONTPORCH
|
||||
# define CONFIG_IMXRT_LCD_HFRONTPORCH 4
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_HBACKPORCH
|
||||
# define CONFIG_IMXRT_LCD_HBACKPORCH 8
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_VHEIGHT
|
||||
# define CONFIG_IMXRT_LCD_VHEIGHT 272
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_VPULSE
|
||||
# define CONFIG_IMXRT_LCD_VPULSE 10
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_VFRONTPORCH
|
||||
# define CONFIG_IMXRT_LCD_VFRONTPORCH 4
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IMXRT_LCD_VBACKPORCH
|
||||
# define CONFIG_IMXRT_LCD_VBACKPORCH 2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_VSYNC_ACTIVE_HIGH
|
||||
# define VSYNC_POL LCDIF_VDCTRL0_VSYNC_POL_MASK
|
||||
#else
|
||||
# define VSYNC_POL 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_HSYNC_ACTIVE_HIGH
|
||||
# define HSYNC_POL LCDIF_VDCTRL0_HSYNC_POL_MASK
|
||||
#else
|
||||
# define HSYNC_POL 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_DATAEN_ACTIVE_HIGH
|
||||
# define DATAEN_POL LCDIF_VDCTRL0_ENABLE_POL_MASK
|
||||
#else
|
||||
# define DATAEN_POL 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_DATA_RISING_EDGE
|
||||
# define DATA_EDGE LCDIF_VDCTRL0_DOTCLK_POL_MASK
|
||||
#else
|
||||
# define DATA_EDGE 0
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: IMXRT_lcdclear
|
||||
*
|
||||
* Description:
|
||||
* This is a non-standard LCD interface just for the I.MX RT. Clearing
|
||||
* the display in the normal way by writing a sequences of runs that
|
||||
* covers the entire display can be slow. Here the display is cleared by
|
||||
* simply setting all VRAM memory to the specified color.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imxrt_lcdclear(nxgl_mxpixel_t color);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lcd_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the LCD. Setup backlight (initially off)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imxrt_lcdinitialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: IMXRT_backlight
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_IMXRT_LCD_BACKLIGHT is defined, then the board-specific logic
|
||||
* must provide this interface to turn the backlight on and off.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LCD_BACKLIGHT
|
||||
void imxrt_backlight(bool blon);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_LCD_H */
|
||||
@ -17,4 +17,10 @@ config IMXRT1050_EVK_QSPI_FLASH
|
||||
|
||||
endchoice # Boot Flash
|
||||
|
||||
config IMXRT1050_EVK_SDRAM
|
||||
bool "Enable SDRAM"
|
||||
default n
|
||||
---help---
|
||||
Activate DCD configuration of SDRAM
|
||||
|
||||
endif
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
/* The i.MXRT1050-EVK has 64Mb of Hyper FLASH beginning at address,
|
||||
* 0x0060:0000, 512Kb of DTCM RAM beginning at 0x2000:0000, and 512Kb OCRAM
|
||||
* beginning at 0x2020:0000. Neither DTCM or SDRAM are used in this
|
||||
* configuratin.
|
||||
* configuration.
|
||||
*
|
||||
* The user and kernel space partitions will be spanned with a single
|
||||
* region of size 2**n bytes. As a consequence, as the partitions increase
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
############################################################################
|
||||
# configs/imxrt1050-evk/src/Makefile
|
||||
#
|
||||
# Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
# Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
@ -66,6 +66,10 @@ ifeq ($(CONFIG_IMXRT_LPSPI),y)
|
||||
CSRCS += imxrt_spi.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_IMXRT_LCD),y)
|
||||
CSRCS += imxrt_lcd.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MMCSD_SPI),y)
|
||||
CSRCS += imxrt_mmcsd_spi.c
|
||||
endif
|
||||
@ -74,4 +78,8 @@ ifeq ($(CONFIG_DEV_GPIO),y)
|
||||
CSRCS += imxrt_gpio.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_IMXRT1050_EVK_SDRAM),y)
|
||||
CSRCS += imxrt_sdram_ini_dcd.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
|
||||
@ -105,6 +105,14 @@
|
||||
#define GPIO_LED (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT1 | \
|
||||
GPIO_PIN9 | IOMUX_LED)
|
||||
|
||||
/* Backlight of LCD */
|
||||
|
||||
#define IOMUX_LCD_BL (IOMUX_PULL_NONE | IOMUX_CMOS_OUTPUT | \
|
||||
IOMUX_DRIVE_40OHM | IOMUX_SPEED_MEDIUM | \
|
||||
IOMUX_SLEW_SLOW)
|
||||
#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT2 | \
|
||||
GPIO_PIN31 | IOMUX_LCD_BL)
|
||||
|
||||
/* Buttons
|
||||
*
|
||||
* The IMXRT board has one external user button
|
||||
|
||||
@ -45,6 +45,7 @@
|
||||
|
||||
#include <syslog.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
#include <nuttx/video/fb.h>
|
||||
#include <imxrt_lpi2c.h>
|
||||
#include <imxrt_lpspi.h>
|
||||
|
||||
@ -188,6 +189,16 @@ int imxrt_bringup(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_FB
|
||||
/* Initialize and register the framebuffer driver */
|
||||
|
||||
ret = fb_register(0, 0);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -44,20 +44,20 @@
|
||||
****************************************************************************/
|
||||
|
||||
__attribute__((section(".boot_hdr.ivt")))
|
||||
const struct ivt_s image_vector_table =
|
||||
const struct ivt_s g_image_vector_table =
|
||||
{
|
||||
IVT_HEADER, /* IVT Header */
|
||||
0x60002000, /* Image Entry Function */
|
||||
IVT_RSVD, /* Reserved = 0 */
|
||||
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
|
||||
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
|
||||
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
|
||||
(uint32_t)&g_image_vector_table, /* Pointer to IVT Self (absolute address */
|
||||
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
|
||||
IVT_RSVD /* Reserved = 0 */
|
||||
};
|
||||
|
||||
__attribute__((section(".boot_hdr.boot_data")))
|
||||
const struct boot_data_s boot_data =
|
||||
const struct boot_data_s g_boot_data =
|
||||
{
|
||||
FLASH_BASE, /* boot start location */
|
||||
(FLASH_END - FLASH_BASE), /* size */
|
||||
|
||||
@ -77,8 +77,13 @@
|
||||
#define FLASH_END 0x7f7fffff
|
||||
#define SCLK 1
|
||||
|
||||
#define DCD_ADDRESS 0
|
||||
#define BOOT_DATA_ADDRESS &boot_data
|
||||
#ifdef CONFIG_IMXRT1050_EVK_SDRAM
|
||||
# define DCD_ADDRESS &g_dcd_data
|
||||
#else
|
||||
# define DCD_ADDRESS 0
|
||||
#endif
|
||||
|
||||
#define BOOT_DATA_ADDRESS &g_boot_data
|
||||
#define CSF_ADDRESS 0
|
||||
#define PLUGIN_FLAG (uint32_t)0
|
||||
|
||||
@ -143,6 +148,10 @@ struct boot_data_s
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
extern const struct boot_data_s boot_data;
|
||||
extern const struct boot_data_s g_boot_data;
|
||||
|
||||
#ifdef CONFIG_IMXRT1050_EVK_SDRAM
|
||||
extern const uint8_t g_dcd_data[];
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIGS_IMXRT1050_EVK_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */
|
||||
|
||||
83
configs/imxrt1050-evk/src/imxrt_lcd.c
Normal file
83
configs/imxrt1050-evk/src/imxrt_lcd.c
Normal file
@ -0,0 +1,83 @@
|
||||
/****************************************************************************
|
||||
* configs/imxrt1050-evk/src/imxrt_lcd.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include "imxrt_lcd.h"
|
||||
#include "imxrt_gpio.h"
|
||||
|
||||
#include "imxrt1050-evk.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lcd_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the LCD. Setup backlight (initially off)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imxrt_lcdinitialize(void)
|
||||
{
|
||||
/* Configure the LCD backlight (and turn the backlight off) */
|
||||
|
||||
imxrt_config_gpio(GPIO_LCD_BL);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_backlight
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_IMXRT_LCD_BACKLIGHT is defined, then the board-specific
|
||||
* logic must provide this interface to turn the backlight on and off.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_LCD_BACKLIGHT
|
||||
void imxrt_backlight(bool blon)
|
||||
{
|
||||
imxrt_gpio_write(GPIO_LCD_BL, blon); /* High illuminates */
|
||||
}
|
||||
#endif
|
||||
1116
configs/imxrt1050-evk/src/imxrt_sdram_ini_dcd.c
Normal file
1116
configs/imxrt1050-evk/src/imxrt_sdram_ini_dcd.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user