From b95fadcaa60d9974b921d694f6071dbc2b0b0fa1 Mon Sep 17 00:00:00 2001 From: Johannes Date: Mon, 4 Mar 2019 08:35:29 -0600 Subject: [PATCH] Squashed commit of the following: Author: Gregory Nutt arch/arm/src/imxrt/: Fix complaints from tools/nxstyle in new LCD files. Use tools/lowhex to convert hexadecimal constants to lower case. Use tools/rmcr to review white space at the end of lines. Author: Johannes arch/arm/src/imxrt and configs/imxrt1050-evk: Adds framebuffer support for thje i.MXRT 1050. Includdd DCD initialization for SDRAM to provide space for the framebufer. External code I used/ported is from NXP and is BSD 3-clause license. --- arch/arm/src/imxrt/Kconfig | 159 +- arch/arm/src/imxrt/Make.defs | 4 + arch/arm/src/imxrt/chip/imxrt105x_pinmux.h | 59 +- arch/arm/src/imxrt/chip/imxrt_ccm.h | 90 +- arch/arm/src/imxrt/chip/imxrt_lcd.h | 1709 +++++++++++++++++ arch/arm/src/imxrt/imxrt_clockconfig.c | 194 +- arch/arm/src/imxrt/imxrt_lcd.c | 742 +++++++ arch/arm/src/imxrt/imxrt_lcd.h | 214 +++ configs/imxrt1050-evk/Kconfig | 6 + configs/imxrt1050-evk/scripts/memory.ld | 2 +- configs/imxrt1050-evk/src/Makefile | 10 +- configs/imxrt1050-evk/src/imxrt1050-evk.h | 8 + configs/imxrt1050-evk/src/imxrt_bringup.c | 11 + .../src/imxrt_flexspi_nor_boot.c | 6 +- .../src/imxrt_flexspi_nor_boot.h | 15 +- configs/imxrt1050-evk/src/imxrt_lcd.c | 83 + .../imxrt1050-evk/src/imxrt_sdram_ini_dcd.c | 1116 +++++++++++ 17 files changed, 4340 insertions(+), 88 deletions(-) create mode 100644 arch/arm/src/imxrt/chip/imxrt_lcd.h create mode 100644 arch/arm/src/imxrt/imxrt_lcd.c create mode 100644 arch/arm/src/imxrt/imxrt_lcd.h create mode 100644 configs/imxrt1050-evk/src/imxrt_lcd.c create mode 100644 configs/imxrt1050-evk/src/imxrt_sdram_ini_dcd.c diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 87223e999b..0171a206b7 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -25,7 +25,7 @@ config ARCH_CHIP_MIMXRT1052DVL6A select ARCH_FAMILY_MXRT105xDVL6A config ARCH_CHIP_MIMXRT1052CVL5A - bool "MIMXRT1052DVL6A" + bool "MIMXRT1052DVL5A" select ARCH_FAMILY_MIMXRT1052CVL5A config ARCH_CHIP_MIMXRT1061DVL6A @@ -71,6 +71,7 @@ config ARCH_FAMILY_IMXRT105x select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select IMXRT_HAVE_LCD config ARCH_FAMILY_MXRT106xDVL6A bool @@ -96,6 +97,7 @@ config ARCH_FAMILY_IMXRT106x select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM select IMXRT_HIGHSPEED_GPIO + select IMXRT_HAVE_LCD # Peripheral support @@ -115,6 +117,10 @@ config IMXRT_HIGHSPEED_GPIO bool default n +config IMXRT_HAVE_LCD + bool + default n + menu "i.MX RT Peripheral Selection" config IMXRT_EDMA @@ -129,6 +135,11 @@ config IMXRT_ENET select ARCH_PHY_INTERRUPT select ARCH_HAVE_NETDEV_STATISTICS +config IMXRT_LCD + bool "LCD controller" + default n + depends on IMXRT_HAVE_LCD + menu "FlexIO Peripherals" endmenu # FlexIO Peripherals @@ -730,5 +741,151 @@ config IMXRT_RTC_MAGIC Value used as Magic to determine if the RTC is already setup endmenu + +menu "LCD Configuration" + depends on IMXRT_LCD + +config IMXRT_LCD_VIDEO_PLL_FREQ + int "Video PLL Frequency" + default 92000000 + range 41500000 1300000000 + ---help--- + Frequency of Video PLL. + +config IMXRT_LCD_VRAMBASE + hex "Video RAM base address" + default 0x80000000 + ---help--- + Base address of the video RAM frame buffer. + Default: SDRAM + +config IMXRT_LCD_REFRESH_FREQ + int "LCD refesh rate (Hz)" + default 60 + ---help--- + LCD refesh rate (Hz) + +config IMXRT_LCD_BACKLIGHT + bool "Enable backlight" + default y + ---help--- + Enable backlight support. If IMXRT_LCD_BACKLIGHT is selected, then + the board-specific logic must provide this IMXRT_backlight() + interface so that the LCD driver can turn the backlight on and off + as necessary. You should select this option and implement + IMXRT_backlight() if your board provides GPIO control over the + backlight. This interface provides only ON/OFF control of the + backlight. If you want finer control over the backlight level (for + example, using PWM), then this interface would need to be extended. + +choice + prompt "Input Bits per pixel" + default IMXRT_LCD_INPUT_BPP16 + +config IMXRT_LCD_INPUT_BPP8_LUT + bool "8 BPP Color Map" + select FB_CMAP + +config IMXRT_LCD_INPUT_BPP8 + bool "8 BPP RGB_332" + +config IMXRT_LCD_INPUT_BPP15 + bool "16 BPP RGB_555" + +config IMXRT_LCD_INPUT_BPP16 + bool "16 BPP RGB_565" + +config IMXRT_LCD_INPUT_BPP24 + bool "24 BPP RGB_888" + +config IMXRT_LCD_INPUT_BPP32 + bool "32 BPP RGB_0888" + +endchoice + +config IMXRT_LCD_BGR + bool "Blue-Green-Red color order" + default n + ---help--- + This option selects BGR color order vs. default RGB + +choice + prompt "Output Bus width" + default IMXRT_LCD_OUTPUT_16 + +config IMXRT_LCD_OUTPUT_8 + bool "8 Bit LCD Bus" + +config IMXRT_LCD_OUTPUT_16 + bool "16 Bit LCD Bus" + +config IMXRT_LCD_OUTPUT_18 + bool "18 Bit LCD Bus" + +config IMXRT_LCD_OUTPUT_24 + bool "24 Bit LCD Bus" + +endchoice + +config IMXRT_LCD_BACKCOLOR + hex "Initial background color" + default 0x0 + ---help--- + Initial background color + +config IMXRT_LCD_HWIDTH + int "Display width (pixels)" + default 480 + ---help--- + Horizontal width the display in pixels + +config IMXRT_LCD_HPULSE + int "Horizontal pulse" + default 41 + +config IMXRT_LCD_HFRONTPORCH + int "Horizontal front porch" + default 4 + +config IMXRT_LCD_HBACKPORCH + int "Horizontal back porch" + default 8 + +config IMXRT_LCD_VHEIGHT + int "Display height (rows)" + default 272 + ---help--- + Vertical height of the display in rows + +config IMXRT_LCD_VPULSE + int "Vertical pulse" + default 10 + +config IMXRT_LCD_VFRONTPORCH + int "Vertical front porch" + default 4 + +config IMXRT_LCD_VBACKPORCH + int "Vertical back porch" + default 2 + +config IMXRT_VSYNC_ACTIVE_HIGH + bool "V-sync active high" + default n + +config IMXRT_HSYNC_ACTIVE_HIGH + bool "H-sync active high" + default n + +config IMXRT_DATAEN_ACTIVE_HIGH + bool "Data enable active high" + default y + +config IMXRT_DATA_RISING_EDGE + bool "Data clock rising edge" + default y + +endmenu # LCD Configuration + endif # ARCH_CHIP_IMXRT diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs index cb30b74d37..e3ad6a818d 100644 --- a/arch/arm/src/imxrt/Make.defs +++ b/arch/arm/src/imxrt/Make.defs @@ -130,6 +130,10 @@ ifdef CONFIG_IMXRT_USDHC CHIP_CSRCS += imxrt_usdhc.c endif +ifeq ($(CONFIG_IMXRT_LCD),y) +CHIP_CSRCS += imxrt_lcd.c +endif + ifeq ($(CONFIG_IMXRT_SNVS_LPSRTC),y) CHIP_CSRCS += imxrt_lpsrtc.c CHIP_CSRCS += imxrt_hprtc.c diff --git a/arch/arm/src/imxrt/chip/imxrt105x_pinmux.h b/arch/arm/src/imxrt/chip/imxrt105x_pinmux.h index 4f3b17ab9f..089b54365c 100644 --- a/arch/arm/src/imxrt/chip/imxrt105x_pinmux.h +++ b/arch/arm/src/imxrt/chip/imxrt105x_pinmux.h @@ -574,34 +574,37 @@ /* LCD */ -#define GPIO_LCD_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) -#define GPIO_LCD_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) -#define GPIO_LCD_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) -#define GPIO_LCD_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) -#define GPIO_LCD_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) -#define GPIO_LCD_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) -#define GPIO_LCD_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) -#define GPIO_LCD_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) -#define GPIO_LCD_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) -#define GPIO_LCD_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) -#define GPIO_LCD_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) -#define GPIO_LCD_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) -#define GPIO_LCD_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) -#define GPIO_LCD_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) -#define GPIO_LCD_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) -#define GPIO_LCD_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) -#define GPIO_LCD_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) -#define GPIO_LCD_DATA16 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) -#define GPIO_LCD_DATA17 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) -#define GPIO_LCD_DATA18 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) -#define GPIO_LCD_DATA19 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) -#define GPIO_LCD_DATA20 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) -#define GPIO_LCD_DATA21 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) -#define GPIO_LCD_DATA22 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) -#define GPIO_LCD_DATA23 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) -#define GPIO_LCD_ENABLE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) -#define GPIO_LCD_HSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) -#define GPIO_LCD_VSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) +#define IOMUX_LCD (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ + IOMUX_SLEW_SLOW | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER) + +#define GPIO_LCD_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA16 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA17 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA18 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA19 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA20 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA21 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA22 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | IOMUX_LCD) +#define GPIO_LCD_DATA23 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | IOMUX_LCD) +#define GPIO_LCD_ENABLE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX) | IOMUX_LCD) +#define GPIO_LCD_HSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX) | IOMUX_LCD) +#define GPIO_LCD_VSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX) | IOMUX_LCD) /* Low Power Inter-Integrated Circuit (LPI2C) */ diff --git a/arch/arm/src/imxrt/chip/imxrt_ccm.h b/arch/arm/src/imxrt/chip/imxrt_ccm.h index 55d9e1c6f0..cc1ca0230f 100644 --- a/arch/arm/src/imxrt/chip/imxrt_ccm.h +++ b/arch/arm/src/imxrt/chip/imxrt_ccm.h @@ -1089,55 +1089,55 @@ /* Miscellaneous Register 2 */ -#define CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC1_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC1_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC1_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG0_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC1_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */ /* Bit 4: Reserved */ -#define CCM_ANALOG_MISC1_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ -#define CCM_ANALOG_MISC1_REG0_OK (1 << 6) /* Bit 6: ARM supply */ -#define CCM_ANALOG_MISC1_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ -#define CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC1_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC1_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC1_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG1_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC1_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ +#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ /* Bit 12: Reserved */ -#define CCM_ANALOG_MISC1_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ -#define CCM_ANALOG_MISC1_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ -#define CCM_ANALOG_MISC1_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ -#define CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC1_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC1_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC1_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG2_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC1_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ /* Bit 20: Reserved */ -#define CCM_ANALOG_MISC1_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ -#define CCM_ANALOG_MISC1_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ -#define CCM_ANALOG_MISC1_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ -#define CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC1_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG0_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC1_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG1_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC1_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC1_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC1_REG2_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ -#define CCM_ANALOG_MISC1_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT) -# define CCM_ANALOG_MISC1_VIDEO_DIV(n) ((uint32_t)(0) << CCM_ANALOG_MISC1_VIDEO_DIV_SHIFT) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) +# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) #endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_lcd.h b/arch/arm/src/imxrt/chip/imxrt_lcd.h new file mode 100644 index 0000000000..4a7b94e254 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt_lcd.h @@ -0,0 +1,1709 @@ +/************************************************************************************************ + * arch/arm/src/imxrt/chip/imxrt_lcd.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2018 NXP. All rights reserved. + * Author: Johannes Schock (Port) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets *****************************************************************************/ + +#define IMXRT_LCDIF_CTRL_OFFSET 0x0000 /* General Control Register */ +#define IMXRT_LCDIF_CTRL_SET_OFFSET 0x0004 /* General Control Register */ +#define IMXRT_LCDIF_CTRL_CLR_OFFSET 0x0008 /* General Control Register */ +#define IMXRT_LCDIF_CTRL_TOG_OFFSET 0x000c /* General Control Register */ +#define IMXRT_LCDIF_CTRL1_OFFSET 0x0010 /* General Control1 Register */ +#define IMXRT_LCDIF_CTRL1_SET_OFFSET 0x0014 /* General Control1 Register */ +#define IMXRT_LCDIF_CTRL1_CLR_OFFSET 0x0018 /* General Control1 Register */ +#define IMXRT_LCDIF_CTRL1_TOG_OFFSET 0x001c /* General Control1 Register */ +#define IMXRT_LCDIF_CTRL2_OFFSET 0x0020 /* General Control2 Register */ +#define IMXRT_LCDIF_CTRL2_SET_OFFSET 0x0024 /* General Control2 Register */ +#define IMXRT_LCDIF_CTRL2_CLR_OFFSET 0x0028 /* General Control2 Register */ +#define IMXRT_LCDIF_CTRL2_TOG_OFFSET 0x002c /* General Control2 Register */ +#define IMXRT_LCDIF_TRANSFER_COUNT_OFFSET 0x0030 /* Horizontal and Vertical Valid Data Count Register */ +#define IMXRT_LCDIF_CUR_BUF_OFFSET 0x0040 /* Current Buffer Address Register */ +#define IMXRT_LCDIF_NEXT_BUF_OFFSET 0x0050 /* Next Buffer Address Register */ +#define IMXRT_LCDIF_VDCTRL0_OFFSET 0x0070 /* VSYNC Mode and Dotclk Mode Control Register0 */ +#define IMXRT_LCDIF_VDCTRL0_SET_OFFSET 0x0074 /* VSYNC Mode and Dotclk Mode Control Register0 */ +#define IMXRT_LCDIF_VDCTRL0_CLR_OFFSET 0x0078 /* VSYNC Mode and Dotclk Mode Control Register0 */ +#define IMXRT_LCDIF_VDCTRL0_TOG_OFFSET 0x007c /* VSYNC Mode and Dotclk Mode Control Register0 */ +#define IMXRT_LCDIF_VDCTRL1_OFFSET 0x0080 /* VSYNC Mode and Dotclk Mode Control Register1 */ +#define IMXRT_LCDIF_VDCTRL2_OFFSET 0x0090 /* VSYNC Mode and Dotclk Mode Control Register2 */ +#define IMXRT_LCDIF_VDCTRL3_OFFSET 0x00a0 /* VSYNC Mode and Dotclk Mode Control Register3 */ +#define IMXRT_LCDIF_VDCTRL4_OFFSET 0x00b0 /* VSYNC Mode and Dotclk Mode Control Register4 */ +#define IMXRT_LCDIF_BM_ERROR_STAT_OFFSET 0x0190 /* Bus Master Error Status Register */ +#define IMXRT_LCDIF_CRC_STAT_OFFSET 0x01a0 /* CRC Status Register */ +#define IMXRT_LCDIF_STAT_OFFSET 0x01b0 /* LCD Interface Status Register */ +#define IMXRT_LCDIF_THRES_OFFSET 0x0200 /* Threshold Register */ + +#define IMXRT_LCDIF_PIGEONCTRL0_OFFSET 0x0380 /* Pigeon Mode Control0 Register */ +#define IMXRT_LCDIF_PIGEONCTRL0_SET_OFFSET 0x0384 /* Pigeon Mode Control0 Register */ +#define IMXRT_LCDIF_PIGEONCTRL0_CLR_OFFSET 0x0388 /* Pigeon Mode Control0 Register */ +#define IMXRT_LCDIF_PIGEONCTRL0_TOG_OFFSET 0x038c /* Pigeon Mode Control0 Register */ +#define IMXRT_LCDIF_PIGEONCTRL1_OFFSET 0x0390 /* Pigeon Mode Control1 Register */ +#define IMXRT_LCDIF_PIGEONCTRL1_SET_OFFSET 0x0394 /* Pigeon Mode Control1 Register */ +#define IMXRT_LCDIF_PIGEONCTRL1_CLR_OFFSET 0x0398 /* Pigeon Mode Control1 Register */ +#define IMXRT_LCDIF_PIGEONCTRL1_TOG_OFFSET 0x039c /* Pigeon Mode Control1 Register */ +#define IMXRT_LCDIF_PIGEONCTRL2_OFFSET 0x03a0 /* Pigeon Mode Control2 Register */ +#define IMXRT_LCDIF_PIGEONCTRL2_SET_OFFSET 0x03a4 /* Pigeon Mode Control2 Register */ +#define IMXRT_LCDIF_PIGEONCTRL2_CLR_OFFSET 0x03a8 /* Pigeon Mode Control2 Register */ +#define IMXRT_LCDIF_PIGEONCTRL2_TOG_OFFSET 0x03ac /* Pigeon Mode Control2 Register */ + +#define IMXRT_LCDIF_PIGEON_START_OFFSET 0x0800 /* Pigeon */ +# define IMXRT_LCDIF_PIGEON0_OFFSET 0x0000 /* Pigeon 0 */ +# define IMXRT_LCDIF_PIGEON1_OFFSET 0x0010 /* Pigeon 1 */ +# define IMXRT_LCDIF_PIGEON2_OFFSET 0x0020 /* Pigeon 2 */ +# define IMXRT_LCDIF_PIGEON_SIZE 0x0040 /* Pigeon Element Size */ +# define IMXRT_LCDIF_PIGEON_NUM 12 /* Pigeon Element Number */ +# define IMXRT_LCDIF_PIGEON_OFFSET(n) (IMXRT_LCDIF_PIGEON_START_OFFSET + ((n) * IMXRT_LCDIF_PIGEON_SIZE)) + +#define IMXRT_LCDIF_LUT_CTRL_OFFSET 0x0b00 /* Lookup Table Data Register */ +#define IMXRT_LCDIF_LUT0_ADDR_OFFSET 0x0b10 /* Lookup Table Control Register */ +#define IMXRT_LCDIF_LUT0_DATA_OFFSET 0x0b20 /* Lookup Table Data Register */ +#define IMXRT_LCDIF_LUT1_ADDR_OFFSET 0x0b30 /* Lookup Table Control Register */ +#define IMXRT_LCDIF_LUT1_DATA_OFFSET 0x0b40 /* Lookup Table Data Register */ + +/* Register Addresses ***************************************************************************/ + +#define IMXRT_LCDIF_CTRL (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_OFFSET) +#define IMXRT_LCDIF_CTRL_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_SET_OFFSET) +#define IMXRT_LCDIF_CTRL_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_CLR_OFFSET) +#define IMXRT_LCDIF_CTRL_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_TOG_OFFSET) +#define IMXRT_LCDIF_CTRL1 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL1_OFFSET) +#define IMXRT_LCDIF_CTRL1_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL1_SET_OFFSET) +#define IMXRT_LCDIF_CTRL1_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL1_CLR_OFFSET) +#define IMXRT_LCDIF_CTRL1_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL1_TOG_OFFSET) +#define IMXRT_LCDIF_CTRL2 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL2_OFFSET) +#define IMXRT_LCDIF_CTRL2_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL2_SET_OFFSET) +#define IMXRT_LCDIF_CTRL2_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL2_CLR_OFFSET) +#define IMXRT_LCDIF_CTRL2_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL2_TOG_OFFSET) +#define IMXRT_LCDIF_TRANSFER_COUNT (IMXRT_LCDIF_BASE + IMXRT_LCDIF_TRANSFER_COUNT_OFFSET) +#define IMXRT_LCDIF_CUR_BUF (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CUR_BUF_OFFSET) +#define IMXRT_LCDIF_NEXT_BUF (IMXRT_LCDIF_BASE + IMXRT_LCDIF_NEXT_BUF_OFFSET) +#define IMXRT_LCDIF_VDCTRL0 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL0_OFFSET) +#define IMXRT_LCDIF_VDCTRL0_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL0_SET_OFFSET) +#define IMXRT_LCDIF_VDCTRL0_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL0_CLR_OFFSET) +#define IMXRT_LCDIF_VDCTRL0_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL0_TOG_OFFSET) +#define IMXRT_LCDIF_VDCTRL1 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL1_OFFSET) +#define IMXRT_LCDIF_VDCTRL2 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL2_OFFSET) +#define IMXRT_LCDIF_VDCTRL3 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL3_OFFSET) +#define IMXRT_LCDIF_VDCTRL4 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_VDCTRL4_OFFSET) +#define IMXRT_LCDIF_BM_ERROR_STAT (IMXRT_LCDIF_BASE + IMXRT_LCDIF_BM_ERROR_STAT_OFFSET) +#define IMXRT_LCDIF_CRC_STAT (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CRC_STAT_OFFSET) +#define IMXRT_LCDIF_STAT (IMXRT_LCDIF_BASE + IMXRT_LCDIF_STAT_OFFSET) +#define IMXRT_LCDIF_THRES (IMXRT_LCDIF_BASE + IMXRT_LCDIF_THRES_OFFSET) + +#define IMXRT_LCDIF_PIGEONCTRL0 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL0_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL0_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL0_SET_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL0_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL0_CLR_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL0_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL0_TOG_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL1 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL1_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL1_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL1_SET_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL1_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL1_CLR_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL1_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL1_TOG_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL2 (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL2_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL2_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL2_SET_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL2_CLR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL2_CLR_OFFSET) +#define IMXRT_LCDIF_PIGEONCTRL2_TOG (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEONCTRL2_TOG_OFFSET) + +#define IMXRT_LCDIF_PIGEON0(n) (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEON_OFFSET(n) + IMXRT_LCDIF_PIGEON0_OFFSET) +#define IMXRT_LCDIF_PIGEON1(n) (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEON_OFFSET(n) + IMXRT_LCDIF_PIGEON1_OFFSET) +#define IMXRT_LCDIF_PIGEON2(n) (IMXRT_LCDIF_BASE + IMXRT_LCDIF_PIGEON_OFFSET(n) + IMXRT_LCDIF_PIGEON2_OFFSET) + +#define IMXRT_LCDIF_LUT_CTRL (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT_CTRL_OFFSET) +#define IMXRT_LCDIF_LUT0_ADDR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT0_ADDR_OFFSET) +#define IMXRT_LCDIF_LUT0_DATA (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT0_DATA_OFFSET) +#define IMXRT_LCDIF_LUT1_ADDR (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT1_ADDR_OFFSET) +#define IMXRT_LCDIF_LUT1_DATA (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT1_DATA_OFFSET) +#define IMXRT_LCDIF_LUT_ENTRY_NUM (256) + +/* Register Bitfield Definitions ****************************************************************/ + +/* CTRL - LCDIF General Control Register */ + +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +/* DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +/* DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +/* WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xc00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) + +/* LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ + +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) + +/* CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ + +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xc000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) + +/* INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ + +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3e00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) + +/* DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ + +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) + +/* CTRL_SET - LCDIF General Control Register */ + +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) + +/* DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ + +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) + +/* DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ + +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) + +/* WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ + +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xc00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) + +/* LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ + +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) + +/* CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ + +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xc000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) + +/* INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ + +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3e00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) + +/* DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ + +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) + +/* CTRL_CLR - LCDIF General Control Register */ + +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) + +/* DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ + +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) + +/* DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ + +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) + +/* WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ + +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xc00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) + +/* LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ + +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) + +/* CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ + +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xc000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) + +/* INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ + +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3e00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) + +/* DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ + +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) + +/* CTRL_TOG - LCDIF General Control Register */ + +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) + +/* DATA_FORMAT_24_BIT + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + */ + +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) + +/* DATA_FORMAT_18_BIT + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + */ + +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) + +/* WORD_LENGTH + * 0b00..Input data is 16 bits per pixel. + * 0b01..Input data is 8 bits wide. + * 0b10..Input data is 18 bits per pixel. + * 0b11..Input data is 24 bits per pixel. + */ + +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xc00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) + +/* LCD_DATABUS_WIDTH + * 0b00..16-bit data bus mode. + * 0b01..8-bit data bus mode. + * 0b10..18-bit data bus mode. + * 0b11..24-bit data bus mode. + */ + +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) + +/* CSC_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ + +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xc000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) + +/* INPUT_DATA_SWIZZLE + * 0b00..No byte swapping.(Little endian) + * 0b00..Little Endian byte ordering (same as NO_SWAP). + * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). + * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). + * 0b10..Swap half-words. + * 0b11..Swap bytes within each half-word. + */ + +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3e00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) + +/* DATA_SHIFT_DIR + * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. + * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. + */ + +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) + +/* CTRL1 - LCDIF General Control1 Register */ + +#define LCDIF_CTRL1_RSRVD0_MASK (0xf8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) + +/* VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) + +/* CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) + +/* UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) + +/* OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) + +/* BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) + +/* CTRL1_SET - LCDIF General Control1 Register */ + +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xf8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) + +/* VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) + +/* CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) + +/* UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) + +/* OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xf0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) + +/* BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) + +/* CTRL1_CLR - LCDIF General Control1 Register */ + +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xf8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) + +/* VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) + +/* CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) + +/* UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) + +/* OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xf0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) + +/* BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) + +/* CTRL1_TOG - LCDIF General Control1 Register */ + +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xf8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) + +/* VSYNC_EDGE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) + +/* CUR_FRAME_DONE_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) + +/* UNDERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) + +/* OVERFLOW_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xf0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) + +/* BM_ERROR_IRQ + * 0b0..No Interrupt Request Pending. + * 0b1..Interrupt Request Pending. + */ + +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U) +#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) +#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) + +/* CTRL2 - LCDIF General Control2 Register */ + +#define LCDIF_CTRL2_RSRVD0_MASK (0xfffU) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) + +/* EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ + +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) + +/* ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ + +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xe00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) + +/* OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ + +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK (0xff000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) + +/* CTRL2_SET - LCDIF General Control2 Register */ + +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xfffU) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) + +/* EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ + +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) + +/* ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ + +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xe00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) + +/* OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ + +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xff000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) + +/* CTRL2_CLR - LCDIF General Control2 Register */ + +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xfffU) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) + +/* EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ + +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) + +/* ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ + +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xe00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) + +/* OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ + +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xff000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) + +/* CTRL2_TOG - LCDIF General Control2 Register */ + +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xfffU) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) + +/* EVEN_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ + +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) + +/* ODD_LINE_PATTERN + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR + */ + +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xe00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) + +/* OUTSTANDING_REQS + * 0b000..REQ_1 + * 0b001..REQ_2 + * 0b010..REQ_4 + * 0b011..REQ_8 + * 0b100..REQ_16 + */ + +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xff000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) + +/* TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ + +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffffU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) + +/* CUR_BUF - LCD Interface Current Buffer Address Register */ + +#define LCDIF_CUR_BUF_ADDR_MASK (0xffffffffU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) + +/* NEXT_BUF - LCD Interface Next Buffer Address Register */ + +#define LCDIF_NEXT_BUF_ADDR_MASK (0xffffffffU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) + +/* VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ + +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3ffffU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xc00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xe0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) + +/* VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ + +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3ffffU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xc00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xe0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) + +/* VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ + +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3ffffU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xc00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xe0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) + +/* VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ + +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3ffffU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xc00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xe0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) + +/* VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ + +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xffffffffU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) + +/* VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ + +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3ffffU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xfffc0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) + +/* VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ + +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffffU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xc0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) + +/* VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ + +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3ffffU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1ff80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xe0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) + +/* BM_ERROR_STAT - Bus Master Error Status Register */ + +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xffffffffU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) + +/* CRC_STAT - CRC Status Register */ + +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xffffffffU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) + +/* STAT - LCD Interface Status Register */ + +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1ffU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK (0x1fffe00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) +#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U) +#define LCDIF_STAT_DMA_REQ_SHIFT (30U) +#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK) +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) + +/* THRES - LCDIF Threshold Register */ + +#define LCDIF_THRES_PANIC_MASK (0x1ffU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK (0xfe00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK (0x1ff0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK (0xfe000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) + +/* PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ + +#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xfffU) +#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xfff0000U) +#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) + +/* PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ + +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xfffU) +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xfff0000U) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) + +/* PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ + +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xfffU) +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xfff0000U) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) + +/* PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ + +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xfffU) +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xfff0000U) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) +#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) + +/* PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ + +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xfffU) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xfff0000U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) + +/* PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ + +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xfffU) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xfff0000U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) + +/* PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ + +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xfffU) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xfff0000U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) + +/* PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ + +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xfffU) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xfff0000U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) +#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) + +/* PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ + +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) + +/* PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ + +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) + +/* PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ + +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) + +/* PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ + +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) +#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) + +/* PIGEON_0 - Panel Interface Signal Generator Register */ + +#define LCDIF_PIGEON_0_EN_MASK (0x1U) +#define LCDIF_PIGEON_0_EN_SHIFT (0U) +#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) +#define LCDIF_PIGEON_0_POL_MASK (0x2U) +#define LCDIF_PIGEON_0_POL_SHIFT (1U) + +/* POL + * 0b0..Normal Signal (Active high) + * 0b1..Inverted signal (Active low) + */ + +#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) +#define LCDIF_PIGEON_0_INC_SEL_MASK (0xcU) +#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) + +/* INC_SEL + * 0b00..pclk + * 0b01..Line start pulse + * 0b10..Frame start pulse + * 0b11..Use another signal as tick event + */ + +#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) +#define LCDIF_PIGEON_0_OFFSET_MASK (0xf0U) +#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U) +#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) +#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xf00U) +#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) + +/* MASK_CNT_SEL + * 0b0000..pclk counter within one hscan state + * 0b0001..pclk cycle within one hscan state + * 0b0010..line counter within one vscan state + * 0b0011..line cycle within one vscan state + * 0b0100..frame counter + * 0b0101..frame cycle + * 0b0110..horizontal counter (pclk counter within one line ) + * 0b0111..vertical counter (line counter within one frame) + */ + +#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) +#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xfff000U) +#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) +#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) +#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xff000000U) +#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) + +/* STATE_MASK + * 0b00000001..FRAME SYNC + * 0b00000010..FRAME BEGIN + * 0b00000100..FRAME DATA + * 0b00001000..FRAME END + * 0b00010000..LINE SYNC + * 0b00100000..LINE BEGIN + * 0b01000000..LINE DATA + * 0b10000000..LINE END + */ + +#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) + +/* The count of LCDIF_PIGEON_0 */ + +#define LCDIF_PIGEON_0_COUNT (12U) + +/* PIGEON_1 - Panel Interface Signal Generator Register */ + +#define LCDIF_PIGEON_1_SET_CNT_MASK (0xffffU) +#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) + +/* SET_CNT + * 0b0000000000000000..Start as active + */ + +#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) +#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xffff0000U) +#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) + +/* CLR_CNT + * 0b0000000000000000..Keep active until mask off + */ + +#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) + +/* The count of LCDIF_PIGEON_1 */ + +#define LCDIF_PIGEON_1_COUNT (12U) + +/* PIGEON_2 - Panel Interface Signal Generator Register */ + +#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xfU) +#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) + +/* SIG_LOGIC + * 0b0000..No logic operation + * 0b0001..sigout = sig_another AND this_sig + * 0b0010..sigout = sig_another OR this_sig + * 0b0011..mask = sig_another AND other_masks + */ + +#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) +#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1f0U) +#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) + +/* SIG_ANOTHER + * 0b00000..Keep active until mask off + */ + +#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) +#define LCDIF_PIGEON_2_RSVD_MASK (0xfffffe00U) +#define LCDIF_PIGEON_2_RSVD_SHIFT (9U) +#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) + +/* The count of LCDIF_PIGEON_2 */ + +#define LCDIF_PIGEON_2_COUNT (12U) + +/* LUT_CTRL - Lookup Table Data Register. */ + +#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) +#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) +#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) + +/* LUT0_ADDR - Lookup Table Control Register. */ + +#define LCDIF_LUT0_ADDR_ADDR_MASK (0xffU) +#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) +#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) + +/* LUT0_DATA - Lookup Table Data Register. */ + +#define LCDIF_LUT0_DATA_DATA_MASK (0xffffffffU) +#define LCDIF_LUT0_DATA_DATA_SHIFT (0U) +#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) + +/* LUT1_ADDR - Lookup Table Control Register. */ + +#define LCDIF_LUT1_ADDR_ADDR_MASK (0xffU) +#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) +#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) + +/* LUT1_DATA - Lookup Table Data Register. */ + +#define LCDIF_LUT1_DATA_DATA_MASK (0xffffffffU) +#define LCDIF_LUT1_DATA_DATA_SHIFT (0U) +#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H */ diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.c b/arch/arm/src/imxrt/imxrt_clockconfig.c index 14efe043e9..05a6b5c07e 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig.c +++ b/arch/arm/src/imxrt/imxrt_clockconfig.c @@ -46,8 +46,182 @@ #include "chip/imxrt_ccm.h" #include "chip/imxrt_dcdc.h" #include "imxrt_clockconfig.h" +#include "imxrt_lcd.h" #include "chip/imxrt_memorymap.h" +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define VIDEO_PLL_MIN_FREQ 650000000 +#define OSC24_FREQ 24000000 + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_lcd_clockconfig + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_LCD +static void imxrt_lcd_clockconfig(void) +{ + uint32_t reg; + uint32_t reg2; + + int post; + int pre; + + uint32_t numerator; + uint32_t denominator; + uint32_t post_divider; + uint32_t pre_divider; + uint32_t loop_divider; + uint32_t target_freq; + uint32_t freq_error; + + target_freq = (CONFIG_IMXRT_LCD_HWIDTH + + CONFIG_IMXRT_LCD_HPULSE + + CONFIG_IMXRT_LCD_HFRONTPORCH + + CONFIG_IMXRT_LCD_HBACKPORCH) * + (CONFIG_IMXRT_LCD_VHEIGHT + + CONFIG_IMXRT_LCD_VPULSE + + CONFIG_IMXRT_LCD_VFRONTPORCH + + CONFIG_IMXRT_LCD_VBACKPORCH) * + CONFIG_IMXRT_LCD_REFRESH_FREQ; + + for (post_divider = 1; post_divider < 16; post_divider <<= 1) + { + if (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider >= VIDEO_PLL_MIN_FREQ) + { + break; + } + } + + loop_divider = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) / OSC24_FREQ; + numerator = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) - + (loop_divider * OSC24_FREQ); + denominator = OSC24_FREQ; + + /* Bypass PLL first */ + + modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO, + CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK, + CCM_ANALOG_PLL_VIDEO_BYPASS | + CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M); + + putreg32(CCM_ANALOG_PLL_VIDEO_NUM_A(numerator), + IMXRT_CCM_ANALOG_PLL_VIDEO_NUM); + putreg32(CCM_ANALOG_PLL_VIDEO_DENOM_B(denominator), + IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM); + + /* Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + + reg = getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO); + reg &= ~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | + CCM_ANALOG_PLL_VIDEO_POWERDOWN); + reg |= CCM_ANALOG_PLL_VIDEO_ENABLE | + CCM_ANALOG_PLL_VIDEO_DIV_SELECT(loop_divider); + + reg2 = getreg32(IMXRT_CCM_ANALOG_MISC2); + reg2 &= ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK; + + switch (post_divider) + { + case 16: + reg |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4; + reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 8: + reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2; + reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 4: + reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1; + reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 2: + reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2; + reg2 |= 0; + break; + + default: + reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1; + reg2 |= 0; + break; + } + + putreg32(reg, IMXRT_CCM_ANALOG_PLL_VIDEO); + + putreg32(reg2, IMXRT_CCM_ANALOG_MISC2); + + while ((getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO) & + CCM_ANALOG_PLL_VIDEO_LOCK) == 0) + { + } + + /* Disable Bypass */ + + modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO, + CCM_ANALOG_PLL_VIDEO_BYPASS, + 0); + + freq_error = IMXRT_LCD_VIDEO_PLL_FREQ; + pre_divider = 0; + post_divider = 0; + + for (post = 0; post < 8; post++) + { + for (pre = 0; pre < 8; pre++) + { + int32_t temp_error; + temp_error = labs((post + 1) * (pre + 1) * target_freq - + IMXRT_LCD_VIDEO_PLL_FREQ); + if (temp_error < freq_error) + { + pre_divider = pre; + post_divider = post; + freq_error = temp_error; + } + } + } + + /* Select PLL5 as LCD Clock and set Pre divider. */ + + modifyreg32(IMXRT_CCM_CSCDR2, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK | CCM_CSCDR2_LCDIF_PRED_MASK, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 | CCM_CSCDR2_LCDIF_PRED(pre_divider)); + + /* Set Post divider. */ + + modifyreg32(IMXRT_CCM_CBCMR, CCM_CBCMR_LCDIF_PODF_MASK, + CCM_CBCMR_LCDIF_PODF(post_divider)); + +} + +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -91,7 +265,7 @@ void imxrt_clockconfig(void) /* Wait handshake */ - while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) == 1) + while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) != 0) { } @@ -104,7 +278,8 @@ void imxrt_clockconfig(void) /* Init Arm PLL1 */ - reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) | CCM_ANALOG_PLL_ARM_ENABLE; + reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) | + CCM_ANALOG_PLL_ARM_ENABLE; putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM); while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0) { @@ -112,12 +287,19 @@ void imxrt_clockconfig(void) /* Init Sys PLL2 */ - reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) | CCM_ANALOG_PLL_SYS_ENABLE; + reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) | + CCM_ANALOG_PLL_SYS_ENABLE; putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS); while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0) { } +#ifdef CONFIG_IMXRT_LCD + /* Init Video PLL5 */ + + imxrt_lcd_clockconfig(); +#endif + /* TODO: other pll configs */ /* Set Dividers */ @@ -163,7 +345,7 @@ void imxrt_clockconfig(void) /* Wait handshake */ - while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) == 1) + while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) != 0) { } @@ -196,7 +378,7 @@ void imxrt_clockconfig(void) reg |= CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M; putreg32(reg, IMXRT_CCM_CSCDR2); - while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) == 1) + while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0) { } @@ -207,7 +389,7 @@ void imxrt_clockconfig(void) reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5); putreg32(reg, IMXRT_CCM_CSCDR2); - while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) == 1) + while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0) { } #endif diff --git a/arch/arm/src/imxrt/imxrt_lcd.c b/arch/arm/src/imxrt/imxrt_lcd.c new file mode 100644 index 0000000000..815f08a2e1 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_lcd.c @@ -0,0 +1,742 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_lcd.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Copyright (C) 2017, NXP Semiconductors, Inc. + * Author: Johannes Schock (Port) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "imxrt_lcd.h" +#include "imxrt_periphclks.h" + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include + +#include + +#include "imxrt_gpio.h" +#include "imxrt_iomuxc.h" + +#include "chip/imxrt_pinmux.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMXRT_LCD_CLK_PER_LINE \ + (CONFIG_IMXRT_LCD_HWIDTH + CONFIG_IMXRT_LCD_HPULSE + \ + CONFIG_IMXRT_LCD_HFRONTPORCH + CONFIG_IMXRT_LCD_HBACKPORCH) +#define IMXRT_LCD_LINES_PER_FRAME \ + (CONFIG_IMXRT_LCD_VHEIGHT + CONFIG_IMXRT_LCD_VPULSE + \ + CONFIG_IMXRT_LCD_VFRONTPORCH + CONFIG_IMXRT_LCD_VBACKPORCH) +#define IMXRT_LCD_PIXEL_CLOCK \ + (IMXRT_LCD_CLK_PER_LINE * IMXRT_LCD_LINES_PER_FRAME * \ + CONFIG_IMXRT_LCD_REFRESH_FREQ) + +/* Framebuffer characteristics in bytes */ + +#define IMXRT_STRIDE ((CONFIG_IMXRT_LCD_HWIDTH * IMXRT_BPP + 7) / 8) +#define IMXRT_FBSIZE (IMXRT_STRIDE * CONFIG_IMXRT_LCD_VHEIGHT) + +/* Delays */ + +#define IMXRT_LCD_RESET_DELAY (0x100) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Get information about the video controller configuration and the + * configuration of each color plane. + */ + +static int imxrt_getvideoinfo(FAR struct fb_vtable_s *vtable, + FAR struct fb_videoinfo_s *vinfo); +static int imxrt_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, + FAR struct fb_planeinfo_s *pinfo); + +/* The following is provided only if the video hardware supports RGB color + * mapping + */ + +#ifdef CONFIG_FB_CMAP +static int imxrt_getcmap(FAR struct fb_vtable_s *vtable, + FAR struct fb_cmap_s *cmap); +static int imxrt_putcmap(FAR struct fb_vtable_s *vtable, + FAR const struct fb_cmap_s *cmap); +#endif + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This structure describes the video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = IMXRT_COLOR_FMT, + .xres = CONFIG_IMXRT_LCD_HWIDTH, + .yres = CONFIG_IMXRT_LCD_VHEIGHT, + .nplanes = 1, +}; + +/* This structure describes the single color plane */ + +static const struct fb_planeinfo_s g_planeinfo = +{ + .fbmem = (FAR void *)CONFIG_IMXRT_LCD_VRAMBASE, + .fblen = IMXRT_FBSIZE, + .stride = IMXRT_STRIDE, + .display = 0, + .bpp = IMXRT_BPP, +}; + +struct pixel_format_reg +{ + uint32_t regCtrl; /* Value of register CTRL. */ + uint32_t regCtrl1; /* Value of register CTRL1. */ +}; + +#if defined (CONFIG_IMXRT_LCD_INPUT_BPP8) || defined (CONFIG_IMXRT_LCD_INPUT_BPP8_LUT) + static const struct pixel_format_reg pixelFormat = + { + /* Register CTRL. */ + + LCDIF_CTRL_WORD_LENGTH(1U), + + /* Register CTRL1. */ + + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0fU) + }; + const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(1); + +#else + +# if defined (CONFIG_IMXRT_LCD_INPUT_BPP15) + static const struct pixel_format_reg pixelFormat = + { + /* Register CTRL. */ + + LCDIF_CTRL_WORD_LENGTH(0U) | LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK, + + /* Register CTRL1. */ + + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0fU) + }; +# elif defined (CONFIG_IMXRT_LCD_INPUT_BPP16) + static const struct pixel_format_reg pixelFormat = + { + /* Register CTRL. */ + + LCDIF_CTRL_WORD_LENGTH(0U), + + /* Register CTRL1. */ + + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0fU) + }; +# elif defined (CONFIG_IMXRT_LCD_INPUT_BPP24) + static const struct pixel_format_reg pixelFormat = + { + /* Register CTRL. 24-bit. */ + + LCDIF_CTRL_WORD_LENGTH(3U), + + /* Register CTRL1. */ + + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x0fU) + }; +# elif defined (CONFIG_IMXRT_LCD_INPUT_BPP32) + static const struct pixel_format_reg pixelFormat = + { + /* Register CTRL. 24-bit. */ + + LCDIF_CTRL_WORD_LENGTH(3U), + + /* Register CTRL1. */ + + LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x07U) + }; +# endif + +# if defined (CONFIG_IMXRT_LCD_OUTPUT_8) + const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(1); +# elif defined (CONFIG_IMXRT_LCD_OUTPUT_16) + const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(0); +# elif defined (CONFIG_IMXRT_LCD_OUTPUT_18) + const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(2); +# elif defined (CONFIG_IMXRT_LCD_OUTPUT_24) + const uint32_t dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH(3); +# endif + +#endif + +/* The framebuffer object -- There is no private state information in this + * framebuffer driver. + */ + +struct fb_vtable_s g_fbobject = +{ + .getvideoinfo = imxrt_getvideoinfo, + .getplaneinfo = imxrt_getplaneinfo, +#ifdef CONFIG_FB_CMAP + .getcmap = imxrt_getcmap, + .putcmap = imxrt_putcmap, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_getvideoinfo + ****************************************************************************/ + +static int imxrt_getvideoinfo(FAR struct fb_vtable_s *vtable, + FAR struct fb_videoinfo_s *vinfo) +{ + lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); + if (vtable && vinfo) + { + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: imxrt_getplaneinfo + ****************************************************************************/ + +static int imxrt_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, + FAR struct fb_planeinfo_s *pinfo) +{ + lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); + if (vtable && planeno == 0 && pinfo) + { + memcpy(pinfo, &g_planeinfo, sizeof(struct fb_planeinfo_s)); + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: imxrt_getcmap + ****************************************************************************/ + +#ifdef CONFIG_FB_CMAP +static int imxrt_getcmap(FAR struct fb_vtable_s *vtable, + FAR struct fb_cmap_s *cmap) +{ + uint32_t n; + uint32_t reg; + + lcdinfo("vtable=%p cmap=%p first=%d len=%d\n", + vtable, cmap, cmap->first, cmap->len); + + DEBUGASSERT(vtable && cmap); + + /* Only has 256 entries. */ + + if (cmap->first + cmap->len > IMXRT_LCDIF_LUT_ENTRY_NUM) + { + return ERROR; + } + + putreg32(cmap->first, IMXRT_LCDIF_LUT0_ADDR); + + for (n = 0; n < cmap->len; n++) + { + reg = getreg32(IMXRT_LCDIF_LUT0_DATA); + +#if defined (CONFIG_IMXRT_LCD_OUTPUT_24) + cmap->red[n] = (reg >> 16) & 0xff; + cmap->green[n] = (reg >> 8) & 0xff; + cmap->blue[n] = (reg >> 0) & 0xff; +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_18) + cmap->red[n] = (reg >> 10) & 0xfc; + cmap->green[n] = (reg >> 4) & 0xfc; + cmap->blue[n] = (reg << 2) & 0xfc; +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_16) + cmap->red[n] = (reg >> 8) & 0xf8; + cmap->green[n] = (reg >> 3) & 0xfc; + cmap->blue[n] = (reg << 3) & 0xf8; +#endif + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: imxrt_putcmap + ****************************************************************************/ + +#ifdef CONFIG_FB_CMAP +static int imxrt_putcmap(FAR struct fb_vtable_s *vtable, + FAR const struct fb_cmap_s *cmap) +{ + uint32_t n; + + lcdinfo("vtable=%p cmap=%p first=%d len=%d\n", + vtable, cmap, cmap->first, cmap->len); + + DEBUGASSERT(vtable && cmap); + + /* Only has 256 entries. */ + + if (cmap->first + cmap->len > IMXRT_LCDIF_LUT_ENTRY_NUM) + { + return ERROR; + } + + putreg32(cmap->first, IMXRT_LCDIF_LUT0_ADDR); + + for (n = 0; n < cmap->len; n++) + { + +#if defined (CONFIG_IMXRT_LCD_OUTPUT_24) + putreg32((uint32_t)0xff000000 | + ((uint32_t)cmap->red[n] << 16) | + ((uint32_t)cmap->green[n] << 8) | + ((uint32_t)cmap->blue[n] << 0), + IMXRT_LCDIF_LUT0_DATA); +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_18) + putreg32((uint32_t)0xfffc0000 | + (((uint32_t)cmap->red[n] & 0xfc) << 10) | + (((uint32_t)cmap->green[n] & 0xfc) << 4) | + (((uint32_t)cmap->blue[n] & 0xfc) >> 2), + IMXRT_LCDIF_LUT0_DATA); +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_16) + putreg32((uint32_t)0xffff0000 | + (((uint32_t)cmap->red[n] & 0xf8) << 8) | + (((uint32_t)cmap->green[n] & 0xfc) << 3) | + (((uint32_t)cmap->blue[n] & 0xf8) >> 3), + IMXRT_LCDIF_LUT0_DATA); +#endif + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: imxrt_lcd_reset + ****************************************************************************/ + +static void imxrt_lcdreset(void) +{ + volatile uint32_t i = IMXRT_LCD_RESET_DELAY; + + /* Disable the clock gate. */ + + putreg32(LCDIF_CTRL_CLKGATE_MASK, IMXRT_LCDIF_CTRL_CLR); + + /* Confirm the clock gate is disabled. */ + + while ((getreg32(IMXRT_LCDIF_CTRL) & LCDIF_CTRL_CLKGATE_MASK) != 0) + { + } + + /* Reset the block. */ + + putreg32(LCDIF_CTRL_SFTRST_MASK, IMXRT_LCDIF_CTRL_SET); + + /* Confirm the reset bit is set. */ + + while ((getreg32(IMXRT_LCDIF_CTRL) & LCDIF_CTRL_SFTRST_MASK) == 0) + { + } + + /* Delay for the reset. */ + + while (i--) + { + } + + /* Bring the module out of reset. */ + + putreg32(LCDIF_CTRL_SFTRST_MASK, IMXRT_LCDIF_CTRL_CLR); + + /* Disable the clock gate. */ + + putreg32(LCDIF_CTRL_CLKGATE_MASK, IMXRT_LCDIF_CTRL_CLR); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_fbinitialize + * + * Description: + * Initialize the framebuffer video hardware associated with the display. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +int up_fbinitialize(int display) +{ + +#if defined (CONFIG_IMXRT_LCD_INPUT_BPP8_LUT) || defined (CONFIG_IMXRT_LCD_INPUT_BPP8) + uint32_t n; +#endif + + /* Configure pins + * + * LCD panel data. Pins used depend on the panel configuration: + */ + + lcdinfo("Configuring pins\n"); + +#if defined(CONFIG_IMXRT_LCD_OUTPUT_24) + + imxrt_config_gpio(GPIO_LCD_DATA23); + imxrt_config_gpio(GPIO_LCD_DATA22); + imxrt_config_gpio(GPIO_LCD_DATA21); + imxrt_config_gpio(GPIO_LCD_DATA20); + imxrt_config_gpio(GPIO_LCD_DATA19); + imxrt_config_gpio(GPIO_LCD_DATA18); + +#endif +#if defined(CONFIG_IMXRT_LCD_OUTPUT_24) || \ + defined(CONFIG_IMXRT_LCD_OUTPUT_18) + + imxrt_config_gpio(GPIO_LCD_DATA17); + imxrt_config_gpio(GPIO_LCD_DATA16); + +#endif +#if defined(CONFIG_IMXRT_LCD_OUTPUT_24) || \ + defined(CONFIG_IMXRT_LCD_OUTPUT_18) || \ + defined(CONFIG_IMXRT_LCD_OUTPUT_16) + + imxrt_config_gpio(GPIO_LCD_DATA15); + imxrt_config_gpio(GPIO_LCD_DATA14); + imxrt_config_gpio(GPIO_LCD_DATA13); + imxrt_config_gpio(GPIO_LCD_DATA12); + imxrt_config_gpio(GPIO_LCD_DATA11); + imxrt_config_gpio(GPIO_LCD_DATA10); + imxrt_config_gpio(GPIO_LCD_DATA09); + imxrt_config_gpio(GPIO_LCD_DATA08); + +#endif + + imxrt_config_gpio(GPIO_LCD_DATA07); + imxrt_config_gpio(GPIO_LCD_DATA06); + imxrt_config_gpio(GPIO_LCD_DATA05); + imxrt_config_gpio(GPIO_LCD_DATA04); + imxrt_config_gpio(GPIO_LCD_DATA03); + imxrt_config_gpio(GPIO_LCD_DATA02); + imxrt_config_gpio(GPIO_LCD_DATA01); + imxrt_config_gpio(GPIO_LCD_DATA00); + + /* Other pins */ + + imxrt_config_gpio(GPIO_LCD_ENABLE); + imxrt_config_gpio(GPIO_LCD_HSYNC); + imxrt_config_gpio(GPIO_LCD_VSYNC); + imxrt_config_gpio(GPIO_LCD_CLK); + + lcdinfo("Enable clocking to the LCD controller\n"); + + /* Enable clocking to the LCD peripheral */ + + imxrt_clockall_pxp(); + + imxrt_clockall_lcd(); + + imxrt_clockall_lcdif_pix(); + + /* Reset the LCD */ + + imxrt_lcdinitialize(); + + imxrt_lcdreset(); + + lcdinfo("Configuring the LCD controller\n"); + + putreg32(pixelFormat.regCtrl | dataBus | + LCDIF_CTRL_DOTCLK_MODE_MASK | + LCDIF_CTRL_BYPASS_COUNT_MASK | + LCDIF_CTRL_MASTER_MASK, IMXRT_LCDIF_CTRL); + + putreg32(pixelFormat.regCtrl1, IMXRT_LCDIF_CTRL1); + + putreg32((CONFIG_IMXRT_LCD_VHEIGHT << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT) | + (CONFIG_IMXRT_LCD_HWIDTH << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT), + IMXRT_LCDIF_TRANSFER_COUNT); + + putreg32(LCDIF_VDCTRL0_ENABLE_PRESENT_MASK | + LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK | + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK | + VSYNC_POL | HSYNC_POL | DATAEN_POL | DATA_EDGE | + CONFIG_IMXRT_LCD_VPULSE, + IMXRT_LCDIF_VDCTRL0); + + putreg32(CONFIG_IMXRT_LCD_VPULSE + CONFIG_IMXRT_LCD_VHEIGHT + + CONFIG_IMXRT_LCD_VFRONTPORCH + CONFIG_IMXRT_LCD_VBACKPORCH, + IMXRT_LCDIF_VDCTRL1); + + putreg32((CONFIG_IMXRT_LCD_HPULSE << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT) | + ((CONFIG_IMXRT_LCD_HFRONTPORCH + CONFIG_IMXRT_LCD_HBACKPORCH + + CONFIG_IMXRT_LCD_HWIDTH + CONFIG_IMXRT_LCD_HPULSE) + << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT), + IMXRT_LCDIF_VDCTRL2); + + putreg32(((CONFIG_IMXRT_LCD_HBACKPORCH + CONFIG_IMXRT_LCD_HPULSE) + << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT) | + ((CONFIG_IMXRT_LCD_VBACKPORCH + CONFIG_IMXRT_LCD_VPULSE) + << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT), + IMXRT_LCDIF_VDCTRL3); + + putreg32(LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK | + (CONFIG_IMXRT_LCD_HWIDTH << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT), + IMXRT_LCDIF_VDCTRL4); + +#ifdef CONFIG_IMXRT_LCD_BGR + /* Swap red and blue. The colors will be 0x00RRGGBB, not 0x00bbGGRR. */ + + /* TODO */ +#endif + +#if defined (CONFIG_IMXRT_LCD_INPUT_BPP8_LUT) || defined (CONFIG_IMXRT_LCD_INPUT_BPP8) + + putreg32(0, IMXRT_LCDIF_LUT0_ADDR); + + for (n = 0; n < IMXRT_LCDIF_LUT_ENTRY_NUM; n++) + { + uint8_t red; + uint8_t green; + uint8_t blue; + + red = (n << 0) & 0xe0; + green = (n << 3) & 0xe0; + blue = (n << 6) & 0xc0; + +#if defined (CONFIG_IMXRT_LCD_OUTPUT_24) + putreg32((uint32_t)0xff000000 | + ((uint32_t)red << 16) | + ((uint32_t)green << 8) | + ((uint32_t)blue << 0), + IMXRT_LCDIF_LUT0_DATA); +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_18) + putreg32((uint32_t)0xfffc0000 | + (((uint32_t)red & 0xfc) << 10) | + (((uint32_t)green & 0xfc) << 4) | + (((uint32_t)blue & 0xfc) >> 2), + IMXRT_LCDIF_LUT0_DATA); +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_16) + putreg32((uint32_t)0xffff0000 | + (((uint32_t)red & 0xf8) << 8) | + (((uint32_t)green & 0xfc) << 3) | + (((uint32_t)blue & 0xf8) >> 3), + IMXRT_LCDIF_LUT0_DATA); +#endif + } + + putreg32(0, IMXRT_LCDIF_LUT_CTRL); + +#endif + + putreg32(CONFIG_IMXRT_LCD_VRAMBASE, IMXRT_LCDIF_CUR_BUF); + putreg32(CONFIG_IMXRT_LCD_VRAMBASE, IMXRT_LCDIF_NEXT_BUF); + + /* Clear the display */ + + imxrt_lcdclear(CONFIG_IMXRT_LCD_BACKCOLOR); + +#ifdef CONFIG_IMXRT_LCD_BACKLIGHT + + /* Turn on the back light */ + + imxrt_backlight(true); + +#endif + + putreg32(LCDIF_CTRL_RUN_MASK | LCDIF_CTRL_DOTCLK_MODE_MASK, + IMXRT_LCDIF_CTRL_SET); + + return OK; +} + +/**************************************************************************** + * Name: up_fbgetvplane + * + * Description: + * Return a a reference to the framebuffer object for the specified video + * plane of the specified plane. Many OSDs support multiple planes of + * video. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * vplane - Identifies the plane being queried. + * + * Returned Value: + * A non-NULL pointer to the frame buffer access structure is returned on + * success; NULL is returned on any failure. + * + ****************************************************************************/ + +FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane) +{ + lcdinfo("vplane: %d\n", vplane); + if (vplane == 0) + { + return &g_fbobject; + } + else + { + return NULL; + } +} + +/**************************************************************************** + * Name: up_fbuninitialize + * + * Description: + * Uninitialize the framebuffer support for the specified display. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_fbuninitialize(int display) +{ + /* We assume there is only one use of the LCD and so we do not need to + * worry about mutually exclusive access to the LCD hardware. + */ + +#ifdef CONFIG_IMXRT_LCD_BACKLIGHT + /* Turn off the back light */ + + imxrt_backlight(false); +#endif + + /* Disable the clock gate. */ + + putreg32(LCDIF_CTRL_CLKGATE_MASK, IMXRT_LCDIF_CTRL_CLR); + + /* Disable clocking to the LCD peripheral */ + + imxrt_clockoff_lcdif_pix(); + + imxrt_clockoff_lcd(); + +} + +/**************************************************************************** + * Name: imxrt_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the IMXRT. Clearing + * the display in the normal way by writing a sequences of runs that + * covers the entire display can be slow. Here the dispaly is cleared by + * simply setting all VRAM memory to the specified color. + * + ****************************************************************************/ + +void imxrt_lcdclear(nxgl_mxpixel_t color) +{ + int i; + int size; + + size = CONFIG_IMXRT_LCD_HWIDTH * CONFIG_IMXRT_LCD_VHEIGHT; + + #if IMXRT_BPP > 24 + uint32_t *dest = (uint32_t *)CONFIG_IMXRT_LCD_VRAMBASE; + + lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n", + color, CONFIG_IMXRT_LCD_VRAMBASE, + size * sizeof(uint32_t)); + +#elif IMXRT_BPP > 16 + uint32_t *dest = (uint32_t *)CONFIG_IMXRT_LCD_VRAMBASE; + + size = (size * 3) >> 2; + + lcdinfo("Clearing display: color=%06x VRAM=%08x size=%d\n", + color, CONFIG_IMXRT_LCD_VRAMBASE, + size * sizeof(uint32_t)); + +#elif IMXRT_BPP > 8 + uint16_t *dest = (uint16_t *)CONFIG_IMXRT_LCD_VRAMBASE; + + lcdinfo("Clearing display: color=%04x VRAM=%08x size=%d\n", + color, CONFIG_IMXRT_LCD_VRAMBASE, + size * sizeof(uint16_t)); +#else + uint8_t *dest = (uint8_t *)CONFIG_IMXRT_LCD_VRAMBASE; + + lcdinfo("Clearing display: color=%02x VRAM=%08x size=%d\n", + color, CONFIG_IMXRT_LCD_VRAMBASE, + size * sizeof(uint8_t)); +#endif + + for (i = 0; i < size; i++) + { + *dest++ = color; + } +} diff --git a/arch/arm/src/imxrt/imxrt_lcd.h b/arch/arm/src/imxrt/imxrt_lcd.h new file mode 100644 index 0000000000..a383f5fcf9 --- /dev/null +++ b/arch/arm/src/imxrt/imxrt_lcd.h @@ -0,0 +1,214 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_lcd.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Johannes Schock + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The I.MX RT LCD driver uses the common framebuffer interfaces declared in + * include/nuttx/video/fb.h. + */ + +#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_LCD_H +#define __ARCH_ARM_SRC_IMXRT_IMXRT_LCD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip/imxrt_lcd.h" + +#include + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration */ + +#ifndef IMXRT_LCD_VIDEO_PLL_FREQ +# define IMXRT_LCD_VIDEO_PLL_FREQ 92000000 +#endif + +/* Base address of the video RAM frame buffer */ + +#ifndef CONFIG_IMXRT_LCD_VRAMBASE +# define CONFIG_IMXRT_LCD_VRAMBASE (0x20240000) +#endif + +/* LCD refresh rate */ + +#ifndef CONFIG_IMXRT_LCD_REFRESH_FREQ +# define CONFIG_IMXRT_LCD_REFRESH_FREQ (60) /* Hz */ +#endif + +#undef IMXRT_BPP +#undef IMXRT_COLOR_FMT + +/* Bits per pixel / color format */ + +#if defined (CONFIG_IMXRT_LCD_INPUT_BPP8_LUT) +# define IMXRT_BPP 8 +# define IMXRT_COLOR_FMT FB_FMT_RGB8 +#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP8) +# define IMXRT_BPP 8 +# define IMXRT_COLOR_FMT FB_FMT_RGB8_332 +#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP15) +# define IMXRT_BPP 16 +# define IMXRT_COLOR_FMT FB_FMT_RGB16_555 +#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP16) +# define IMXRT_BPP 16 +# define IMXRT_COLOR_FMT FB_FMT_RGB16_565 +#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP24) +# define IMXRT_BPP 24 +# define IMXRT_COLOR_FMT FB_FMT_RGB24 +#elif defined (CONFIG_IMXRT_LCD_INPUT_BPP32) +# define IMXRT_BPP 32 +# define IMXRT_COLOR_FMT FB_FMT_RGB32 +#else +# define CONFIG_IMXRT_LCD_INPUT_BPP16 +# define IMXRT_BPP 16 +# define IMXRT_COLOR_FMT FB_FMT_RGB16_565 +#endif + +#if defined (CONFIG_IMXRT_LCD_OUTPUT_8) +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_16) +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_18) +#elif defined (CONFIG_IMXRT_LCD_OUTPUT_24) +#else +# define CONFIG_IMXRT_LCD_OUTPUT_24 +#endif + +#ifndef CONFIG_IMXRT_LCD_BACKCOLOR +# define CONFIG_IMXRT_LCD_BACKCOLOR 0x0 +#endif + +#ifndef CONFIG_IMXRT_LCD_HWIDTH +# define CONFIG_IMXRT_LCD_HWIDTH 480 +#endif + +#ifndef CONFIG_IMXRT_LCD_HPULSE +# define CONFIG_IMXRT_LCD_HPULSE 41 +#endif + +#ifndef CONFIG_IMXRT_LCD_HFRONTPORCH +# define CONFIG_IMXRT_LCD_HFRONTPORCH 4 +#endif + +#ifndef CONFIG_IMXRT_LCD_HBACKPORCH +# define CONFIG_IMXRT_LCD_HBACKPORCH 8 +#endif + +#ifndef CONFIG_IMXRT_LCD_VHEIGHT +# define CONFIG_IMXRT_LCD_VHEIGHT 272 +#endif + +#ifndef CONFIG_IMXRT_LCD_VPULSE +# define CONFIG_IMXRT_LCD_VPULSE 10 +#endif + +#ifndef CONFIG_IMXRT_LCD_VFRONTPORCH +# define CONFIG_IMXRT_LCD_VFRONTPORCH 4 +#endif + +#ifndef CONFIG_IMXRT_LCD_VBACKPORCH +# define CONFIG_IMXRT_LCD_VBACKPORCH 2 +#endif + +#ifdef CONFIG_IMXRT_VSYNC_ACTIVE_HIGH +# define VSYNC_POL LCDIF_VDCTRL0_VSYNC_POL_MASK +#else +# define VSYNC_POL 0 +#endif + +#ifdef CONFIG_IMXRT_HSYNC_ACTIVE_HIGH +# define HSYNC_POL LCDIF_VDCTRL0_HSYNC_POL_MASK +#else +# define HSYNC_POL 0 +#endif + +#ifdef CONFIG_IMXRT_DATAEN_ACTIVE_HIGH +# define DATAEN_POL LCDIF_VDCTRL0_ENABLE_POL_MASK +#else +# define DATAEN_POL 0 +#endif + +#ifdef CONFIG_IMXRT_DATA_RISING_EDGE +# define DATA_EDGE LCDIF_VDCTRL0_DOTCLK_POL_MASK +#else +# define DATA_EDGE 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: IMXRT_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the I.MX RT. Clearing + * the display in the normal way by writing a sequences of runs that + * covers the entire display can be slow. Here the display is cleared by + * simply setting all VRAM memory to the specified color. + * + ****************************************************************************/ + +void imxrt_lcdclear(nxgl_mxpixel_t color); + +/**************************************************************************** + * Name: imxrt_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * + ****************************************************************************/ + +void imxrt_lcdinitialize(void); + +/**************************************************************************** + * Name: IMXRT_backlight + * + * Description: + * If CONFIG_IMXRT_LCD_BACKLIGHT is defined, then the board-specific logic + * must provide this interface to turn the backlight on and off. + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_LCD_BACKLIGHT +void imxrt_backlight(bool blon); +#endif + +#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_LCD_H */ diff --git a/configs/imxrt1050-evk/Kconfig b/configs/imxrt1050-evk/Kconfig index 710420308c..8214387300 100644 --- a/configs/imxrt1050-evk/Kconfig +++ b/configs/imxrt1050-evk/Kconfig @@ -17,4 +17,10 @@ config IMXRT1050_EVK_QSPI_FLASH endchoice # Boot Flash +config IMXRT1050_EVK_SDRAM + bool "Enable SDRAM" + default n + ---help--- + Activate DCD configuration of SDRAM + endif diff --git a/configs/imxrt1050-evk/scripts/memory.ld b/configs/imxrt1050-evk/scripts/memory.ld index 061d16f70b..59cccb2187 100644 --- a/configs/imxrt1050-evk/scripts/memory.ld +++ b/configs/imxrt1050-evk/scripts/memory.ld @@ -36,7 +36,7 @@ /* The i.MXRT1050-EVK has 64Mb of Hyper FLASH beginning at address, * 0x0060:0000, 512Kb of DTCM RAM beginning at 0x2000:0000, and 512Kb OCRAM * beginning at 0x2020:0000. Neither DTCM or SDRAM are used in this - * configuratin. + * configuration. * * The user and kernel space partitions will be spanned with a single * region of size 2**n bytes. As a consequence, as the partitions increase diff --git a/configs/imxrt1050-evk/src/Makefile b/configs/imxrt1050-evk/src/Makefile index 914aba2635..108f9b81c1 100644 --- a/configs/imxrt1050-evk/src/Makefile +++ b/configs/imxrt1050-evk/src/Makefile @@ -1,7 +1,7 @@ ############################################################################ # configs/imxrt1050-evk/src/Makefile # -# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -66,6 +66,10 @@ ifeq ($(CONFIG_IMXRT_LPSPI),y) CSRCS += imxrt_spi.c endif +ifeq ($(CONFIG_IMXRT_LCD),y) +CSRCS += imxrt_lcd.c +endif + ifeq ($(CONFIG_MMCSD_SPI),y) CSRCS += imxrt_mmcsd_spi.c endif @@ -74,4 +78,8 @@ ifeq ($(CONFIG_DEV_GPIO),y) CSRCS += imxrt_gpio.c endif +ifeq ($(CONFIG_IMXRT1050_EVK_SDRAM),y) +CSRCS += imxrt_sdram_ini_dcd.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/imxrt1050-evk/src/imxrt1050-evk.h b/configs/imxrt1050-evk/src/imxrt1050-evk.h index 94600c4da6..634d394632 100644 --- a/configs/imxrt1050-evk/src/imxrt1050-evk.h +++ b/configs/imxrt1050-evk/src/imxrt1050-evk.h @@ -105,6 +105,14 @@ #define GPIO_LED (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT1 | \ GPIO_PIN9 | IOMUX_LED) +/* Backlight of LCD */ + +#define IOMUX_LCD_BL (IOMUX_PULL_NONE | IOMUX_CMOS_OUTPUT | \ + IOMUX_DRIVE_40OHM | IOMUX_SPEED_MEDIUM | \ + IOMUX_SLEW_SLOW) +#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT2 | \ + GPIO_PIN31 | IOMUX_LCD_BL) + /* Buttons * * The IMXRT board has one external user button diff --git a/configs/imxrt1050-evk/src/imxrt_bringup.c b/configs/imxrt1050-evk/src/imxrt_bringup.c index c622feadc6..0bcf97c12d 100644 --- a/configs/imxrt1050-evk/src/imxrt_bringup.c +++ b/configs/imxrt1050-evk/src/imxrt_bringup.c @@ -45,6 +45,7 @@ #include #include +#include #include #include @@ -188,6 +189,16 @@ int imxrt_bringup(void) } #endif +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/imxrt1050-evk/src/imxrt_flexspi_nor_boot.c b/configs/imxrt1050-evk/src/imxrt_flexspi_nor_boot.c index c11518efdb..4a048170fb 100644 --- a/configs/imxrt1050-evk/src/imxrt_flexspi_nor_boot.c +++ b/configs/imxrt1050-evk/src/imxrt_flexspi_nor_boot.c @@ -44,20 +44,20 @@ ****************************************************************************/ __attribute__((section(".boot_hdr.ivt"))) -const struct ivt_s image_vector_table = +const struct ivt_s g_image_vector_table = { IVT_HEADER, /* IVT Header */ 0x60002000, /* Image Entry Function */ IVT_RSVD, /* Reserved = 0 */ (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)&g_image_vector_table, /* Pointer to IVT Self (absolute address */ (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ IVT_RSVD /* Reserved = 0 */ }; __attribute__((section(".boot_hdr.boot_data"))) -const struct boot_data_s boot_data = +const struct boot_data_s g_boot_data = { FLASH_BASE, /* boot start location */ (FLASH_END - FLASH_BASE), /* size */ diff --git a/configs/imxrt1050-evk/src/imxrt_flexspi_nor_boot.h b/configs/imxrt1050-evk/src/imxrt_flexspi_nor_boot.h index abe1c698c5..c5de64a8f2 100644 --- a/configs/imxrt1050-evk/src/imxrt_flexspi_nor_boot.h +++ b/configs/imxrt1050-evk/src/imxrt_flexspi_nor_boot.h @@ -77,8 +77,13 @@ #define FLASH_END 0x7f7fffff #define SCLK 1 -#define DCD_ADDRESS 0 -#define BOOT_DATA_ADDRESS &boot_data +#ifdef CONFIG_IMXRT1050_EVK_SDRAM +# define DCD_ADDRESS &g_dcd_data +#else +# define DCD_ADDRESS 0 +#endif + +#define BOOT_DATA_ADDRESS &g_boot_data #define CSF_ADDRESS 0 #define PLUGIN_FLAG (uint32_t)0 @@ -143,6 +148,10 @@ struct boot_data_s * Public Data ****************************************************************************/ -extern const struct boot_data_s boot_data; +extern const struct boot_data_s g_boot_data; + +#ifdef CONFIG_IMXRT1050_EVK_SDRAM +extern const uint8_t g_dcd_data[]; +#endif #endif /* __CONFIGS_IMXRT1050_EVK_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */ diff --git a/configs/imxrt1050-evk/src/imxrt_lcd.c b/configs/imxrt1050-evk/src/imxrt_lcd.c new file mode 100644 index 0000000000..e70032e338 --- /dev/null +++ b/configs/imxrt1050-evk/src/imxrt_lcd.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * configs/imxrt1050-evk/src/imxrt_lcd.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imxrt_lcd.h" +#include "imxrt_gpio.h" + +#include "imxrt1050-evk.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * + ****************************************************************************/ + +void imxrt_lcdinitialize(void) +{ + /* Configure the LCD backlight (and turn the backlight off) */ + + imxrt_config_gpio(GPIO_LCD_BL); +} + +/**************************************************************************** + * Name: imxrt_backlight + * + * Description: + * If CONFIG_IMXRT_LCD_BACKLIGHT is defined, then the board-specific + * logic must provide this interface to turn the backlight on and off. + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_LCD_BACKLIGHT +void imxrt_backlight(bool blon) +{ + imxrt_gpio_write(GPIO_LCD_BL, blon); /* High illuminates */ +} +#endif diff --git a/configs/imxrt1050-evk/src/imxrt_sdram_ini_dcd.c b/configs/imxrt1050-evk/src/imxrt_sdram_ini_dcd.c new file mode 100644 index 0000000000..83a4ecbd36 --- /dev/null +++ b/configs/imxrt1050-evk/src/imxrt_sdram_ini_dcd.c @@ -0,0 +1,1116 @@ +/***************************************************************************** + * configs/imxrt/src/imxrt_sdram_ini_dcd.c + * + * Copyright (C) 2017, NXP Semiconductors, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +#include "imxrt_flexspi_nor_boot.h" + +__attribute__((section(".boot_hdr.dcd_data"))) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const uint8_t g_dcd_data[] = +{ + /* 0000 */ dcd_tag_header, + 0x04, + 0x30, + 0x41, + 0xcc, + 0x03, + 0xac, + 0x04, + 0x40, + 0x0f, + 0xc0, + 0x68, + 0xff, + 0xff, + 0xff, + 0xff, + /* 0010 */ 0x40, + 0x0f, + 0xc0, + 0x6c, + 0xff, + 0xff, + 0xff, + 0xff, + 0x40, + 0x0f, + 0xc0, + 0x70, + 0xff, + 0xff, + 0xff, + 0xff, + /* 0020 */ 0x40, + 0x0f, + 0xc0, + 0x74, + 0xff, + 0xff, + 0xff, + 0xff, + 0x40, + 0x0f, + 0xc0, + 0x78, + 0xff, + 0xff, + 0xff, + 0xff, + /* 0030 */ 0x40, + 0x0f, + 0xc0, + 0x7c, + 0xff, + 0xff, + 0xff, + 0xff, + 0x40, + 0x0f, + 0xc0, + 0x80, + 0xff, + 0xff, + 0xff, + 0xff, + /* 0040 */ 0x40, + 0x0d, + 0x80, + 0x30, + 0x00, + 0x00, + 0x20, + 0x01, + 0x40, + 0x0d, + 0x81, + 0x00, + 0x00, + 0x1d, + 0x00, + 0x00, + /* 0050 */ 0x40, + 0x0f, + 0xc0, + 0x14, + 0x00, + 0x01, + 0x0d, + 0x40, + 0x40, + 0x1f, + 0x80, + 0x14, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0060 */ 0x40, + 0x1f, + 0x80, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x1c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0070 */ 0x40, + 0x1f, + 0x80, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x24, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0080 */ 0x40, + 0x1f, + 0x80, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x2c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0090 */ 0x40, + 0x1f, + 0x80, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x34, + 0x00, + 0x00, + 0x00, + 0x00, + /* 00a0 */ 0x40, + 0x1f, + 0x80, + 0x38, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x3c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 00b0 */ 0x40, + 0x1f, + 0x80, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + /* 00c0 */ 0x40, + 0x1f, + 0x80, + 0x48, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x4c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 00d0 */ 0x40, + 0x1f, + 0x80, + 0x50, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x54, + 0x00, + 0x00, + 0x00, + 0x00, + /* 00e0 */ 0x40, + 0x1f, + 0x80, + 0x58, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x5c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 00f0 */ 0x40, + 0x1f, + 0x80, + 0x60, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x64, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0100 */ 0x40, + 0x1f, + 0x80, + 0x68, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x6c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0110 */ 0x40, + 0x1f, + 0x80, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x74, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0120 */ 0x40, + 0x1f, + 0x80, + 0x78, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x7c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0130 */ 0x40, + 0x1f, + 0x80, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x84, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0140 */ 0x40, + 0x1f, + 0x80, + 0x88, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x8c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0150 */ 0x40, + 0x1f, + 0x80, + 0x90, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x94, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0160 */ 0x40, + 0x1f, + 0x80, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0x9c, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0170 */ 0x40, + 0x1f, + 0x80, + 0xa0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0xa4, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0180 */ 0x40, + 0x1f, + 0x80, + 0xa8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x80, + 0xac, + 0x00, + 0x00, + 0x00, + 0x00, + /* 0190 */ 0x40, + 0x1f, + 0x80, + 0xb0, + 0x00, + 0x00, + 0x00, + 0x10, + 0x40, + 0x1f, + 0x80, + 0xb4, + 0x00, + 0x00, + 0x00, + 0x00, + /* 01a0 */ 0x40, + 0x1f, + 0x80, + 0xb8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x1f, + 0x82, + 0x04, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 01b0 */ 0x40, + 0x1f, + 0x82, + 0x08, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x0c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 01c0 */ 0x40, + 0x1f, + 0x82, + 0x10, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x14, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 01d0 */ 0x40, + 0x1f, + 0x82, + 0x18, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x1c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 01e0 */ 0x40, + 0x1f, + 0x82, + 0x20, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x24, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 01f0 */ 0x40, + 0x1f, + 0x82, + 0x28, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x2c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0200 */ 0x40, + 0x1f, + 0x82, + 0x30, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x34, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0210 */ 0x40, + 0x1f, + 0x82, + 0x38, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x3c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0220 */ 0x40, + 0x1f, + 0x82, + 0x40, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x44, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0230 */ 0x40, + 0x1f, + 0x82, + 0x48, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x4c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0240 */ 0x40, + 0x1f, + 0x82, + 0x50, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x54, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0250 */ 0x40, + 0x1f, + 0x82, + 0x58, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x5c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0260 */ 0x40, + 0x1f, + 0x82, + 0x60, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x64, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0270 */ 0x40, + 0x1f, + 0x82, + 0x68, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x6c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0280 */ 0x40, + 0x1f, + 0x82, + 0x70, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x74, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 0290 */ 0x40, + 0x1f, + 0x82, + 0x78, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x7c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 02a0 */ 0x40, + 0x1f, + 0x82, + 0x80, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x84, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 02b0 */ 0x40, + 0x1f, + 0x82, + 0x88, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x8c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 02c0 */ 0x40, + 0x1f, + 0x82, + 0x90, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x94, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 02d0 */ 0x40, + 0x1f, + 0x82, + 0x98, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0x9c, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 02e0 */ 0x40, + 0x1f, + 0x82, + 0xa0, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x1f, + 0x82, + 0xa4, + 0x00, + 0x01, + 0x10, + 0xf9, + /* 02f0 */ 0x40, + 0x1f, + 0x82, + 0xa8, + 0x00, + 0x01, + 0x10, + 0xf9, + 0x40, + 0x2f, + 0x00, + 0x00, + 0x10, + 0x00, + 0x00, + 0x04, + /* 0300 */ 0x40, + 0x2f, + 0x00, + 0x08, + 0x00, + 0x03, + 0x05, + 0x24, + 0x40, + 0x2f, + 0x00, + 0x0c, + 0x06, + 0x03, + 0x05, + 0x24, + /* 0310 */ 0x40, + 0x2f, + 0x00, + 0x10, + 0x80, + 0x00, + 0x00, + 0x1b, + 0x40, + 0x2f, + 0x00, + 0x14, + 0x82, + 0x00, + 0x00, + 0x1b, + /* 0320 */ 0x40, + 0x2f, + 0x00, + 0x18, + 0x84, + 0x00, + 0x00, + 0x1b, + 0x40, + 0x2f, + 0x00, + 0x1c, + 0x86, + 0x00, + 0x00, + 0x1b, + /* 0330 */ 0x40, + 0x2f, + 0x00, + 0x20, + 0x90, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2f, + 0x00, + 0x24, + 0xa0, + 0x00, + 0x00, + 0x19, + /* 0340 */ 0x40, + 0x2f, + 0x00, + 0x28, + 0xa8, + 0x00, + 0x00, + 0x17, + 0x40, + 0x2f, + 0x00, + 0x2c, + 0xa9, + 0x00, + 0x00, + 0x1b, + /* 0350 */ 0x40, + 0x2f, + 0x00, + 0x30, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2f, + 0x00, + 0x04, + 0x00, + 0x00, + 0x79, + 0xa8, + /* 0360 */ 0x40, + 0x2f, + 0x00, + 0x40, + 0x00, + 0x00, + 0x0f, + 0x31, + 0x40, + 0x2f, + 0x00, + 0x44, + 0x00, + 0x65, + 0x29, + 0x22, + /* 0370 */ 0x40, + 0x2f, + 0x00, + 0x48, + 0x00, + 0x01, + 0x09, + 0x20, + 0x40, + 0x2f, + 0x00, + 0x4c, + 0x50, + 0x21, + 0x0a, + 0x08, + /* 0380 */ 0x40, + 0x2f, + 0x00, + 0x80, + 0x00, + 0x00, + 0x00, + 0x21, + 0x40, + 0x2f, + 0x00, + 0x84, + 0x00, + 0x88, + 0x88, + 0x88, + /* 0390 */ 0x40, + 0x2f, + 0x00, + 0x94, + 0x00, + 0x00, + 0x00, + 0x02, + 0x40, + 0x2f, + 0x00, + 0x98, + 0x00, + 0x00, + 0x00, + 0x00, + /* 03a0 */ 0x40, + 0x2f, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2f, + 0x00, + 0x9c, + 0xa5, + 0x5a, + 0x00, + 0x0f, + /* 03b0 */ 0xcf, + 0x00, + 0x0c, + 0x1c, + 0x40, + 0x2f, + 0x00, + 0x3c, + 0x00, + 0x00, + 0x00, + 0x01, + 0xcc, + 0x00, + 0x14, + 0x04, + /* 03c0 */ 0x40, + 0x2f, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2f, + 0x00, + 0x9c, + 0xa5, + 0x5a, + 0x00, + 0x0c, + /* 03d0 */ 0xcf, + 0x00, + 0x0c, + 0x1c, + 0x40, + 0x2f, + 0x00, + 0x3c, + 0x00, + 0x00, + 0x00, + 0x01, + 0xcc, + 0x00, + 0x14, + 0x04, + /* 03e0 */ 0x40, + 0x2f, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + 0x40, + 0x2f, + 0x00, + 0x9c, + 0xa5, + 0x5a, + 0x00, + 0x0c, + /* 03f0 */ 0xcf, + 0x00, + 0x0c, + 0x1c, + 0x40, + 0x2f, + 0x00, + 0x3c, + 0x00, + 0x00, + 0x00, + 0x01, + 0xcc, + 0x00, + 0x1c, + 0x04, + /* 0400 */ 0x40, + 0x2f, + 0x00, + 0xa0, + 0x00, + 0x00, + 0x00, + 0x33, + 0x40, + 0x2f, + 0x00, + 0x90, + 0x80, + 0x00, + 0x00, + 0x00, + /* 0410 */ 0x40, + 0x2f, + 0x00, + 0x9c, + 0xa5, + 0x5a, + 0x00, + 0x0a, + 0xcf, + 0x00, + 0x0c, + 0x1c, + 0x40, + 0x2f, + 0x00, + 0x3c, + /* 0420 */ 0x00, + 0x00, + 0x00, + 0x01, + 0xcc, + 0x00, + 0x0c, + 0x04, + 0x40, + 0x2f, + 0x00, + 0x4c, + 0x50, + 0x21, + 0x0a, + 0x09, +};