From b96a141e8a6ca8510fc58f5f8f2cbee06a64b6fc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 26 May 2015 10:39:38 -0600 Subject: [PATCH] SAML21-Xlplained: Add options to enable XOSC32K and to use it as the DFLL source; NSH configure now uses DFLL with OSC16M source --- arch/arm/src/samdl/saml_clockconfig.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/samdl/saml_clockconfig.c b/arch/arm/src/samdl/saml_clockconfig.c index c9bcd74572..dbfc77b782 100644 --- a/arch/arm/src/samdl/saml_clockconfig.c +++ b/arch/arm/src/samdl/saml_clockconfig.c @@ -512,16 +512,12 @@ static inline void sam_xosc32k_config(void) OSC32KCTRL_XOSC32K_EN1K | OSC32KCTRL_XOSC32K_RUNSTDBY | OSC32KCTRL_XOSC32K_ONDEMAND | OSC32KCTRL_XOSC32K_STARTUP_MASK | OSC32KCTRL_XOSC32K_WRTLOCK); - regval |= BOARD_XOSC32K_STARTUPTIME + regval |= BOARD_XOSC32K_STARTUPTIME; #ifdef BOARD_XOSC32K_ISCRYSTAL regval |= OSC32KCTRL_XOSC32K_XTALEN; #endif -#ifdef BOARD_XOSC32K_AAMPEN - regval |= OSC32KCTRL_XOSC32K_AAMPEN; -#endif - #ifdef BOARD_XOSC32K_EN1KHZ regval |= OSC32KCTRL_XOSC32K_EN1K; #endif @@ -543,7 +539,7 @@ static inline void sam_xosc32k_config(void) /* Wait for XOSC32K to be ready */ - while ((getreg32(SAM_OSC32CTRL_STATUS) & OSC32KCTRL_INT_XOSC32KRDY) == 0); + while ((getreg32(SAM_OSC32KCTRL_STATUS) & OSC32KCTRL_INT_XOSC32KRDY) == 0); #ifdef BOARD_XOSC32K_ONDEMAND /* Set the on-demand bit */