From b9816723a54764668ed69d7894d32bb8a8ba77c8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 5 Jan 2014 15:49:06 -0600 Subject: [PATCH] Add ARMv7-A syscall.h header file --- arch/arm/include/armv7-a/syscall.h | 242 +++++++++++++++++++++++++++++ arch/arm/include/syscall.h | 4 +- 2 files changed, 245 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/armv7-a/syscall.h diff --git a/arch/arm/include/armv7-a/syscall.h b/arch/arm/include/armv7-a/syscall.h new file mode 100644 index 0000000000..d4028688e8 --- /dev/null +++ b/arch/arm/include/armv7-a/syscall.h @@ -0,0 +1,242 @@ +/**************************************************************************** + * arch/arm/include/armv-7a/syscall.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H +#define __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +#define SYS_syscall 0x900001 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* SWI with SYS_ call number and no parameters */ + +static inline uintptr_t sys_call0(unsigned int nbr) +{ + register long reg0 __asm__("r0") = (long)(nbr); + + __asm__ __volatile__ + ( + "swi %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0) + : "memory" + ); + + return reg0; +} + +/* SWI with SYS_ call number and one parameter */ + +static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "swi %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1) + : "memory" + ); + + return reg0; +} + +/* SWI with SYS_ call number and two parameters */ + +static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "swi %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2) + : "memory" + ); + + return reg0; +} + +/* SWI with SYS_ call number and three parameters */ + +static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg3 __asm__("r3") = (long)(parm3); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "swi %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3) + : "memory" + ); + + return reg0; +} + +/* SWI with SYS_ call number and four parameters */ + +static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg4 __asm__("r4") = (long)(parm4); + register long reg3 __asm__("r3") = (long)(parm3); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "swi %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4) + : "memory" + ); + + return reg0; +} + +/* SWI with SYS_ call number and five parameters */ + +static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4, uintptr_t parm5) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg5 __asm__("r5") = (long)(parm5); + register long reg4 __asm__("r4") = (long)(parm4); + register long reg3 __asm__("r3") = (long)(parm3); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "swi %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4), "r"(reg5) + : "memory" + ); + + return reg0; +} + +/* SWI with SYS_ call number and six parameters */ + +static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4, uintptr_t parm5, + uintptr_t parm6) +{ + register long reg0 __asm__("r0") = (long)(nbr); + register long reg6 __asm__("r6") = (long)(parm6); + register long reg5 __asm__("r5") = (long)(parm5); + register long reg4 __asm__("r4") = (long)(parm4); + register long reg3 __asm__("r3") = (long)(parm3); + register long reg2 __asm__("r2") = (long)(parm2); + register long reg1 __asm__("r1") = (long)(parm1); + + __asm__ __volatile__ + ( + "swi %1" + : "=r"(reg0) + : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), + "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6) + : "memory" + ); + + return reg0; +} + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H */ diff --git a/arch/arm/include/syscall.h b/arch/arm/include/syscall.h index a11fc2ba37..446228038f 100644 --- a/arch/arm/include/syscall.h +++ b/arch/arm/include/syscall.h @@ -46,7 +46,9 @@ /* Include ARM architecture-specific syscall macros */ -#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) +#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) +# include +#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) # include #elif defined(CONFIG_ARCH_CORTEXM0) # include