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EFM32, STM32 (FS/HS), STM32F7, and STM32L4 OTGFS/HS: Th epin_configure() function used the same eptype as the TxFIFO number for all endpoints. This should probably be the physical EP number, not the EP type. Suggested by Key Two.

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This commit is contained in:
Gregory Nutt 2018-10-02 10:10:56 -06:00
parent a90e031028
commit b9823ce1d7
5 changed files with 5 additions and 5 deletions
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2
arch/arm/src/efm32/efm32_usbdev.c
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@ -3929,7 +3929,7 @@ static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
_USB_DIEPCTL_TXFNUM_MASK);
regval |= mpsiz;
regval |= (eptype << _USB_DIEPCTL_EPTYPE_SHIFT);
regval |= (eptype << _USB_DIEPCTL_TXFNUM_SHIFT);
regval |= (privep->epphy << _USB_DIEPCTL_TXFNUM_SHIFT);
regval |= (USB_DIEPCTL_SETD0PIDEF | USB_DIEPCTL_USBACTEP);
efm32_putreg(regval, regaddr);

2
arch/arm/src/stm32/stm32_otgfsdev.c
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@ -3980,7 +3980,7 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | OTGFS_DIEPCTL_TXFNUM_MASK);
regval |= mpsiz;
regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT);
regval |= (eptype << OTGFS_DIEPCTL_TXFNUM_SHIFT);
regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT);
regval |= (OTGFS_DIEPCTL_SD0PID | OTGFS_DIEPCTL_USBAEP);
stm32_putreg(regval, regaddr);

2
arch/arm/src/stm32/stm32_otghsdev.c
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@ -3930,7 +3930,7 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
regval &= ~(OTGHS_DIEPCTL_MPSIZ_MASK | OTGHS_DIEPCTL_EPTYP_MASK | OTGHS_DIEPCTL_TXFNUM_MASK);
regval |= mpsiz;
regval |= (eptype << OTGHS_DIEPCTL_EPTYP_SHIFT);
regval |= (eptype << OTGHS_DIEPCTL_TXFNUM_SHIFT);
regval |= (privep->epphy << OTGHS_DIEPCTL_TXFNUM_SHIFT);
regval |= (OTGHS_DIEPCTL_SD0PID | OTGHS_DIEPCTL_USBAEP);
stm32_putreg(regval, regaddr);

2
arch/arm/src/stm32f7/stm32_otgdev.c
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@ -4000,7 +4000,7 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep,
OTG_DIEPCTL_TXFNUM_MASK);
regval |= mpsiz;
regval |= (eptype << OTG_DIEPCTL_EPTYP_SHIFT);
regval |= (eptype << OTG_DIEPCTL_TXFNUM_SHIFT);
regval |= (privep->epphy << OTG_DIEPCTL_TXFNUM_SHIFT);
regval |= (OTG_DIEPCTL_SD0PID | OTG_DIEPCTL_USBAEP);
stm32_putreg(regval, regaddr);

2
arch/arm/src/stm32l4/stm32l4_otgfsdev.c
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@ -4035,7 +4035,7 @@ static int stm32l4_epin_configure(FAR struct stm32l4_ep_s *privep, uint8_t eptyp
regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | OTGFS_DIEPCTL_TXFNUM_MASK);
regval |= mpsiz;
regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT);
regval |= (eptype << OTGFS_DIEPCTL_TXFNUM_SHIFT);
regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT);
regval |= (OTGFS_DIEPCTL_SD0PID | OTGFS_DIEPCTL_USBAEP);
stm32l4_putreg(regval, regaddr);