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esp32(s3)_cpustart.c: Don't reset app CPU if it was already configured by

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OpenOCD.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2021-12-10 23:50:43 +01:00 committed by Gustavo Henrique Nihei
parent b10c8955cf
commit b98676f8be
2 changed files with 51 additions and 36 deletions
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38
arch/xtensa/src/esp32/esp32_cpustart.c
View File

@ -124,7 +124,7 @@ static inline void xtensa_attach_fromcpu0_interrupt(void)
*
****************************************************************************/
void xtensa_appcpu_start(void)
void IRAM_ATTR xtensa_appcpu_start(void)
{
struct tcb_s *tcb = this_task();
register uint32_t sp;
@ -296,25 +296,33 @@ int up_cpu_start(int cpu)
regval &= ~RTC_CNTL_SW_STALL_APPCPU_C0_M;
putreg32(regval, RTC_CNTL_OPTIONS0_REG);
/* Enable clock gating for the APP CPU */
/* OpenOCD might have already enabled clock gating and taken APP CPU
* out of reset. Don't reset the APP CPU if that's the case as this
* will clear the breakpoints that may have already been set.
*/
regval = getreg32(DPORT_APPCPU_CTRL_B_REG);
regval |= DPORT_APPCPU_CLKGATE_EN;
putreg32(regval, DPORT_APPCPU_CTRL_B_REG);
regval = getreg32(DPORT_APPCPU_CTRL_B_REG);
if ((regval & DPORT_APPCPU_CLKGATE_EN_M) == 0)
{
/* Enable clock gating for the APP CPU */
regval = getreg32(DPORT_APPCPU_CTRL_C_REG);
regval &= ~DPORT_APPCPU_RUNSTALL;
putreg32(regval, DPORT_APPCPU_CTRL_C_REG);
regval |= DPORT_APPCPU_CLKGATE_EN;
putreg32(regval, DPORT_APPCPU_CTRL_B_REG);
/* Reset the APP CPU */
regval = getreg32(DPORT_APPCPU_CTRL_C_REG);
regval &= ~DPORT_APPCPU_RUNSTALL;
putreg32(regval, DPORT_APPCPU_CTRL_C_REG);
regval = getreg32(DPORT_APPCPU_CTRL_A_REG);
regval |= DPORT_APPCPU_RESETTING;
putreg32(regval, DPORT_APPCPU_CTRL_A_REG);
/* Reset the APP CPU */
regval = getreg32(DPORT_APPCPU_CTRL_A_REG);
regval &= ~DPORT_APPCPU_RESETTING;
putreg32(regval, DPORT_APPCPU_CTRL_A_REG);
regval = getreg32(DPORT_APPCPU_CTRL_A_REG);
regval |= DPORT_APPCPU_RESETTING;
putreg32(regval, DPORT_APPCPU_CTRL_A_REG);
regval = getreg32(DPORT_APPCPU_CTRL_A_REG);
regval &= ~DPORT_APPCPU_RESETTING;
putreg32(regval, DPORT_APPCPU_CTRL_A_REG);
}
/* Set the CPU1 start address */

49
arch/xtensa/src/esp32s3/esp32s3_cpustart.c
View File

@ -241,35 +241,42 @@ int up_cpu_start(int cpu)
spin_initialize(&g_appcpu_interlock, SP_LOCKED);
/* Unstall the APP CPU */
/* OpenOCD might have already enabled clock gating and taken APP CPU
* out of reset. Don't reset the APP CPU if that's the case as this
* will clear the breakpoints that may have already been set.
*/
regval = getreg32(RTC_CNTL_RTC_SW_CPU_STALL_REG);
regval &= ~RTC_CNTL_SW_STALL_APPCPU_C1_M;
putreg32(regval, RTC_CNTL_RTC_SW_CPU_STALL_REG);
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
if ((regval & SYSTEM_CONTROL_CORE_1_CLKGATE_EN) == 0)
{
regval = getreg32(RTC_CNTL_RTC_SW_CPU_STALL_REG);
regval &= ~RTC_CNTL_SW_STALL_APPCPU_C1_M;
putreg32(regval, RTC_CNTL_RTC_SW_CPU_STALL_REG);
regval = getreg32(RTC_CNTL_RTC_OPTIONS0_REG);
regval &= ~RTC_CNTL_SW_STALL_APPCPU_C0_M;
putreg32(regval, RTC_CNTL_RTC_OPTIONS0_REG);
regval = getreg32(RTC_CNTL_RTC_OPTIONS0_REG);
regval &= ~RTC_CNTL_SW_STALL_APPCPU_C0_M;
putreg32(regval, RTC_CNTL_RTC_OPTIONS0_REG);
/* Enable clock gating for the APP CPU */
/* Enable clock gating for the APP CPU */
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval |= SYSTEM_CONTROL_CORE_1_CLKGATE_EN;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval |= SYSTEM_CONTROL_CORE_1_CLKGATE_EN;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval &= ~SYSTEM_CONTROL_CORE_1_RUNSTALL;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval &= ~SYSTEM_CONTROL_CORE_1_RUNSTALL;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
/* Reset the APP CPU */
/* Reset the APP CPU */
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval |= SYSTEM_CONTROL_CORE_1_RESETING;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval |= SYSTEM_CONTROL_CORE_1_RESETING;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval &= ~SYSTEM_CONTROL_CORE_1_RESETING;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
regval &= ~SYSTEM_CONTROL_CORE_1_RESETING;
putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
}
/* Set the CPU1 start address */