Merged in raiden00/nuttx_h7/h7dma (pull request #831)
Missing definitions and better organistaion for STM32H7 DMA arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h: rename DMA channel definitions arch/arm/src/stm32h7/chip/stm32_dma: separated files for MDMA, DMA, BDMA and DMAMUX arch/arm/src/stm32h7/chip/stm32_dma: missing definitions for MDMA, BDMA and DMAMUX Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
Gregory Nutt
parent
9a5134acac
commit
b9ef70ed0f
@ -49,16 +49,21 @@
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#undef DMA_HAVE_CSELR
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/* 2 DMA controllers */
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#define DMA1 (0)
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#define DMA2 (1)
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/* These definitions apply to both the STM32 F1 and F3 families */
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/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
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#define DMA1 0
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#define DMA2 1
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#define DMA3 2
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#define DMA4 3
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#define DMA5 4
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#define DMA6 5
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#define DMA7 6
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#define DMA_CHAN1 (0)
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#define DMA_CHAN2 (1)
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#define DMA_CHAN3 (2)
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#define DMA_CHAN4 (3)
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#define DMA_CHAN5 (4)
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#define DMA_CHAN6 (5)
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#define DMA_CHAN7 (6)
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/* Register Offsets *****************************************************************/
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@ -51,15 +51,20 @@
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# define DMA_HAVE_CSELR 1
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#endif
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/* 2 DMA controllers */
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#define DMA1 (0)
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#define DMA2 (1)
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/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
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#define DMA1 0
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#define DMA2 1
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#define DMA3 2
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#define DMA4 3
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#define DMA5 4
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#define DMA6 5
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#define DMA7 6
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#define DMA_CHAN1 (0)
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#define DMA_CHAN2 (1)
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#define DMA_CHAN3 (2)
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#define DMA_CHAN4 (3)
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#define DMA_CHAN5 (4)
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#define DMA_CHAN6 (5)
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#define DMA_CHAN7 (6)
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/* Register Offsets *****************************************************************/
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256
arch/arm/src/stm32h7/chip/stm32_bdma.h
Normal file
256
arch/arm/src/stm32h7/chip/stm32_bdma.h
Normal file
@ -0,0 +1,256 @@
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/************************************************************************************
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* arch/arm/src/stm32h7/chip/stm32_bdma.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H
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#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_BDMA_ISR_OFFSET 0x0000 /* BDMA interrupt status register */
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#define STM32_BDMA_IFCR_OFFSET 0x0004 /* BDMA interrupt flag clear register */
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#define STM32_BDMA_CCRX_OFFSET(x) (0x0008+(x*0x0014)) /* BDMA channel x configuration register */
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#define STM32_BDMA_CCR0_OFFSET STM32_BDMA_CCRX_OFFSET(0)
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#define STM32_BDMA_CCR1_OFFSET STM32_BDMA_CCRX_OFFSET(1)
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#define STM32_BDMA_CCR2_OFFSET STM32_BDMA_CCRX_OFFSET(2)
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#define STM32_BDMA_CCR3_OFFSET STM32_BDMA_CCRX_OFFSET(3)
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#define STM32_BDMA_CCR4_OFFSET STM32_BDMA_CCRX_OFFSET(4)
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#define STM32_BDMA_CCR5_OFFSET STM32_BDMA_CCRX_OFFSET(5)
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#define STM32_BDMA_CCR6_OFFSET STM32_BDMA_CCRX_OFFSET(6)
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#define STM32_BDMA_CCR7_OFFSET STM32_BDMA_CCRX_OFFSET(7)
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#define STM32_BDMA_CNDTRX_OFFSET(x) (0x000C+(x*0x0014)) /* BDMA channel x number of data to transfer register */
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#define STM32_BDMA_CNDTR0_OFFSET STM32_BDMA_CNDTRX_OFFSET(0)
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#define STM32_BDMA_CNDTR1_OFFSET STM32_BDMA_CNDTRX_OFFSET(1)
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#define STM32_BDMA_CNDTR2_OFFSET STM32_BDMA_CNDTRX_OFFSET(2)
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#define STM32_BDMA_CNDTR3_OFFSET STM32_BDMA_CNDTRX_OFFSET(3)
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#define STM32_BDMA_CNDTR4_OFFSET STM32_BDMA_CNDTRX_OFFSET(4)
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#define STM32_BDMA_CNDTR5_OFFSET STM32_BDMA_CNDTRX_OFFSET(5)
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#define STM32_BDMA_CNDTR6_OFFSET STM32_BDMA_CNDTRX_OFFSET(6)
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#define STM32_BDMA_CNDTR7_OFFSET STM32_BDMA_CNDTRX_OFFSET(7)
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#define STM32_BDMA_CPARX_OFFSET(x) (0x0010+(x*0x0014)) /* BDMA channel x peripheral address register */
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#define STM32_BDMA_CPAR0_OFFSET STM32_BDMA_CPARX_OFFSET(0)
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#define STM32_BDMA_CPAR1_OFFSET STM32_BDMA_CPARX_OFFSET(1)
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#define STM32_BDMA_CPAR2_OFFSET STM32_BDMA_CPARX_OFFSET(2)
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#define STM32_BDMA_CPAR3_OFFSET STM32_BDMA_CPARX_OFFSET(3)
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#define STM32_BDMA_CPAR4_OFFSET STM32_BDMA_CPARX_OFFSET(4)
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#define STM32_BDMA_CPAR5_OFFSET STM32_BDMA_CPARX_OFFSET(5)
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#define STM32_BDMA_CPAR6_OFFSET STM32_BDMA_CPARX_OFFSET(6)
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#define STM32_BDMA_CPAR7_OFFSET STM32_BDMA_CPARX_OFFSET(7)
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#define STM32_BDMA_CM0ARX_OFFSET(x) (0x0014+(x*0x0014)) /* BDMA channel x memory 0 address register */
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#define STM32_BDMA_CM0AR0_OFFSET STM32_BDMA_CM0ARX_OFFSET(0)
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#define STM32_BDMA_CM0AR1_OFFSET STM32_BDMA_CM0ARX_OFFSET(1)
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#define STM32_BDMA_CM0AR2_OFFSET STM32_BDMA_CM0ARX_OFFSET(2)
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#define STM32_BDMA_CM0AR3_OFFSET STM32_BDMA_CM0ARX_OFFSET(3)
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#define STM32_BDMA_CM0AR4_OFFSET STM32_BDMA_CM0ARX_OFFSET(4)
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#define STM32_BDMA_CM0AR5_OFFSET STM32_BDMA_CM0ARX_OFFSET(5)
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#define STM32_BDMA_CM0AR6_OFFSET STM32_BDMA_CM0ARX_OFFSET(6)
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#define STM32_BDMA_CM0AR7_OFFSET STM32_BDMA_CM0ARX_OFFSET(7)
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#define STM32_BDMA_CM1ARX_OFFSET(x) (0x0018+(x*0x0014)) /* BDMA channel x memory 1 address register */
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#define STM32_BDMA_CM1AR0_OFFSET STM32_BDMA_CM1ARX_OFFSET(0)
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#define STM32_BDMA_CM1AR1_OFFSET STM32_BDMA_CM1ARX_OFFSET(1)
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#define STM32_BDMA_CM1AR2_OFFSET STM32_BDMA_CM1ARX_OFFSET(2)
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#define STM32_BDMA_CM1AR3_OFFSET STM32_BDMA_CM1ARX_OFFSET(3)
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#define STM32_BDMA_CM1AR4_OFFSET STM32_BDMA_CM1ARX_OFFSET(4)
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#define STM32_BDMA_CM1AR5_OFFSET STM32_BDMA_CM1ARX_OFFSET(5)
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#define STM32_BDMA_CM1AR6_OFFSET STM32_BDMA_CM1ARX_OFFSET(6)
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#define STM32_BDMA_CM1AR7_OFFSET STM32_BDMA_CM1ARX_OFFSET(7)
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/* Register Addresses ***************************************************************/
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#define STM32_BDMA_ISR (STM32_BDMA_BASE+STM32_BDMA_ISR_OFFSET)
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#define STM32_BDMA_IFCR (STM32_BDMA_BASE+STM32_BDMA_IFCR_OFFSET)
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#define STM32_BDMA_CCRX(x) (STM32_BDMA_BASE+STM32_BDMA_CCRX_OFFSET(x))
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#define STM32_BDMA_CCR0 (STM32_BDMA_BASE+STM32_BDMA_CCR0_OFFSET)
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#define STM32_BDMA_CCR1 (STM32_BDMA_BASE+STM32_BDMA_CCR1_OFFSET)
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#define STM32_BDMA_CCR2 (STM32_BDMA_BASE+STM32_BDMA_CCR2_OFFSET)
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#define STM32_BDMA_CCR3 (STM32_BDMA_BASE+STM32_BDMA_CCR3_OFFSET)
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#define STM32_BDMA_CCR4 (STM32_BDMA_BASE+STM32_BDMA_CCR4_OFFSET)
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#define STM32_BDMA_CCR5 (STM32_BDMA_BASE+STM32_BDMA_CCR5_OFFSET)
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#define STM32_BDMA_CCR6 (STM32_BDMA_BASE+STM32_BDMA_CCR6_OFFSET)
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#define STM32_BDMA_CCR7 (STM32_BDMA_BASE+STM32_BDMA_CCR7_OFFSET)
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#define STM32_BDMA_CNDTRX(x) (STM32_BDMA_BASE+STM32_BDMA_CNDTRX_OFFSET(x))
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#define STM32_BDMA_CNDTR0 (STM32_BDMA_BASE+STM32_BDMA_CNDTR0_OFFSET)
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#define STM32_BDMA_CNDTR1 (STM32_BDMA_BASE+STM32_BDMA_CNDTR1_OFFSET)
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#define STM32_BDMA_CNDTR2 (STM32_BDMA_BASE+STM32_BDMA_CNDTR2_OFFSET)
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#define STM32_BDMA_CNDTR3 (STM32_BDMA_BASE+STM32_BDMA_CNDTR3_OFFSET)
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#define STM32_BDMA_CNDTR4 (STM32_BDMA_BASE+STM32_BDMA_CNDTR4_OFFSET)
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#define STM32_BDMA_CNDTR5 (STM32_BDMA_BASE+STM32_BDMA_CNDTR5_OFFSET)
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#define STM32_BDMA_CNDTR6 (STM32_BDMA_BASE+STM32_BDMA_CNDTR6_OFFSET)
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#define STM32_BDMA_CNDTR7 (STM32_BDMA_BASE+STM32_BDMA_CNDTR7_OFFSET)
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#define STM32_BDMA_CPARX(x) (STM32_BDMA_BASE+STM32_BDMA_CPARX_OFFSET(x))
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#define STM32_BDMA_CPAR0 (STM32_BDMA_BASE+STM32_BDMA_CPAR0_OFFSET)
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#define STM32_BDMA_CPAR1 (STM32_BDMA_BASE+STM32_BDMA_CPAR1_OFFSET)
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#define STM32_BDMA_CPAR2 (STM32_BDMA_BASE+STM32_BDMA_CPAR2_OFFSET)
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#define STM32_BDMA_CPAR3 (STM32_BDMA_BASE+STM32_BDMA_CPAR3_OFFSET)
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#define STM32_BDMA_CPAR4 (STM32_BDMA_BASE+STM32_BDMA_CPAR4_OFFSET)
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#define STM32_BDMA_CPAR5 (STM32_BDMA_BASE+STM32_BDMA_CPAR5_OFFSET)
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#define STM32_BDMA_CPAR6 (STM32_BDMA_BASE+STM32_BDMA_CPAR6_OFFSET)
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#define STM32_BDMA_CPAR7 (STM32_BDMA_BASE+STM32_BDMA_CPAR7_OFFSET)
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#define STM32_BDMA_CM0ARX(x) (STM32_BDMA_BASE+STM32_BDMA_CM0ARX_OFFSET(x))
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#define STM32_BDMA_CM0AR0 (STM32_BDMA_BASE+STM32_BDMA_CM0AR0_OFFSET)
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#define STM32_BDMA_CM0AR1 (STM32_BDMA_BASE+STM32_BDMA_CM0AR1_OFFSET)
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#define STM32_BDMA_CM0AR2 (STM32_BDMA_BASE+STM32_BDMA_CM0AR2_OFFSET)
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#define STM32_BDMA_CM0AR3 (STM32_BDMA_BASE+STM32_BDMA_CM0AR3_OFFSET)
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#define STM32_BDMA_CM0AR4 (STM32_BDMA_BASE+STM32_BDMA_CM0AR4_OFFSET)
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#define STM32_BDMA_CM0AR5 (STM32_BDMA_BASE+STM32_BDMA_CM0AR5_OFFSET)
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#define STM32_BDMA_CM0AR6 (STM32_BDMA_BASE+STM32_BDMA_CM0AR6_OFFSET)
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#define STM32_BDMA_CM0AR7 (STM32_BDMA_BASE+STM32_BDMA_CM0AR7_OFFSET)
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#define STM32_BDMA_CM1ARX(x) (STM32_BDMA_BASE+STM32_BDMA_CM1ARX_OFFSET(x))
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#define STM32_BDMA_CM1AR0 (STM32_BDMA_BASE+STM32_BDMA_CM1AR0_OFFSET)
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#define STM32_BDMA_CM1AR1 (STM32_BDMA_BASE+STM32_BDMA_CM1AR1_OFFSET)
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#define STM32_BDMA_CM1AR2 (STM32_BDMA_BASE+STM32_BDMA_CM1AR2_OFFSET)
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#define STM32_BDMA_CM1AR3 (STM32_BDMA_BASE+STM32_BDMA_CM1AR3_OFFSET)
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#define STM32_BDMA_CM1AR4 (STM32_BDMA_BASE+STM32_BDMA_CM1AR4_OFFSET)
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#define STM32_BDMA_CM1AR5 (STM32_BDMA_BASE+STM32_BDMA_CM1AR5_OFFSET)
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#define STM32_BDMA_CM1AR6 (STM32_BDMA_BASE+STM32_BDMA_CM1AR6_OFFSET)
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#define STM32_BDMA_CM1AR7 (STM32_BDMA_BASE+STM32_BDMA_CM1AR7_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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#define BDMA_CHAN_SHIFT(n) ((n) << 2)
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#define BDMA_CHAN_MASK 0xf
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#define BDMA_CHAN_CGIF (1 << 0) /* Bit 0: Global interrupt flag */
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#define BDMA_CHAN_TCIF (1 << 1) /* Bit 1: Transfer complete flag */
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#define BDMA_CHAN_HTIF (1 << 2) /* Bit 2: half transfer complete flag */
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#define BDMA_CHAN_TEIF (1 << 3) /* Bit 3: Transfer error flag */
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/* BDMA interrupt status register */
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#define BDMA_ISR_CHAN_SHIFT(n) BDMA_CHAN_SHIFT(n)
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#define BDMA_ISR_CHAN_MASK(n) (BDMA_CHAN_MASK << BDMA_ISR_CHAN_SHIFT(n))
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#define BDMA_ISR_CHAN0_SHIFT (0) /* Bits 3-0: BDMA Channel 0 interrupt status */
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#define BDMA_ISR_CHAN0_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN1_SHIFT)
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#define BDMA_ISR_CHAN1_SHIFT (4) /* Bits 7-4: BDMA Channel 1 interrupt status */
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#define BDMA_ISR_CHAN1_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN2_SHIFT)
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#define BDMA_ISR_CHAN2_SHIFT (8) /* Bits 11-8: BDMA Channel 2 interrupt status */
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#define BDMA_ISR_CHAN2_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN3_SHIFT)
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#define BDMA_ISR_CHAN3_SHIFT (12) /* Bits 15-12: BDMA Channel 3 interrupt status */
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#define BDMA_ISR_CHAN3_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN4_SHIFT)
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#define BDMA_ISR_CHAN4_SHIFT (16) /* Bits 19-16: BDMA Channel 4 interrupt status */
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#define BDMA_ISR_CHAN4_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN5_SHIFT)
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#define BDMA_ISR_CHAN5_SHIFT (20) /* Bits 23-20: BDMA Channel 5 interrupt status */
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#define BDMA_ISR_CHAN5_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN6_SHIFT)
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#define BDMA_ISR_CHAN6_SHIFT (24) /* Bits 27-24: BDMA Channel 6 interrupt status */
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#define BDMA_ISR_CHAN6_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN7_SHIFT)
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#define BDMA_ISR_CHAN7_SHIFT (28) /* Bits 31-28: BDMA Channel 7 interrupt status */
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#define BDMA_ISR_CHAN7_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN7_SHIFT)
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#define BDMA_ISR_CGIF(n) (BDMA_CHAN_CGIF_BIT << BDMA_ISR_CHAN_SHIFT(n))
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#define BDMA_ISR_TCIF(n) (BDMA_CHAN_TCIF_BIT << BDMA_ISR_CHAN_SHIFT(n))
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#define BDMA_ISR_HTIF(n) (BDMA_CHAN_HTIF_BIT << BDMA_ISR_CHAN_SHIFT(n))
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#define BDMA_ISR_TEIF(n) (BDMA_CHAN_TEIF_BIT << BDMA_ISR_CHAN_SHIFT(n))
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/* BDMA interrupt flag clear register */
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#define BDMA_IFCR_CHAN_SHIFT(n) BDMA_CHAN_SHIFT(n)
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#define BDMA_IFCR_CHAN_MASK(n) (BDMA_CHAN_MASK << BDMA_IFCR_CHAN_SHIFT(n))
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#define BDMA_IFCR_CHAN0_SHIFT (0) /* Bits 3-0: BDMA Channel 0 interrupt status */
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#define BDMA_IFCR_CHAN0_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN1_SHIFT)
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#define BDMA_IFCR_CHAN1_SHIFT (4) /* Bits 7-4: BDMA Channel 1 interrupt status */
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#define BDMA_IFCR_CHAN1_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN2_SHIFT)
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#define BDMA_IFCR_CHAN2_SHIFT (8) /* Bits 11-8: BDMA Channel 2 interrupt status */
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#define BDMA_IFCR_CHAN2_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN3_SHIFT)
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#define BDMA_IFCR_CHAN3_SHIFT (12) /* Bits 15-12: BDMA Channel 3 interrupt status */
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#define BDMA_IFCR_CHAN3_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN4_SHIFT)
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#define BDMA_IFCR_CHAN4_SHIFT (16) /* Bits 19-16: BDMA Channel 4 interrupt status */
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#define BDMA_IFCR_CHAN4_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN5_SHIFT)
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#define BDMA_IFCR_CHAN5_SHIFT (20) /* Bits 23-20: BDMA Channel 5 interrupt status */
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#define BDMA_IFCR_CHAN5_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN6_SHIFT)
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#define BDMA_IFCR_CHAN6_SHIFT (24) /* Bits 27-24: BDMA Channel 6 interrupt status */
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#define BDMA_IFCR_CHAN6_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN7_SHIFT)
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#define BDMA_IFCR_CHAN7_SHIFT (28) /* Bits 31-28: BDMA Channel 7 interrupt status */
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#define BDMA_IFCR_CHAN7_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN7_SHIFT)
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#define BDMA_IFCR_CGIF(n) (BDMA_CHAN_CGIF_BIT << BDMA_IFCR_CHAN_SHIFT(n))
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#define BDMA_IFCR_TCIF(n) (BDMA_CHAN_TCIF_BIT << BDMA_IFCR_CHAN_SHIFT(n))
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#define BDMA_IFCR_HTIF(n) (BDMA_CHAN_HTIF_BIT << BDMA_IFCR_CHAN_SHIFT(n))
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#define BDMA_IFCR_TEIF(n) (BDMA_CHAN_TEIF_BIT << BDMA_IFCR_CHAN_SHIFT(n))
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/* BDMA channel x configuration register */
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#define BDMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
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#define BDMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
|
||||
#define BDMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
|
||||
#define BDMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
|
||||
#define BDMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
|
||||
#define BDMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
|
||||
#define BDMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
|
||||
#define BDMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment */
|
||||
#define BDMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
|
||||
#define BDMA_CCR_PSIZE_MASK (3 << BDMA_CCR_PSIZE_SHIFT)
|
||||
# define BDMA_CCR_PSIZE_8BITS (0 << BDMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define BDMA_CCR_PSIZE_16BITS (1 << BDMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define BDMA_CCR_PSIZE_32BITS (2 << BDMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define BDMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size*/
|
||||
#define BDMA_CCR_MSIZE_MASK (3 << BDMA_CCR_MSIZE_SHIFT)
|
||||
# define BDMA_CCR_MSIZE_8BITS (0 << BDMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define BDMA_CCR_MSIZE_16BITS (1 << BDMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define BDMA_CCR_MSIZE_32BITS (2 << BDMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define BDMA_CCR_PL_SHIFT (12) /* Bits 12-13: Priority level */
|
||||
#define BDMA_CCR_PL_MASK (3 << BDMA_CCR_PL_SHIFT)
|
||||
# define BDMA_CCR_PRILO (0 << BDMA_CCR_PL_SHIFT) /* 00: Low */
|
||||
# define BDMA_CCR_PRIMED (1 << BDMA_CCR_PL_SHIFT) /* 01: Medium */
|
||||
# define BDMA_CCR_PRIHI (2 << BDMA_CCR_PL_SHIFT) /* 10: High */
|
||||
# define BDMA_CCR_PRIVERYHI (3 << BDMA_CCR_PL_SHIFT) /* 11: Very high */
|
||||
#define BDMA_CCR_M2M (1 << 14) /* Bit 14: Memory-to-memory mode */
|
||||
#define BDMA_CCR_DBM (1 << 15) /* Bit 15: dobule buffer mode*/
|
||||
#define BDMA_CCR_CT (1 << 16) /* Bit 16: Current target */
|
||||
|
||||
/* BDMA channel x number of data to transfer register */
|
||||
|
||||
#define BDMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define BDMA_CNDTR_NDT_MASK (0xffff << BDMA_CNDTR_NDT_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H */
|
||||
@ -43,10 +43,334 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32H7_STM32H7X3XX)
|
||||
# include "chip/stm32h7x3xx_dma.h"
|
||||
#else
|
||||
# error "Unsupported STM32 H7 sub family"
|
||||
#endif
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* 2 DMA controllers + 1 MDMA + 1 BDMA*/
|
||||
|
||||
#define DMA1 (0)
|
||||
#define DMA2 (1)
|
||||
#define MDMA (3)
|
||||
#define BDMA (4)
|
||||
|
||||
/* 8 DMA streams */
|
||||
|
||||
#define DMA_STREAM0 (0)
|
||||
#define DMA_STREAM1 (1)
|
||||
#define DMA_STREAM2 (2)
|
||||
#define DMA_STREAM3 (3)
|
||||
#define DMA_STREAM4 (4)
|
||||
#define DMA_STREAM5 (5)
|
||||
#define DMA_STREAM6 (6)
|
||||
#define DMA_STREAM7 (7)
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */
|
||||
#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */
|
||||
#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */
|
||||
#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */
|
||||
|
||||
#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n))
|
||||
#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */
|
||||
#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */
|
||||
#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */
|
||||
#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */
|
||||
#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */
|
||||
#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */
|
||||
|
||||
#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */
|
||||
#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */
|
||||
#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */
|
||||
#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */
|
||||
#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */
|
||||
#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */
|
||||
#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */
|
||||
#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */
|
||||
|
||||
#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */
|
||||
#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */
|
||||
#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */
|
||||
#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */
|
||||
#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */
|
||||
#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */
|
||||
#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */
|
||||
#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */
|
||||
|
||||
#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */
|
||||
#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */
|
||||
#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */
|
||||
#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */
|
||||
#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */
|
||||
#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */
|
||||
#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */
|
||||
#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */
|
||||
|
||||
#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */
|
||||
#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */
|
||||
#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */
|
||||
#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */
|
||||
#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */
|
||||
#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */
|
||||
#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */
|
||||
#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */
|
||||
|
||||
#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */
|
||||
#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */
|
||||
#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */
|
||||
#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */
|
||||
#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */
|
||||
#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */
|
||||
#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */
|
||||
#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */
|
||||
|
||||
#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */
|
||||
#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */
|
||||
#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */
|
||||
#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */
|
||||
#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */
|
||||
#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */
|
||||
#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */
|
||||
#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET)
|
||||
#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET)
|
||||
#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET)
|
||||
#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET)
|
||||
#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET)
|
||||
#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET)
|
||||
#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET)
|
||||
#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET)
|
||||
#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET)
|
||||
#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET)
|
||||
#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET)
|
||||
#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET)
|
||||
#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET)
|
||||
#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET)
|
||||
#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET)
|
||||
#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET)
|
||||
#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET)
|
||||
#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET)
|
||||
#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET)
|
||||
#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET)
|
||||
#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET)
|
||||
#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET)
|
||||
#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET)
|
||||
#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET)
|
||||
#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET)
|
||||
#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET)
|
||||
#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET)
|
||||
#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET)
|
||||
#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET)
|
||||
#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET)
|
||||
#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET)
|
||||
#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET)
|
||||
#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET)
|
||||
#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET)
|
||||
#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET)
|
||||
#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET)
|
||||
#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET)
|
||||
#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET)
|
||||
#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET)
|
||||
#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET)
|
||||
#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET)
|
||||
#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET)
|
||||
#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET)
|
||||
#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET)
|
||||
#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET)
|
||||
#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET)
|
||||
#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET)
|
||||
#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET)
|
||||
#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET)
|
||||
#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET)
|
||||
#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET)
|
||||
#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET)
|
||||
#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET)
|
||||
#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET)
|
||||
#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET)
|
||||
#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET)
|
||||
#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET)
|
||||
#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET)
|
||||
#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET)
|
||||
#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET)
|
||||
#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET)
|
||||
#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET)
|
||||
#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET)
|
||||
#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET)
|
||||
#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET)
|
||||
#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET)
|
||||
#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET)
|
||||
#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET)
|
||||
#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET)
|
||||
#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET)
|
||||
#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET)
|
||||
#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET)
|
||||
#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET)
|
||||
#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET)
|
||||
#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET)
|
||||
#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET)
|
||||
#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET)
|
||||
#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET)
|
||||
#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET)
|
||||
#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET)
|
||||
#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET)
|
||||
#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET)
|
||||
#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET)
|
||||
#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
|
||||
#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET)
|
||||
#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET)
|
||||
#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET)
|
||||
#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET)
|
||||
#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET)
|
||||
#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET)
|
||||
#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET)
|
||||
#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_STREAM_MASK 0x3f
|
||||
#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */
|
||||
#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */
|
||||
#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */
|
||||
#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */
|
||||
#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */
|
||||
|
||||
/* DMA interrupt status register and interrupt flag clear register field definitions */
|
||||
|
||||
#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */
|
||||
#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT)
|
||||
#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */
|
||||
#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT)
|
||||
#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */
|
||||
#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT)
|
||||
#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */
|
||||
#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT)
|
||||
|
||||
#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */
|
||||
#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT)
|
||||
#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */
|
||||
#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT)
|
||||
#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */
|
||||
#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT)
|
||||
#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */
|
||||
#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT)
|
||||
|
||||
/* DMA stream configuration register */
|
||||
|
||||
#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */
|
||||
#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */
|
||||
#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */
|
||||
#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */
|
||||
#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */
|
||||
#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */
|
||||
#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */
|
||||
#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT)
|
||||
# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */
|
||||
# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */
|
||||
# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */
|
||||
#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */
|
||||
#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */
|
||||
#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */
|
||||
#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */
|
||||
#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT)
|
||||
# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */
|
||||
#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT)
|
||||
# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */
|
||||
#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */
|
||||
#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT)
|
||||
# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */
|
||||
#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */
|
||||
/* Bit 20: Reserved */
|
||||
#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */
|
||||
#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT)
|
||||
# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */
|
||||
# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */
|
||||
# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */
|
||||
# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */
|
||||
#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */
|
||||
#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT)
|
||||
# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */
|
||||
# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */
|
||||
# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */
|
||||
# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */
|
||||
/* Bits 25-31: Reserved */
|
||||
|
||||
#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE)
|
||||
|
||||
/* DMA stream number of data register */
|
||||
|
||||
#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA stream n FIFO control register */
|
||||
|
||||
#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */
|
||||
#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT)
|
||||
# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */
|
||||
# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */
|
||||
# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */
|
||||
# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */
|
||||
#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */
|
||||
#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */
|
||||
#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT)
|
||||
# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */
|
||||
# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */
|
||||
# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */
|
||||
# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */
|
||||
# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */
|
||||
# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */
|
||||
/* Bit 6: Reserved */
|
||||
#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H */
|
||||
|
||||
205
arch/arm/src/stm32h7/chip/stm32_dmamux.h
Normal file
205
arch/arm/src/stm32h7/chip/stm32_dmamux.h
Normal file
@ -0,0 +1,205 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/chip/stm32_dmamux.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX12 request line multiplexer channel x configuration register */
|
||||
#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0)
|
||||
#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1)
|
||||
#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2)
|
||||
#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3)
|
||||
#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4)
|
||||
#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5)
|
||||
#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6)
|
||||
#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7)
|
||||
#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8)
|
||||
#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9)
|
||||
#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10)
|
||||
#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11)
|
||||
#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12)
|
||||
#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13)
|
||||
#define STM32_DMAMUX_C14CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(14)
|
||||
#define STM32_DMAMUX_C15CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(15)
|
||||
/* 0x040-0x07C: Reserved */
|
||||
#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */
|
||||
#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */
|
||||
/* 0x088-0x0FC: Reserved */
|
||||
#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX12 request generator channel x configuration register */
|
||||
#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0)
|
||||
#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1)
|
||||
#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2)
|
||||
#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3)
|
||||
#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX12 request generator interrupt status register */
|
||||
#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX12 request generator interrupt clear flag register */
|
||||
/* 0x148-0x3FC: Reserved */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C14CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C15CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C14CR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET)
|
||||
#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET)
|
||||
#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX2_CXCR(x) (STM32_DMAMUX2_BASE+STM32_DMAMUX_CXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX2_C0CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C0CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C1CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C1CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C2CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C2CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C3CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C3CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C4CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C4CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C5CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C5CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C6CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C6CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C7CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C7CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C8CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C8CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C9CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C9CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C10CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C10CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C11CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C11CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C12CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C12CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C13CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C12CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C14CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C13CR_OFFSET)
|
||||
#define STM32_DMAMUX2_C15CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C14CR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX2_CSR (STM32_DMAMUX2_BASE+STM32_DMAMUX_CSR_OFFSET)
|
||||
#define STM32_DMAMUX2_CFR (STM32_DMAMUX2_BASE+STM32_DMAMUX_CFR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX2_RGXCR(x) (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX2_RG0CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG0CR_OFFSET)
|
||||
#define STM32_DMAMUX2_RG1CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG1CR_OFFSET)
|
||||
#define STM32_DMAMUX2_RG2CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG2CR_OFFSET)
|
||||
#define STM32_DMAMUX2_RG3CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG3CR_OFFSET)
|
||||
|
||||
#define STM32_DMAMUX2_RGSR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGSR_OFFSET)
|
||||
#define STM32_DMAMUX2_RGCFR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGCFR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* DMAMUX12 request line multiplexer channel x configuration register */
|
||||
|
||||
#define DMAMUX_CXCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */
|
||||
#define DMAMUX_CXCR_DMAREQID_MASK (0x7f << DMAMUX_CXCR_DMAREQID_SHIFT)
|
||||
#define DMAMUX_CXCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */
|
||||
#define DMAMUX_CXCR_EGE (9) /* Bit 9: Event generation enable */
|
||||
#define DMAMUX_CXCR_SE (16) /* Bit 16: Synchronization enable */
|
||||
#define DMAMUX_CXCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */
|
||||
#define DMAMUX_CXCR_SPOL_MASK (3 << DMAMUX_CXCR_SPOL_SHIFT)
|
||||
#define DMAMUX_CXCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */
|
||||
#define DMAMUX_CXCR_NBREQ_MASK (0x1f << DMAMUX_CXCR_NBREQ_SHIFT)
|
||||
#define DMAMUX_CXCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */
|
||||
#define DMAMUX_CXCR_SYNCID_MASK (7 << DMAMUX_CXCR_SYNCID_SHIFT)
|
||||
|
||||
/* DMAMUX12 request line multiplexer interrupt channel status register */
|
||||
|
||||
#define DMAMUX1_CSR_SOF(x) (1 << x) /* Synchronization overrun event flag */
|
||||
|
||||
/* DMAMUX12 request line multiplexer interrupt clear flag register */
|
||||
|
||||
#define DMAMUX1_CFR_SOF(x) (1 << x) /* Clear synchronization overrun event flag */
|
||||
|
||||
/* DMAMUX12 request generator channel x configuration register */
|
||||
|
||||
#define DMAMUX_RGXCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction */
|
||||
/* WARNING: different length for DMAMUX1 and DMAMUX2 !*/
|
||||
#define DMAMUX_RGXCR_SIGID_MASK (0x1f << DMAMUX_RGXCR_SIGID_SHIFT)
|
||||
#define DMAMUX_RGXCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */
|
||||
#define DMAMUX_RGXCR_GE (16) /* Bit 16: DMA request generator channel X enable*/
|
||||
#define DMAMUX_RGXCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */
|
||||
#define DMAMUX_RGXCR_GPOL_MASK (7 << DMAMUX_RGXCR_GPOL_SHIFT)
|
||||
#define DMAMUX_RGXCR_GNBREQ_SHIFT (17) /* Bits 19-23: Number of DMA requests to be generated -1 */
|
||||
#define DMAMUX_RGXCR_GNBREQL_MASK (7 << DMAMUX_RGXCR_GNBREQ_SHIFT)
|
||||
|
||||
/* DMAMUX12 request generator interrupt status register */
|
||||
|
||||
#define DMAMUX1_RGSR_SOF(x) (1 << x) /* Trigger overrun event flag */
|
||||
|
||||
/* DMAMUX12 request generator interrupt clear flag register */
|
||||
|
||||
#define DMAMUX1_RGCFR_SOF(x) (1 << x) /* Clear trigger overrun event flag */
|
||||
|
||||
/* DMA Stream mapping.
|
||||
* TODO:
|
||||
*/
|
||||
|
||||
#define STM32_DMA_MAP(d,s,c) ((d) << 7 | (s) << 4 | (c))
|
||||
#define STM32_DMA_CONTROLLER(m) (((m) >> 7) & 1)
|
||||
#define STM32_DMA_STREAM(m) (((m) >> 4) & 7)
|
||||
#define STM32_DMA_CHANNEL(m) ((m) & 15)
|
||||
|
||||
/* Import DMAMUX map */
|
||||
|
||||
#if defined(CONFIG_STM32H7_STM32H7X3XX)
|
||||
# include "chip/stm32h7x3xx_dmamux.h"
|
||||
#else
|
||||
# error "Unsupported STM32 H7 sub family"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H */
|
||||
631
arch/arm/src/stm32h7/chip/stm32_mdma.h
Normal file
631
arch/arm/src/stm32h7/chip/stm32_mdma.h
Normal file
@ -0,0 +1,631 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/chip/stm32_mdma.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MDMA_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MDMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_MDMA_GISR0_OFFSET 0x0000 /* MDMA global interrupt/status register */
|
||||
/* 0x0004-0x003C: Reserved */
|
||||
#define STM32_MDMA_CXISR_OFFSET(x) (0x0040+0x040*(x)) /* MDMA channel x interrupt/status register*/
|
||||
#define STM32_MDMA_C0ISR_OFFSET STM32_MDMA_CXISR_OFFSET(0)
|
||||
#define STM32_MDMA_C1ISR_OFFSET STM32_MDMA_CXISR_OFFSET(1)
|
||||
#define STM32_MDMA_C2ISR_OFFSET STM32_MDMA_CXISR_OFFSET(2)
|
||||
#define STM32_MDMA_C3ISR_OFFSET STM32_MDMA_CXISR_OFFSET(3)
|
||||
#define STM32_MDMA_C4ISR_OFFSET STM32_MDMA_CXISR_OFFSET(4)
|
||||
#define STM32_MDMA_C5ISR_OFFSET STM32_MDMA_CXISR_OFFSET(5)
|
||||
#define STM32_MDMA_C6ISR_OFFSET STM32_MDMA_CXISR_OFFSET(6)
|
||||
#define STM32_MDMA_C7ISR_OFFSET STM32_MDMA_CXISR_OFFSET(7)
|
||||
#define STM32_MDMA_C8ISR_OFFSET STM32_MDMA_CXISR_OFFSET(8)
|
||||
#define STM32_MDMA_C9ISR_OFFSET STM32_MDMA_CXISR_OFFSET(9)
|
||||
#define STM32_MDMA_C10ISR_OFFSET STM32_MDMA_CXISR_OFFSET(10)
|
||||
#define STM32_MDMA_C11ISR_OFFSET STM32_MDMA_CXISR_OFFSET(11)
|
||||
#define STM32_MDMA_C12ISR_OFFSET STM32_MDMA_CXISR_OFFSET(12)
|
||||
#define STM32_MDMA_C13ISR_OFFSET STM32_MDMA_CXISR_OFFSET(13)
|
||||
#define STM32_MDMA_C14ISR_OFFSET STM32_MDMA_CXISR_OFFSET(14)
|
||||
#define STM32_MDMA_C15ISR_OFFSET STM32_MDMA_CXISR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXIFCR_OFFSET(x) (0x0044+0x040*(x)) /* MDMA channel x interrupt flag clear register */
|
||||
#define STM32_MDMA_C0IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(0)
|
||||
#define STM32_MDMA_C1IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(1)
|
||||
#define STM32_MDMA_C2IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(2)
|
||||
#define STM32_MDMA_C3IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(3)
|
||||
#define STM32_MDMA_C4IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(4)
|
||||
#define STM32_MDMA_C5IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(5)
|
||||
#define STM32_MDMA_C6IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(6)
|
||||
#define STM32_MDMA_C7IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(7)
|
||||
#define STM32_MDMA_C8IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(8)
|
||||
#define STM32_MDMA_C9IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(9)
|
||||
#define STM32_MDMA_C10IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(10)
|
||||
#define STM32_MDMA_C11IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(11)
|
||||
#define STM32_MDMA_C12IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(12)
|
||||
#define STM32_MDMA_C13IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(13)
|
||||
#define STM32_MDMA_C14IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(14)
|
||||
#define STM32_MDMA_C15IFCR_OFFSET STM32_MDMA_CXIFCR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXESR_OFFSET(x) (0x0048+0x040*(x)) /* MDMA channel x error status register */
|
||||
#define STM32_MDMA_C0ESR_OFFSET STM32_MDMA_CXESR_OFFSET0)
|
||||
#define STM32_MDMA_C1ESR_OFFSET STM32_MDMA_CXESR_OFFSET1)
|
||||
#define STM32_MDMA_C2ESR_OFFSET STM32_MDMA_CXESR_OFFSET2)
|
||||
#define STM32_MDMA_C3ESR_OFFSET STM32_MDMA_CXESR_OFFSET3)
|
||||
#define STM32_MDMA_C4ESR_OFFSET STM32_MDMA_CXESR_OFFSET4)
|
||||
#define STM32_MDMA_C5ESR_OFFSET STM32_MDMA_CXESR_OFFSET5)
|
||||
#define STM32_MDMA_C6ESR_OFFSET STM32_MDMA_CXESR_OFFSET6)
|
||||
#define STM32_MDMA_C7ESR_OFFSET STM32_MDMA_CXESR_OFFSET7)
|
||||
#define STM32_MDMA_C8ESR_OFFSET STM32_MDMA_CXESR_OFFSET8)
|
||||
#define STM32_MDMA_C9ESR_OFFSET STM32_MDMA_CXESR_OFFSET9)
|
||||
#define STM32_MDMA_C10ESR_OFFSET STM32_MDMA_CXESR_OFFSET10)
|
||||
#define STM32_MDMA_C11ESR_OFFSET STM32_MDMA_CXESR_OFFSET11)
|
||||
#define STM32_MDMA_C12ESR_OFFSET STM32_MDMA_CXESR_OFFSET12)
|
||||
#define STM32_MDMA_C13ESR_OFFSET STM32_MDMA_CXESR_OFFSET13)
|
||||
#define STM32_MDMA_C14ESR_OFFSET STM32_MDMA_CXESR_OFFSET14)
|
||||
#define STM32_MDMA_C15ESR_OFFSET STM32_MDMA_CXESR_OFFSET15)
|
||||
|
||||
#define STM32_MDMA_CXCR_OFFSET(x) (0x004C+0x040*(x)) /* MDMA channel x control register */
|
||||
#define STM32_MDMA_C0CR_OFFSET STM32_MDMA_CXCR_OFFSET(0)
|
||||
#define STM32_MDMA_C1CR_OFFSET STM32_MDMA_CXCR_OFFSET(1)
|
||||
#define STM32_MDMA_C2CR_OFFSET STM32_MDMA_CXCR_OFFSET(2)
|
||||
#define STM32_MDMA_C3CR_OFFSET STM32_MDMA_CXCR_OFFSET(3)
|
||||
#define STM32_MDMA_C4CR_OFFSET STM32_MDMA_CXCR_OFFSET(4)
|
||||
#define STM32_MDMA_C5CR_OFFSET STM32_MDMA_CXCR_OFFSET(5)
|
||||
#define STM32_MDMA_C6CR_OFFSET STM32_MDMA_CXCR_OFFSET(6)
|
||||
#define STM32_MDMA_C7CR_OFFSET STM32_MDMA_CXCR_OFFSET(7)
|
||||
#define STM32_MDMA_C8CR_OFFSET STM32_MDMA_CXCR_OFFSET(8)
|
||||
#define STM32_MDMA_C9CR_OFFSET STM32_MDMA_CXCR_OFFSET(9)
|
||||
#define STM32_MDMA_C10CR_OFFSET STM32_MDMA_CXCR_OFFSET(10)
|
||||
#define STM32_MDMA_C11CR_OFFSET STM32_MDMA_CXCR_OFFSET(11)
|
||||
#define STM32_MDMA_C12CR_OFFSET STM32_MDMA_CXCR_OFFSET(12)
|
||||
#define STM32_MDMA_C13CR_OFFSET STM32_MDMA_CXCR_OFFSET(13)
|
||||
#define STM32_MDMA_C14CR_OFFSET STM32_MDMA_CXCR_OFFSET(14)
|
||||
#define STM32_MDMA_C15CR_OFFSET STM32_MDMA_CXCR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXTCR_OFFSET(x) (0x0050+0x040*(x)) /* MDMA channel x transfer configuration register */
|
||||
#define STM32_MDMA_C0TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(0)
|
||||
#define STM32_MDMA_C1TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(1)
|
||||
#define STM32_MDMA_C2TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(2)
|
||||
#define STM32_MDMA_C3TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(3)
|
||||
#define STM32_MDMA_C4TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(4)
|
||||
#define STM32_MDMA_C5TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(5)
|
||||
#define STM32_MDMA_C6TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(6)
|
||||
#define STM32_MDMA_C7TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(7)
|
||||
#define STM32_MDMA_C8TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(8)
|
||||
#define STM32_MDMA_C9TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(9)
|
||||
#define STM32_MDMA_C10TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(10)
|
||||
#define STM32_MDMA_C11TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(11)
|
||||
#define STM32_MDMA_C12TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(12)
|
||||
#define STM32_MDMA_C13TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(13)
|
||||
#define STM32_MDMA_C14TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(14)
|
||||
#define STM32_MDMA_C15TCR_OFFSET STM32_MDMA_CXTCR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXBNDTR_OFFSET(x) (0x0054+0x040*(x)) /* MDMA channel x block number of data register */
|
||||
#define STM32_MDMA_C0BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(0)
|
||||
#define STM32_MDMA_C1BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(1)
|
||||
#define STM32_MDMA_C2BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(2)
|
||||
#define STM32_MDMA_C3BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(3)
|
||||
#define STM32_MDMA_C4BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(4)
|
||||
#define STM32_MDMA_C5BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(5)
|
||||
#define STM32_MDMA_C6BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(6)
|
||||
#define STM32_MDMA_C7BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(7)
|
||||
#define STM32_MDMA_C8BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(8)
|
||||
#define STM32_MDMA_C9BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(9)
|
||||
#define STM32_MDMA_C10BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(10)
|
||||
#define STM32_MDMA_C11BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(11)
|
||||
#define STM32_MDMA_C12BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(12)
|
||||
#define STM32_MDMA_C13BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(13)
|
||||
#define STM32_MDMA_C14BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(14)
|
||||
#define STM32_MDMA_C15BNDTR_OFFSET STM32_MDMA_CXBNDTR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXSAR_OFFSET(x) (0x0058+0x040*(x)) /* MDMA channel x source address register */
|
||||
#define STM32_MDMA_C0SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(0)
|
||||
#define STM32_MDMA_C1SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(1)
|
||||
#define STM32_MDMA_C2SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(2)
|
||||
#define STM32_MDMA_C3SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(3)
|
||||
#define STM32_MDMA_C4SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(4)
|
||||
#define STM32_MDMA_C5SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(5)
|
||||
#define STM32_MDMA_C6SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(6)
|
||||
#define STM32_MDMA_C7SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(7)
|
||||
#define STM32_MDMA_C8SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(8)
|
||||
#define STM32_MDMA_C9SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(9)
|
||||
#define STM32_MDMA_C10SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(10)
|
||||
#define STM32_MDMA_C11SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(11)
|
||||
#define STM32_MDMA_C12SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(12)
|
||||
#define STM32_MDMA_C13SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(13)
|
||||
#define STM32_MDMA_C14SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(14)
|
||||
#define STM32_MDMA_C15SAR_OFFSET STM32_MDMA_CXSAR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXDAR_OFFSET(x) (0x005C+0x040*(x)) /* MDMA channel x destination address register */
|
||||
#define STM32_MDMA_C0DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(0)
|
||||
#define STM32_MDMA_C1DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(1)
|
||||
#define STM32_MDMA_C2DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(2)
|
||||
#define STM32_MDMA_C3DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(3)
|
||||
#define STM32_MDMA_C4DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(4)
|
||||
#define STM32_MDMA_C5DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(5)
|
||||
#define STM32_MDMA_C6DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(6)
|
||||
#define STM32_MDMA_C7DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(7)
|
||||
#define STM32_MDMA_C8DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(8)
|
||||
#define STM32_MDMA_C9DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(9)
|
||||
#define STM32_MDMA_C10DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(10)
|
||||
#define STM32_MDMA_C11DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(11)
|
||||
#define STM32_MDMA_C12DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(12)
|
||||
#define STM32_MDMA_C13DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(13)
|
||||
#define STM32_MDMA_C14DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(14)
|
||||
#define STM32_MDMA_C15DAR_OFFSET STM32_MDMA_CXDAR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXBRUR_OFFSET(x) (0x0060+0x040*(x)) /* MDMA channel x block repeat address update register */
|
||||
#define STM32_MDMA_C0BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(0)
|
||||
#define STM32_MDMA_C1BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(1)
|
||||
#define STM32_MDMA_C2BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(2)
|
||||
#define STM32_MDMA_C3BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(3)
|
||||
#define STM32_MDMA_C4BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(4)
|
||||
#define STM32_MDMA_C5BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(5)
|
||||
#define STM32_MDMA_C6BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(6)
|
||||
#define STM32_MDMA_C7BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(7)
|
||||
#define STM32_MDMA_C8BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(8)
|
||||
#define STM32_MDMA_C9BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(9)
|
||||
#define STM32_MDMA_C10BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(10)
|
||||
#define STM32_MDMA_C11BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(11)
|
||||
#define STM32_MDMA_C12BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(12)
|
||||
#define STM32_MDMA_C13BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(13)
|
||||
#define STM32_MDMA_C14BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(14)
|
||||
#define STM32_MDMA_C15BRUR_OFFSET STM32_MDMA_CXBRUR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXLAR_OFFSET(x) (0x0064+0x040*(x)) /* MDMA channel x link address register */
|
||||
#define STM32_MDMA_C0LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(0)
|
||||
#define STM32_MDMA_C1LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(1)
|
||||
#define STM32_MDMA_C2LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(2)
|
||||
#define STM32_MDMA_C3LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(3)
|
||||
#define STM32_MDMA_C4LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(4)
|
||||
#define STM32_MDMA_C5LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(5)
|
||||
#define STM32_MDMA_C6LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(6)
|
||||
#define STM32_MDMA_C7LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(7)
|
||||
#define STM32_MDMA_C8LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(8)
|
||||
#define STM32_MDMA_C9LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(9)
|
||||
#define STM32_MDMA_C10LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(10)
|
||||
#define STM32_MDMA_C11LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(11)
|
||||
#define STM32_MDMA_C12LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(12)
|
||||
#define STM32_MDMA_C13LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(13)
|
||||
#define STM32_MDMA_C14LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(14)
|
||||
#define STM32_MDMA_C15LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXTBR_OFFSET(x) (0x0064+0x040*(x)) /* MDMA channel x trigger and bus selection register */
|
||||
#define STM32_MDMA_C0TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(0)
|
||||
#define STM32_MDMA_C1TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(1)
|
||||
#define STM32_MDMA_C2TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(2)
|
||||
#define STM32_MDMA_C3TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(3)
|
||||
#define STM32_MDMA_C4TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(4)
|
||||
#define STM32_MDMA_C5TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(5)
|
||||
#define STM32_MDMA_C6TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(6)
|
||||
#define STM32_MDMA_C7TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(7)
|
||||
#define STM32_MDMA_C8TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(8)
|
||||
#define STM32_MDMA_C9TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(9)
|
||||
#define STM32_MDMA_C10TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(10)
|
||||
#define STM32_MDMA_C11TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(11)
|
||||
#define STM32_MDMA_C12TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(12)
|
||||
#define STM32_MDMA_C13TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(13)
|
||||
#define STM32_MDMA_C14TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(14)
|
||||
#define STM32_MDMA_C15TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXMAR_OFFSET(x) (0x0068+0x040*(x)) /* MDMA channel x mask address register */
|
||||
#define STM32_MDMA_C0MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(0)
|
||||
#define STM32_MDMA_C1MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(1)
|
||||
#define STM32_MDMA_C2MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(2)
|
||||
#define STM32_MDMA_C3MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(3)
|
||||
#define STM32_MDMA_C4MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(4)
|
||||
#define STM32_MDMA_C5MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(5)
|
||||
#define STM32_MDMA_C6MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(6)
|
||||
#define STM32_MDMA_C7MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(7)
|
||||
#define STM32_MDMA_C8MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(8)
|
||||
#define STM32_MDMA_C9MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(9)
|
||||
#define STM32_MDMA_C10MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(10)
|
||||
#define STM32_MDMA_C11MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(11)
|
||||
#define STM32_MDMA_C12MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(12)
|
||||
#define STM32_MDMA_C13MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(13)
|
||||
#define STM32_MDMA_C14MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(14)
|
||||
#define STM32_MDMA_C15MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(15)
|
||||
|
||||
#define STM32_MDMA_CXMDR_OFFSET(x) (0x0070+0x040*(x)) /* MDMA channel x mask data register */
|
||||
#define STM32_MDMA_C0MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(0)
|
||||
#define STM32_MDMA_C1MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(1)
|
||||
#define STM32_MDMA_C2MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(2)
|
||||
#define STM32_MDMA_C3MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(3)
|
||||
#define STM32_MDMA_C4MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(4)
|
||||
#define STM32_MDMA_C5MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(5)
|
||||
#define STM32_MDMA_C6MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(6)
|
||||
#define STM32_MDMA_C7MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(7)
|
||||
#define STM32_MDMA_C8MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(8)
|
||||
#define STM32_MDMA_C9MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(9)
|
||||
#define STM32_MDMA_C10MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(10)
|
||||
#define STM32_MDMA_C11MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(11)
|
||||
#define STM32_MDMA_C12MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(12)
|
||||
#define STM32_MDMA_C13MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(13)
|
||||
#define STM32_MDMA_C14MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(14)
|
||||
#define STM32_MDMA_C15MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(15)
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_MDMA_GISR0 (STM32_MDMA_BASE+STM32_MDMA_GISR0_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXISR(x) (STM32_MDMA_BASE+STM32_MDMA_CXISR_OFFSET(x))
|
||||
#define STM32_MDMA_C0ISR (STM32_MDMA_BASE+STM32_MDMA_C0ISR_OFFSET)
|
||||
#define STM32_MDMA_C1ISR (STM32_MDMA_BASE+STM32_MDMA_C1ISR_OFFSET)
|
||||
#define STM32_MDMA_C2ISR (STM32_MDMA_BASE+STM32_MDMA_C2ISR_OFFSET)
|
||||
#define STM32_MDMA_C3ISR (STM32_MDMA_BASE+STM32_MDMA_C3ISR_OFFSET)
|
||||
#define STM32_MDMA_C4ISR (STM32_MDMA_BASE+STM32_MDMA_C4ISR_OFFSET)
|
||||
#define STM32_MDMA_C5ISR (STM32_MDMA_BASE+STM32_MDMA_C5ISR_OFFSET)
|
||||
#define STM32_MDMA_C6ISR (STM32_MDMA_BASE+STM32_MDMA_C6ISR_OFFSET)
|
||||
#define STM32_MDMA_C7ISR (STM32_MDMA_BASE+STM32_MDMA_C7ISR_OFFSET)
|
||||
#define STM32_MDMA_C8ISR (STM32_MDMA_BASE+STM32_MDMA_C8ISR_OFFSET)
|
||||
#define STM32_MDMA_C9ISR (STM32_MDMA_BASE+STM32_MDMA_C9ISR_OFFSET)
|
||||
#define STM32_MDMA_C10ISR (STM32_MDMA_BASE+STM32_MDMA_C10ISR_OFFSET)
|
||||
#define STM32_MDMA_C11ISR (STM32_MDMA_BASE+STM32_MDMA_C11ISR_OFFSET)
|
||||
#define STM32_MDMA_C12ISR (STM32_MDMA_BASE+STM32_MDMA_C12ISR_OFFSET)
|
||||
#define STM32_MDMA_C13ISR (STM32_MDMA_BASE+STM32_MDMA_C13ISR_OFFSET)
|
||||
#define STM32_MDMA_C14ISR (STM32_MDMA_BASE+STM32_MDMA_C14ISR_OFFSET)
|
||||
#define STM32_MDMA_C15ISR (STM32_MDMA_BASE+STM32_MDMA_C15ISR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXIFCR(x) (STM32_MDMA_BASE+STM32_MDMA_CXIFCR_OFFSET(x))
|
||||
#define STM32_MDMA_C0IFCR (STM32_MDMA_BASE+STM32_MDMA_C0IFCR_OFFSET)
|
||||
#define STM32_MDMA_C1IFCR (STM32_MDMA_BASE+STM32_MDMA_C1IFCR_OFFSET)
|
||||
#define STM32_MDMA_C2IFCR (STM32_MDMA_BASE+STM32_MDMA_C2IFCR_OFFSET)
|
||||
#define STM32_MDMA_C3IFCR (STM32_MDMA_BASE+STM32_MDMA_C3IFCR_OFFSET)
|
||||
#define STM32_MDMA_C4IFCR (STM32_MDMA_BASE+STM32_MDMA_C4IFCR_OFFSET)
|
||||
#define STM32_MDMA_C5IFCR (STM32_MDMA_BASE+STM32_MDMA_C5IFCR_OFFSET)
|
||||
#define STM32_MDMA_C6IFCR (STM32_MDMA_BASE+STM32_MDMA_C6IFCR_OFFSET)
|
||||
#define STM32_MDMA_C7IFCR (STM32_MDMA_BASE+STM32_MDMA_C7IFCR_OFFSET)
|
||||
#define STM32_MDMA_C8IFCR (STM32_MDMA_BASE+STM32_MDMA_C8IFCR_OFFSET)
|
||||
#define STM32_MDMA_C9IFCR (STM32_MDMA_BASE+STM32_MDMA_C9IFCR_OFFSET)
|
||||
#define STM32_MDMA_C10IFCR (STM32_MDMA_BASE+STM32_MDMA_C10IFCR_OFFSET)
|
||||
#define STM32_MDMA_C11IFCR (STM32_MDMA_BASE+STM32_MDMA_C11IFCR_OFFSET)
|
||||
#define STM32_MDMA_C12IFCR (STM32_MDMA_BASE+STM32_MDMA_C12IFCR_OFFSET)
|
||||
#define STM32_MDMA_C13IFCR (STM32_MDMA_BASE+STM32_MDMA_C13IFCR_OFFSET)
|
||||
#define STM32_MDMA_C14IFCR (STM32_MDMA_BASE+STM32_MDMA_C14IFCR_OFFSET)
|
||||
#define STM32_MDMA_C15IFCR (STM32_MDMA_BASE+STM32_MDMA_C15IFCR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXESR(x) (STM32_MDMA_BASE+STM32_MDMA_CXESR_OFFSET(x))
|
||||
#define STM32_MDMA_C0ESR (STM32_MDMA_BASE+STM32_MDMA_C0ESR_OFFSET)
|
||||
#define STM32_MDMA_C1ESR (STM32_MDMA_BASE+STM32_MDMA_C1ESR_OFFSET)
|
||||
#define STM32_MDMA_C2ESR (STM32_MDMA_BASE+STM32_MDMA_C2ESR_OFFSET)
|
||||
#define STM32_MDMA_C3ESR (STM32_MDMA_BASE+STM32_MDMA_C3ESR_OFFSET)
|
||||
#define STM32_MDMA_C4ESR (STM32_MDMA_BASE+STM32_MDMA_C4ESR_OFFSET)
|
||||
#define STM32_MDMA_C5ESR (STM32_MDMA_BASE+STM32_MDMA_C5ESR_OFFSET)
|
||||
#define STM32_MDMA_C6ESR (STM32_MDMA_BASE+STM32_MDMA_C6ESR_OFFSET)
|
||||
#define STM32_MDMA_C7ESR (STM32_MDMA_BASE+STM32_MDMA_C7ESR_OFFSET)
|
||||
#define STM32_MDMA_C8ESR (STM32_MDMA_BASE+STM32_MDMA_C8ESR_OFFSET)
|
||||
#define STM32_MDMA_C9ESR (STM32_MDMA_BASE+STM32_MDMA_C9ESR_OFFSET)
|
||||
#define STM32_MDMA_C10ESR (STM32_MDMA_BASE+STM32_MDMA_C10ESR_OFFSET)
|
||||
#define STM32_MDMA_C11ESR (STM32_MDMA_BASE+STM32_MDMA_C11ESR_OFFSET)
|
||||
#define STM32_MDMA_C12ESR (STM32_MDMA_BASE+STM32_MDMA_C12ESR_OFFSET)
|
||||
#define STM32_MDMA_C13ESR (STM32_MDMA_BASE+STM32_MDMA_C13ESR_OFFSET)
|
||||
#define STM32_MDMA_C14ESR (STM32_MDMA_BASE+STM32_MDMA_C14ESR_OFFSET)
|
||||
#define STM32_MDMA_C15ESR (STM32_MDMA_BASE+STM32_MDMA_C15ESR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXCR(x) (STM32_MDMA_BASE+STM32_MDMA_CXCR_OFFSET(x))
|
||||
#define STM32_MDMA_C0CR (STM32_MDMA_BASE+STM32_MDMA_C0CR_OFFSET)
|
||||
#define STM32_MDMA_C1CR (STM32_MDMA_BASE+STM32_MDMA_C1CR_OFFSET)
|
||||
#define STM32_MDMA_C2CR (STM32_MDMA_BASE+STM32_MDMA_C2CR_OFFSET)
|
||||
#define STM32_MDMA_C3CR (STM32_MDMA_BASE+STM32_MDMA_C3CR_OFFSET)
|
||||
#define STM32_MDMA_C4CR (STM32_MDMA_BASE+STM32_MDMA_C4CR_OFFSET)
|
||||
#define STM32_MDMA_C5CR (STM32_MDMA_BASE+STM32_MDMA_C5CR_OFFSET)
|
||||
#define STM32_MDMA_C6CR (STM32_MDMA_BASE+STM32_MDMA_C6CR_OFFSET)
|
||||
#define STM32_MDMA_C7CR (STM32_MDMA_BASE+STM32_MDMA_C7CR_OFFSET)
|
||||
#define STM32_MDMA_C8CR (STM32_MDMA_BASE+STM32_MDMA_C8CR_OFFSET)
|
||||
#define STM32_MDMA_C9CR (STM32_MDMA_BASE+STM32_MDMA_C9CR_OFFSET)
|
||||
#define STM32_MDMA_C10CR (STM32_MDMA_BASE+STM32_MDMA_C10CR_OFFSET)
|
||||
#define STM32_MDMA_C11CR (STM32_MDMA_BASE+STM32_MDMA_C11CR_OFFSET)
|
||||
#define STM32_MDMA_C12CR (STM32_MDMA_BASE+STM32_MDMA_C12CR_OFFSET)
|
||||
#define STM32_MDMA_C13CR (STM32_MDMA_BASE+STM32_MDMA_C13CR_OFFSET)
|
||||
#define STM32_MDMA_C14CR (STM32_MDMA_BASE+STM32_MDMA_C14CR_OFFSET)
|
||||
#define STM32_MDMA_C15CR (STM32_MDMA_BASE+STM32_MDMA_C15CR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXTCR(x) (STM32_MDMA_BASE+STM32_MDMA_CXTCR_OFFSET(x))
|
||||
#define STM32_MDMA_C0TCR (STM32_MDMA_BASE+STM32_MDMA_C0TCR_OFFSET)
|
||||
#define STM32_MDMA_C1TCR (STM32_MDMA_BASE+STM32_MDMA_C1TCR_OFFSET)
|
||||
#define STM32_MDMA_C2TCR (STM32_MDMA_BASE+STM32_MDMA_C2TCR_OFFSET)
|
||||
#define STM32_MDMA_C3TCR (STM32_MDMA_BASE+STM32_MDMA_C3TCR_OFFSET)
|
||||
#define STM32_MDMA_C4TCR (STM32_MDMA_BASE+STM32_MDMA_C4TCR_OFFSET)
|
||||
#define STM32_MDMA_C5TCR (STM32_MDMA_BASE+STM32_MDMA_C5TCR_OFFSET)
|
||||
#define STM32_MDMA_C6TCR (STM32_MDMA_BASE+STM32_MDMA_C6TCR_OFFSET)
|
||||
#define STM32_MDMA_C7TCR (STM32_MDMA_BASE+STM32_MDMA_C7TCR_OFFSET)
|
||||
#define STM32_MDMA_C8TCR (STM32_MDMA_BASE+STM32_MDMA_C8TCR_OFFSET)
|
||||
#define STM32_MDMA_C9TCR (STM32_MDMA_BASE+STM32_MDMA_C9TCR_OFFSET)
|
||||
#define STM32_MDMA_C10TCR (STM32_MDMA_BASE+STM32_MDMA_C10TCR_OFFSET)
|
||||
#define STM32_MDMA_C11TCR (STM32_MDMA_BASE+STM32_MDMA_C11TCR_OFFSET)
|
||||
#define STM32_MDMA_C12TCR (STM32_MDMA_BASE+STM32_MDMA_C12TCR_OFFSET)
|
||||
#define STM32_MDMA_C13TCR (STM32_MDMA_BASE+STM32_MDMA_C13TCR_OFFSET)
|
||||
#define STM32_MDMA_C14TCR (STM32_MDMA_BASE+STM32_MDMA_C14TCR_OFFSET)
|
||||
#define STM32_MDMA_C15TCR (STM32_MDMA_BASE+STM32_MDMA_C15TCR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXBNDTR(x) (STM32_MDMA_BASE+STM32_MDMA_CXBNDTR_OFFSET(x))
|
||||
#define STM32_MDMA_C0BNDTR (STM32_MDMA_BASE+STM32_MDMA_C0BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C1BNDTR (STM32_MDMA_BASE+STM32_MDMA_C1BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C2BNDTR (STM32_MDMA_BASE+STM32_MDMA_C2BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C3BNDTR (STM32_MDMA_BASE+STM32_MDMA_C3BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C4BNDTR (STM32_MDMA_BASE+STM32_MDMA_C4BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C5BNDTR (STM32_MDMA_BASE+STM32_MDMA_C5BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C6BNDTR (STM32_MDMA_BASE+STM32_MDMA_C6BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C7BNDTR (STM32_MDMA_BASE+STM32_MDMA_C7BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C8BNDTR (STM32_MDMA_BASE+STM32_MDMA_C8BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C9BNDTR (STM32_MDMA_BASE+STM32_MDMA_C9BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C10BNDTR (STM32_MDMA_BASE+STM32_MDMA_C10BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C11BNDTR (STM32_MDMA_BASE+STM32_MDMA_C11BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C12BNDTR (STM32_MDMA_BASE+STM32_MDMA_C12BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C13BNDTR (STM32_MDMA_BASE+STM32_MDMA_C13BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C14BNDTR (STM32_MDMA_BASE+STM32_MDMA_C14BNDTR_OFFSET)
|
||||
#define STM32_MDMA_C15BNDTR (STM32_MDMA_BASE+STM32_MDMA_C15BNDTR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXBRUR(x) (STM32_MDMA_BASE+STM32_MDMA_CXBRUR_OFFSET(x))
|
||||
#define STM32_MDMA_C0BRUR (STM32_MDMA_BASE+STM32_MDMA_C0BRUR_OFFSET)
|
||||
#define STM32_MDMA_C1BRUR (STM32_MDMA_BASE+STM32_MDMA_C1BRUR_OFFSET)
|
||||
#define STM32_MDMA_C2BRUR (STM32_MDMA_BASE+STM32_MDMA_C2BRUR_OFFSET)
|
||||
#define STM32_MDMA_C3BRUR (STM32_MDMA_BASE+STM32_MDMA_C3BRUR_OFFSET)
|
||||
#define STM32_MDMA_C4BRUR (STM32_MDMA_BASE+STM32_MDMA_C4BRUR_OFFSET)
|
||||
#define STM32_MDMA_C5BRUR (STM32_MDMA_BASE+STM32_MDMA_C5BRUR_OFFSET)
|
||||
#define STM32_MDMA_C6BRUR (STM32_MDMA_BASE+STM32_MDMA_C6BRUR_OFFSET)
|
||||
#define STM32_MDMA_C7BRUR (STM32_MDMA_BASE+STM32_MDMA_C7BRUR_OFFSET)
|
||||
#define STM32_MDMA_C8BRUR (STM32_MDMA_BASE+STM32_MDMA_C8BRUR_OFFSET)
|
||||
#define STM32_MDMA_C9BRUR (STM32_MDMA_BASE+STM32_MDMA_C9BRUR_OFFSET)
|
||||
#define STM32_MDMA_C10BRUR (STM32_MDMA_BASE+STM32_MDMA_C10BRUR_OFFSET)
|
||||
#define STM32_MDMA_C11BRUR (STM32_MDMA_BASE+STM32_MDMA_C11BRUR_OFFSET)
|
||||
#define STM32_MDMA_C12BRUR (STM32_MDMA_BASE+STM32_MDMA_C12BRUR_OFFSET)
|
||||
#define STM32_MDMA_C13BRUR (STM32_MDMA_BASE+STM32_MDMA_C13BRUR_OFFSET)
|
||||
#define STM32_MDMA_C14BRUR (STM32_MDMA_BASE+STM32_MDMA_C14BRUR_OFFSET)
|
||||
#define STM32_MDMA_C15BRUR (STM32_MDMA_BASE+STM32_MDMA_C15BRUR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXLAR(x) (STM32_MDMA_BASE+STM32_MDMA_CXLAR_OFFSET(x))
|
||||
#define STM32_MDMA_C0LAR (STM32_MDMA_BASE+STM32_MDMA_C0LAR_OFFSET)
|
||||
#define STM32_MDMA_C1LAR (STM32_MDMA_BASE+STM32_MDMA_C1LAR_OFFSET)
|
||||
#define STM32_MDMA_C2LAR (STM32_MDMA_BASE+STM32_MDMA_C2LAR_OFFSET)
|
||||
#define STM32_MDMA_C3LAR (STM32_MDMA_BASE+STM32_MDMA_C3LAR_OFFSET)
|
||||
#define STM32_MDMA_C4LAR (STM32_MDMA_BASE+STM32_MDMA_C4LAR_OFFSET)
|
||||
#define STM32_MDMA_C5LAR (STM32_MDMA_BASE+STM32_MDMA_C5LAR_OFFSET)
|
||||
#define STM32_MDMA_C6LAR (STM32_MDMA_BASE+STM32_MDMA_C6LAR_OFFSET)
|
||||
#define STM32_MDMA_C7LAR (STM32_MDMA_BASE+STM32_MDMA_C7LAR_OFFSET)
|
||||
#define STM32_MDMA_C8LAR (STM32_MDMA_BASE+STM32_MDMA_C8LAR_OFFSET)
|
||||
#define STM32_MDMA_C9LAR (STM32_MDMA_BASE+STM32_MDMA_C9LAR_OFFSET)
|
||||
#define STM32_MDMA_C10LAR (STM32_MDMA_BASE+STM32_MDMA_C10LAR_OFFSET)
|
||||
#define STM32_MDMA_C11LAR (STM32_MDMA_BASE+STM32_MDMA_C11LAR_OFFSET)
|
||||
#define STM32_MDMA_C12LAR (STM32_MDMA_BASE+STM32_MDMA_C12LAR_OFFSET)
|
||||
#define STM32_MDMA_C13LAR (STM32_MDMA_BASE+STM32_MDMA_C13LAR_OFFSET)
|
||||
#define STM32_MDMA_C14LAR (STM32_MDMA_BASE+STM32_MDMA_C14LAR_OFFSET)
|
||||
#define STM32_MDMA_C15LAR (STM32_MDMA_BASE+STM32_MDMA_C15LAR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXTBR(x) (STM32_MDMA_BASE+STM32_MDMA_CXTBR_OFFSET(x))
|
||||
#define STM32_MDMA_C0TBR (STM32_MDMA_BASE+STM32_MDMA_C0TBR_OFFSET)
|
||||
#define STM32_MDMA_C1TBR (STM32_MDMA_BASE+STM32_MDMA_C1TBR_OFFSET)
|
||||
#define STM32_MDMA_C2TBR (STM32_MDMA_BASE+STM32_MDMA_C2TBR_OFFSET)
|
||||
#define STM32_MDMA_C3TBR (STM32_MDMA_BASE+STM32_MDMA_C3TBR_OFFSET)
|
||||
#define STM32_MDMA_C4TBR (STM32_MDMA_BASE+STM32_MDMA_C4TBR_OFFSET)
|
||||
#define STM32_MDMA_C5TBR (STM32_MDMA_BASE+STM32_MDMA_C5TBR_OFFSET)
|
||||
#define STM32_MDMA_C6TBR (STM32_MDMA_BASE+STM32_MDMA_C6TBR_OFFSET)
|
||||
#define STM32_MDMA_C7TBR (STM32_MDMA_BASE+STM32_MDMA_C7TBR_OFFSET)
|
||||
#define STM32_MDMA_C8TBR (STM32_MDMA_BASE+STM32_MDMA_C8TBR_OFFSET)
|
||||
#define STM32_MDMA_C9TBR (STM32_MDMA_BASE+STM32_MDMA_C9TBR_OFFSET)
|
||||
#define STM32_MDMA_C10TBR (STM32_MDMA_BASE+STM32_MDMA_C10TBR_OFFSET)
|
||||
#define STM32_MDMA_C11TBR (STM32_MDMA_BASE+STM32_MDMA_C11TBR_OFFSET)
|
||||
#define STM32_MDMA_C12TBR (STM32_MDMA_BASE+STM32_MDMA_C12TBR_OFFSET)
|
||||
#define STM32_MDMA_C13TBR (STM32_MDMA_BASE+STM32_MDMA_C13TBR_OFFSET)
|
||||
#define STM32_MDMA_C14TBR (STM32_MDMA_BASE+STM32_MDMA_C14TBR_OFFSET)
|
||||
#define STM32_MDMA_C15TBR (STM32_MDMA_BASE+STM32_MDMA_C15TBR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXMAR(x) (STM32_MDMA_BASE+STM32_MDMA_CXMAR_OFFSET(x))
|
||||
#define STM32_MDMA_C0MAR (STM32_MDMA_BASE+STM32_MDMA_C0MAR_OFFSET)
|
||||
#define STM32_MDMA_C1MAR (STM32_MDMA_BASE+STM32_MDMA_C1MAR_OFFSET)
|
||||
#define STM32_MDMA_C2MAR (STM32_MDMA_BASE+STM32_MDMA_C2MAR_OFFSET)
|
||||
#define STM32_MDMA_C3MAR (STM32_MDMA_BASE+STM32_MDMA_C3MAR_OFFSET)
|
||||
#define STM32_MDMA_C4MAR (STM32_MDMA_BASE+STM32_MDMA_C4MAR_OFFSET)
|
||||
#define STM32_MDMA_C5MAR (STM32_MDMA_BASE+STM32_MDMA_C5MAR_OFFSET)
|
||||
#define STM32_MDMA_C6MAR (STM32_MDMA_BASE+STM32_MDMA_C6MAR_OFFSET)
|
||||
#define STM32_MDMA_C7MAR (STM32_MDMA_BASE+STM32_MDMA_C7MAR_OFFSET)
|
||||
#define STM32_MDMA_C8MAR (STM32_MDMA_BASE+STM32_MDMA_C8MAR_OFFSET)
|
||||
#define STM32_MDMA_C9MAR (STM32_MDMA_BASE+STM32_MDMA_C9MAR_OFFSET)
|
||||
#define STM32_MDMA_C10MAR (STM32_MDMA_BASE+STM32_MDMA_C10MAR_OFFSET)
|
||||
#define STM32_MDMA_C11MAR (STM32_MDMA_BASE+STM32_MDMA_C11MAR_OFFSET)
|
||||
#define STM32_MDMA_C12MAR (STM32_MDMA_BASE+STM32_MDMA_C12MAR_OFFSET)
|
||||
#define STM32_MDMA_C13MAR (STM32_MDMA_BASE+STM32_MDMA_C13MAR_OFFSET)
|
||||
#define STM32_MDMA_C14MAR (STM32_MDMA_BASE+STM32_MDMA_C14MAR_OFFSET)
|
||||
#define STM32_MDMA_C15MAR (STM32_MDMA_BASE+STM32_MDMA_C15MAR_OFFSET)
|
||||
|
||||
#define STM32_MDMA_CXMDR(x) (STM32_MDMA_BASE+STM32_MDMA_CXMDR_OFFSET(x))
|
||||
#define STM32_MDMA_C0MDR (STM32_MDMA_BASE+STM32_MDMA_C0MDR_OFFSET)
|
||||
#define STM32_MDMA_C1MDR (STM32_MDMA_BASE+STM32_MDMA_C1MDR_OFFSET)
|
||||
#define STM32_MDMA_C2MDR (STM32_MDMA_BASE+STM32_MDMA_C2MDR_OFFSET)
|
||||
#define STM32_MDMA_C3MDR (STM32_MDMA_BASE+STM32_MDMA_C3MDR_OFFSET)
|
||||
#define STM32_MDMA_C4MDR (STM32_MDMA_BASE+STM32_MDMA_C4MDR_OFFSET)
|
||||
#define STM32_MDMA_C5MDR (STM32_MDMA_BASE+STM32_MDMA_C5MDR_OFFSET)
|
||||
#define STM32_MDMA_C6MDR (STM32_MDMA_BASE+STM32_MDMA_C6MDR_OFFSET)
|
||||
#define STM32_MDMA_C7MDR (STM32_MDMA_BASE+STM32_MDMA_C7MDR_OFFSET)
|
||||
#define STM32_MDMA_C8MDR (STM32_MDMA_BASE+STM32_MDMA_C8MDR_OFFSET)
|
||||
#define STM32_MDMA_C9MDR (STM32_MDMA_BASE+STM32_MDMA_C9MDR_OFFSET)
|
||||
#define STM32_MDMA_C10MDR (STM32_MDMA_BASE+STM32_MDMA_C10MDR_OFFSET)
|
||||
#define STM32_MDMA_C11MDR (STM32_MDMA_BASE+STM32_MDMA_C11MDR_OFFSET)
|
||||
#define STM32_MDMA_C12MDR (STM32_MDMA_BASE+STM32_MDMA_C12MDR_OFFSET)
|
||||
#define STM32_MDMA_C13MDR (STM32_MDMA_BASE+STM32_MDMA_C13MDR_OFFSET)
|
||||
#define STM32_MDMA_C14MDR (STM32_MDMA_BASE+STM32_MDMA_C14MDR_OFFSET)
|
||||
#define STM32_MDMA_C15MDR (STM32_MDMA_BASE+STM32_MDMA_C15MDR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* MDMA global interrupt/status register */
|
||||
|
||||
#define MDMA_CXISR_GIF(x) (1 << x)
|
||||
|
||||
/* MDMA channel x interrupt/status register and channel x interrupt flag clear register */
|
||||
|
||||
#define MDMA_INT_TEIF (1 << 0) /* Bit 0: Channel X transfer error flag */
|
||||
#define BDMA_INT_CTCIF (1 << 1) /* Bit 1: Channel X transfer complete flag */
|
||||
#define BDMA_INT_BRTIF (1 << 2) /* Bit 2: Channel X block repeat transfer complete flag */
|
||||
#define BDMA_INT_BTIF (1 << 3) /* Bit 3: Channel X block transfer complete flag */
|
||||
#define BDMA_INT_TCIF (1 << 4) /* Bit 4: Channel X buffer transfer complete interrupt flag */
|
||||
#define BDMA_INT_CRQA (1 << 5) /* Bit 5: Channel X request active flag */
|
||||
|
||||
/* MDMA channel x error status register */
|
||||
|
||||
#define MDMA_CESR_TEA_SHIFT (0) /* Bits 0-6: Transfer error address */
|
||||
#define MDMA_CESR_TEA_MASK (0x7f << MDMA_CESR_TEA_SHIFT)
|
||||
#define MDMA_CESR_TED (7) /* Bit 7: Transfer error direction */
|
||||
#define MDMA_CESR_TELD (8) /* Bit 8: Transfer error link data */
|
||||
#define MDMA_CESR_TEMD (9) /* Bit 9: Transfer error mask data */
|
||||
#define MDMA_CESR_ASE (10) /* Bit 10: Address/size error */
|
||||
#define MDMA_CESR_BSE (11) /* Bit 11: Block size error */
|
||||
|
||||
/* MDMA channel x control register */
|
||||
|
||||
#define MDMA_CCR_EN (0) /* Bit 0: Channel eanble / flag channel ready */
|
||||
#define MDMA_CCR_TEIE (1) /* Bit 1: Transfer error interrupt enable */
|
||||
#define MDMA_CCR_CTCIE (2) /* Bit 2: Channel transfer complete interrupt enable */
|
||||
#define MDMA_CCR_BRTIE (3) /* Bit 3: Block repeat transfer interrupt enable */
|
||||
#define MDMA_CCR_BTIE (4) /* Bit 4: Block transfer interrupt enable */
|
||||
#define MDMA_CCR_TCIE (5) /* Bit 5: Buffer transfer complete interrupt enable */
|
||||
#define MDMA_CCR_PL_SHIFT (6) /* Bis 6-7: Priority level */
|
||||
#define MDMA_CCR_PL_MASK (3 << MDMA_CCR_PL_SHIFT)
|
||||
# define MDMA_CCR_PRILO (0 << MDMA_CCR_PL_SHIFT) /* 00: Low */
|
||||
# define MDMA_CCR_PRIMED (1 << MDMA_CCR_PL_SHIFT) /* 01: Medium */
|
||||
# define MDMA_CCR_PRIHI (2 << MDMA_CCR_PL_SHIFT) /* 10: High */
|
||||
# define MDMA_CCR_PRIVERYHI (3 << MDMA_CCR_PL_SHIFT) /* 11: Very high */
|
||||
#define MDMA_CCR_BEX (12) /* Bit 12: Byte endianess exchange */
|
||||
#define MDMA_CCR_HEX (13) /* Bit 13: Half word endianess exchange */
|
||||
#define MDMA_CCR_WEX (14) /* Bit 14: Word endianess exchange */
|
||||
#define MDMA_CCR_SWRQ (16) /* Bit 16: Software request */
|
||||
|
||||
/* MDMA channel x transfer configuration register */
|
||||
|
||||
#define MDMA_CTCR_SINC_SHIFT (0) /* Bits 0-1: Source increment mode */
|
||||
#define MDMA_CTCR_SINC_MASK (3 << MDMA_CTCR_SINC_SHIFT)
|
||||
# define MDMA_CTCR_SINC_FIXED (0 << MDMA_CTCR_SINC_SHIFT) /* 00: */
|
||||
# define MDMA_CTCR_SINC_INCR (2 << MDMA_CTCR_SINC_SHIFT) /* 10: */
|
||||
# define MDMA_CTCR_SINC_DECR (3 << MDMA_CTCR_SINC_SHIFT) /* 11: */
|
||||
#define MDMA_CTCR_DINC_SHIFT (2) /* Bits 2-3: Destination increment mode */
|
||||
#define MDMA_CTCR_DINC_MASK (3 << MDMA_CTCR_DINC_SHIFT)
|
||||
# define MDMA_CTCR_DINC_FIXED (0 << MDMA_CTCR_DINC_SHIFT) /* 00: */
|
||||
# define MDMA_CTCR_DINC_INCR (2 << MDMA_CTCR_DINC_SHIFT) /* 10: */
|
||||
# define MDMA_CTCR_DINC_DECR (3 << MDMA_CTCR_DINC_SHIFT) /* 11: */
|
||||
#define MDMA_CTCR_SSIZE_SHIFT (4) /* Bits 4-5: Source data size */
|
||||
#define MDMA_CTCR_SSIZE_MASK (3 << MDMA_CTCR_SSIZE_SHIFT)
|
||||
# define MDMA_CTCR_SSIZE_8BITS (0 << MDMA_CTCR_SSIZE_SHIFT) /* 00: */
|
||||
# define MDMA_CTCR_SSIZE_16BITS (1 << MDMA_CTCR_SSIZE_SHIFT) /* 01: */
|
||||
# define MDMA_CTCR_SSIZE_32BITS (2 << MDMA_CTCR_SSIZE_SHIFT) /* 10: */
|
||||
# define MDMA_CTCR_SSIZE_64BITS (3 << MDMA_CTCR_SSIZE_SHIFT) /* 11: */
|
||||
#define MDMA_CTCR_DSIZE_SHIFT (6) /* Bits 6-7: Destination data size */
|
||||
#define MDMA_CTCR_DSIZE_MASK (3 << MDMA_CTCR_DSIZE_SHIFT)
|
||||
# define MDMA_CTCR_DSIZE_8BITS (0 << MDMA_CTCR_DSIZE_SHIFT) /* 00: */
|
||||
# define MDMA_CTCR_DSIZE_16BITS (1 << MDMA_CTCR_DSIZE_SHIFT) /* 01: */
|
||||
# define MDMA_CTCR_DSIZE_32BITS (2 << MDMA_CTCR_DSIZE_SHIFT) /* 10: */
|
||||
# define MDMA_CTCR_DSIZE_64BITS (3 << MDMA_CTCR_DSIZE_SHIFT) /* 11: */
|
||||
#define MDMA_CTCR_SINCOS_SHIFT (8) /* Bits 8-9: Source increment offset size */
|
||||
#define MDMA_CTCR_SINCOS_MASK (3 << MDMA_CTCR_SINCOS_SHIFT)
|
||||
# define MDMA_CTCR_SINCOS_8BITS (0 << MDMA_CTCR_SINCOS_SHIFT) /* 00: */
|
||||
# define MDMA_CTCR_SINCOS_16BITS (1 << MDMA_CTCR_SINCOS_SHIFT) /* 01: */
|
||||
# define MDMA_CTCR_SINCOS_32BITS (2 << MDMA_CTCR_SINCOS_SHIFT) /* 10: */
|
||||
# define MDMA_CTCR_SINCOS_64BITS (3 << MDMA_CTCR_SINCOS_SHIFT) /* 11: */
|
||||
#define MDMA_CTCR_DINCOS_SHIFT (10) /* Bits 10-11: Destination increment offset size */
|
||||
#define MDMA_CTCR_DINCOS_MASK (7 << MDMA_CTCR_DINCOS_SHIFT)
|
||||
# define MDMA_CTCR_DINCOS_8BITS (0 << MDMA_CTCR_DINCOS_SHIFT) /* 00: */
|
||||
# define MDMA_CTCR_DINCOS_16BITS (1 << MDMA_CTCR_DINCOS_SHIFT) /* 01: */
|
||||
# define MDMA_CTCR_DINCOS_32BITS (2 << MDMA_CTCR_DINCOS_SHIFT) /* 10: */
|
||||
# define MDMA_CTCR_DINCOS_64BITS (3 << MDMA_CTCR_DINCOS_SHIFT) /* 11: */
|
||||
#define MDMA_CTCR_SBURST_SHIFT (12) /* Bits 12-14: Source burst transfer configuration */
|
||||
#define MDMA_CTCR_SBURST_MASK (7 << MDMA_CTCR_SBURST_SHIFT)
|
||||
# define MDMA_CTCR_SBURST_1 (0 << MDMA_CTCR_SBURST_SHIFT) /* 000: */
|
||||
# define MDMA_CTCR_SBURST_2 (1 << MDMA_CTCR_SBURST_SHIFT) /* 001: */
|
||||
# define MDMA_CTCR_SBURST_4 (2 << MDMA_CTCR_SBURST_SHIFT) /* 010: */
|
||||
# define MDMA_CTCR_SBURST_8 (3 << MDMA_CTCR_SBURST_SHIFT) /* 011: */
|
||||
# define MDMA_CTCR_SBURST_16 (4 << MDMA_CTCR_SBURST_SHIFT) /* 100: */
|
||||
# define MDMA_CTCR_SBURST_32 (5 << MDMA_CTCR_SBURST_SHIFT) /* 101: */
|
||||
# define MDMA_CTCR_SBURST_64 (6 << MDMA_CTCR_SBURST_SHIFT) /* 110: */
|
||||
# define MDMA_CTCR_SBURST_128 (7 << MDMA_CTCR_SBURST_SHIFT) /* 111: */
|
||||
#define MDMA_CTCR_DBURST_SHIFT (15) /* Bits 15-16: Destination burst transfer configuration */
|
||||
#define MDMA_CTCR_DBURST_MASK (7 << MDMA_CTCR_DBURST_SHIFT)
|
||||
# define MDMA_CTCR_DBURST_1 (0 << MDMA_CTCR_DBURST_SHIFT) /* 000: */
|
||||
# define MDMA_CTCR_DBURST_2 (1 << MDMA_CTCR_DBURST_SHIFT) /* 001: */
|
||||
# define MDMA_CTCR_DBURST_4 (2 << MDMA_CTCR_DBURST_SHIFT) /* 010: */
|
||||
# define MDMA_CTCR_DBURST_8 (3 << MDMA_CTCR_DBURST_SHIFT) /* 011: */
|
||||
# define MDMA_CTCR_DBURST_16 (4 << MDMA_CTCR_DBURST_SHIFT) /* 100: */
|
||||
# define MDMA_CTCR_DBURST_32 (5 << MDMA_CTCR_DBURST_SHIFT) /* 101: */
|
||||
# define MDMA_CTCR_DBURST_64 (6 << MDMA_CTCR_DBURST_SHIFT) /* 110: */
|
||||
# define MDMA_CTCR_DBURST_128 (7 << MDMA_CTCR_DBURST_SHIFT) /* 111: */
|
||||
#define MDMA_CTCR_TLEN_SHIFT (18) /* Bits 18-24: Buffer transfer length - 1 */
|
||||
#define MDMA_CTCR_TLEN_MASK (0x7f << MDMA_CTCR_TLEN_SHIFT)
|
||||
# define MDMA_CTCR_TLEN(len) (((len-1) << MDMA_CTCR_TLEN_SHIFT) & MDMA_CTCR_TLEN_MASK)
|
||||
#define MDMA_CTCR_PKE (25) /* Bit 25: Pack enable */
|
||||
#define MDMA_CTCR_PAM_SHIFT (26) /* Bits 26-27: Padding/alignement mode */
|
||||
#define MDMA_CTCR_PAM_MASK (3 << MDMA_CTCR_PAM_SHIFT)
|
||||
# define MDMA_CTCR_PAM_RIGHT (0 << MDMA_CTCR_PAM_SHIFT) /* 00: */
|
||||
# define MDMA_CTCR_PAM_SINRIGHT (1 << MDMA_CTCR_PAM_SHIFT) /* 01: */
|
||||
# define MDMA_CTCR_PAM_LEFT (2 << MDMA_CTCR_PAM_SHIFT) /* 10: */
|
||||
#define MDMA_CTCR_TRGM_SHIFT (28) /* Bits 28-29: Trigger mode */
|
||||
#define MDMA_CTCR_TRGM_MASK (3 << MDMA_CTCR_TRGM_SHIFT)
|
||||
# define MDMA_CTCR_TRGM_BUFFER (0 << MDMA_CTCR_TRGM_SHIFT) /* 00: */
|
||||
# define MDMA_CTCR_TRGM_BLOCK (1 << MDMA_CTCR_TRGM_SHIFT) /* 01: */
|
||||
# define MDMA_CTCR_TRGM_RBLOCK (2 << MDMA_CTCR_TRGM_SHIFT) /* 10: */
|
||||
# define MDMA_CTCR_TRGM_DATA (3 << MDMA_CTCR_TRGM_SHIFT) /* 11: */
|
||||
#define MDMA_CTCR_SWRM (30) /* Bit 30: Software request mode */
|
||||
#define MDMA_CTCR_BWM (31) /* Bit 31: Bufferable write mode */
|
||||
|
||||
/* MDMA channel x block number of data register */
|
||||
|
||||
#define MDMA_CBNDTR_BNDT_SHIFT (0) /* Bits 0-16: Block number of data bytes to transfer */
|
||||
#define MDMA_CBNDTR_BNDT_MASK (0x1ffff << MDMA_CBNDTR_BNDT_SHIFT)
|
||||
#define MDMA_CBNDTR_BNDT_BRSUM (18) /* Bit 18: Block repeat source address update mode */
|
||||
#define MDMA_CBNDTR_BNDT_BRDUM (19) /* Bit 19: Block repeat destination address update mode */
|
||||
#define MDMA_CBNDTR_BNDT_SHIFT (20) /* Bits 20-31: Block repeat count */
|
||||
#define MDMA_CBNDTR_BNDT_MASK (0xfff << MDMA_CBNDTR_BNDT_SHIFT)
|
||||
|
||||
/* MDMA channel x block repeat address update register */
|
||||
|
||||
#define MDMA_CBRUR_SUV_SHIFT (0) /* Bits 0-15: Source address update value */
|
||||
#define MDMA_CBRUR_SUV_MASK (0xff << MDMA_CBRUR_SUV_SHIFT)
|
||||
#define MDMA_CBRUR_DUV_SHIFT (16) /* Bits 16-31: Destination address update value */
|
||||
#define MDMA_CBRUR_DUV_MASK (0xff << MDMA_CBRUR_DUV_SHIFT)
|
||||
|
||||
/* MDMA channel x trigger and bus selection register */
|
||||
|
||||
#define MDMA_TSEL_SHIFT (0) /* Bits 0-5: Trigger selection */
|
||||
#define MDMA_TSEL_MASK (0x3f << MDMA_TSEL_SHIFT)
|
||||
#define MDMA_TSEL_SBUS (16) /* Bit 16: Source BUS select */
|
||||
#define MDMA_TSEL_DBUS (17) /* Bit 16: Destination BUS select */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MDMA_H */
|
||||
File diff suppressed because it is too large
Load Diff
195
arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h
Normal file
195
arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h
Normal file
@ -0,0 +1,195 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
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|
||||
/* DMAMUX1 mapping ****************************************************/
|
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|
||||
/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7.
|
||||
* DMAMUX1 channels 8 to 15 are connected to DMA2 channels 0 to 7.
|
||||
*/
|
||||
|
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#define DMAMUX1_REQ_GEN0 (1)
|
||||
#define DMAMUX1_REQ_GEN1 (2)
|
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#define DMAMUX1_REQ_GEN2 (3)
|
||||
#define DMAMUX1_REQ_GEN3 (4)
|
||||
#define DMAMUX1_REQ_GEN4 (5)
|
||||
#define DMAMUX1_REQ_GEN5 (6)
|
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#define DMAMUX1_REQ_GEN6 (7)
|
||||
#define DMAMUX1_REQ_GEN7 (8)
|
||||
#define DMAMUX1_ADC1 (9)
|
||||
#define DMAMUX1_ADC2 (10)
|
||||
#define DMAMUX1_TIM1_CH1 (11)
|
||||
#define DMAMUX1_TIM1_CH2 (12)
|
||||
#define DMAMUX1_TIM1_CH3 (13)
|
||||
#define DMAMUX1_TIM1_CH4 (14)
|
||||
#define DMAMUX1_TIM1_UP (15)
|
||||
#define DMAMUX1_TIM1_TRIG (16)
|
||||
#define DMAMUX1_TIM1_COM (17)
|
||||
#define DMAMUX1_TIM2_CH1 (18)
|
||||
#define DMAMUX1_TIM2_CH2 (19)
|
||||
#define DMAMUX1_TIM2_CH3 (20)
|
||||
#define DMAMUX1_TIM2_CH4 (21)
|
||||
#define DMAMUX1_TIM2_UP (22)
|
||||
#define DMAMUX1_TIM3_CH1 (23)
|
||||
#define DMAMUX1_TIM3_CH2 (24)
|
||||
#define DMAMUX1_TIM3_CH3 (25)
|
||||
#define DMAMUX1_TIM3_CH4 (26)
|
||||
#define DMAMUX1_TIM3_UP (27)
|
||||
#define DMAMUX1_TIM3_TRIG (28)
|
||||
#define DMAMUX1_TIM4_CH1 (29)
|
||||
#define DMAMUX1_TIM4_CH2 (30)
|
||||
#define DMAMUX1_TIM4_CH3 (31)
|
||||
#define DMAMUX1_TIM4_UP (32)
|
||||
#define DMAMUX1_I2C1_RX (33)
|
||||
#define DMAMUX1_I2C1_TX (34)
|
||||
#define DMAMUX1_I2C2_RX (35)
|
||||
#define DMAMUX1_I2C2_TX (36)
|
||||
#define DMAMUX1_SPI1_RX (37)
|
||||
#define DMAMUX1_SPI1_TX (38)
|
||||
#define DMAMUX1_SPI2_RX (39)
|
||||
#define DMAMUX1_SPI2_TX (40)
|
||||
#define DMAMUX1_USART1_TX (41)
|
||||
#define DMAMUX1_USART1_RX (42)
|
||||
#define DMAMUX1_USART2_RX (43)
|
||||
#define DMAMUX1_USART2_TX (44)
|
||||
#define DMAMUX1_USART3_RX (45)
|
||||
#define DMAMUX1_USART3_TX (46)
|
||||
#define DMAMUX1_TIM8_CH1 (47)
|
||||
#define DMAMUX1_TIM8_CH2 (48)
|
||||
#define DMAMUX1_TIM8_CH3 (49)
|
||||
#define DMAMUX1_TIM8_CH4 (50)
|
||||
#define DMAMUX1_TIM8_UP (51)
|
||||
#define DMAMUX1_TIM8_TRIG (52)
|
||||
#define DMAMUX1_TIM8_COM (53)
|
||||
/* DMAMUX1 54: Reserved */
|
||||
#define DMAMUX1_TIM5_CH1 (55)
|
||||
#define DMAMUX1_TIM5_CH2 (56)
|
||||
#define DMAMUX1_TIM5_CH3 (57)
|
||||
#define DMAMUX1_TIM5_CH4 (58)
|
||||
#define DMAMUX1_TIM5_UP (59)
|
||||
#define DMAMUX1_TIM5_TRIG (60)
|
||||
#define DMAMUX1_SPI3_RX (61)
|
||||
#define DMAMUX1_SPI3_TX (62)
|
||||
#define DMAMUX1_UART4_RX (63)
|
||||
#define DMAMUX1_UART4_TX (64)
|
||||
#define DMAMUX1_UART5_RX (65)
|
||||
#define DMAMUX1_UART5_TX (66)
|
||||
#define DMAMUX1_DAC_CH1 (67)
|
||||
#define DMAMUX1_DAC_CH2 (68)
|
||||
#define DMAMUX1_TIM6_UP (69)
|
||||
#define DMAMUX1_TIM7_UP (70)
|
||||
#define DMAMUX1_USART6_RX (71)
|
||||
#define DMAMUX1_USART6_TX (72)
|
||||
#define DMAMUX1_I2C3_RX (73)
|
||||
#define DMAMUX1_I2C3_TX (74)
|
||||
#define DMAMUX1_DCMI (75)
|
||||
#define DMAMUX1_CRYPT_IN (76)
|
||||
#define DMAMUX1_CRYPT_OUT (77)
|
||||
#define DMAMUX1_HASH_IN (78)
|
||||
#define DMAMUX1_UART7_RX (70)
|
||||
#define DMAMUX1_UART7_TX (80)
|
||||
#define DMAMUX1_UART8_RX (81)
|
||||
#define DMAMUX1_UART8_TX (82)
|
||||
#define DMAMUX1_SPI4_RX (83)
|
||||
#define DMAMUX1_SPI4_TX (84)
|
||||
#define DMAMUX1_SPI5_RX (85)
|
||||
#define DMAMUX1_SPI5_TX (86)
|
||||
#define DMAMUX1_SAI1A (87)
|
||||
#define DMAMUX1_SAI1B (88)
|
||||
#define DMAMUX1_SAI2A (89)
|
||||
#define DMAMUX1_SAI2B (90)
|
||||
#define DMAMUX1_SWPMI_RX (91)
|
||||
#define DMAMUX1_SWPMI_TX (92)
|
||||
#define DMAMUX1_SPDIFRX_DAT (93)
|
||||
#define DMAMUX1_SPDIFRX_CTRL (94)
|
||||
#define DMAMUX1_HR_REQ1 (95)
|
||||
#define DMAMUX1_HR_REQ2 (96)
|
||||
#define DMAMUX1_HR_REQ3 (97)
|
||||
#define DMAMUX1_HR_REQ4 (98)
|
||||
#define DMAMUX1_HR_REQ5 (99)
|
||||
#define DMAMUX1_HR_REQ6 (100)
|
||||
#define DMAMUX1_DFSDM1_0 (101)
|
||||
#define DMAMUX1_DFSDM1_1 (102)
|
||||
#define DMAMUX1_DFSDM1_2 (103)
|
||||
#define DMAMUX1_DFSDM1_3 (104)
|
||||
#define DMAMUX1_TIM15_CH1 (105)
|
||||
#define DMAMUX1_TIM15_UP (106)
|
||||
#define DMAMUX1_TIM15_TRIG (107)
|
||||
#define DMAMUX1_TIM15_COM (108)
|
||||
#define DMAMUX1_TIM16_CH1 (109)
|
||||
#define DMAMUX1_TIM16_UP (110)
|
||||
#define DMAMUX1_TIM17_CH1 (111)
|
||||
#define DMAMUX1_TIM17_UP (112)
|
||||
#define DMAMUX1_SAI3A (113)
|
||||
#define DMAMUX1_SAI3B (114)
|
||||
#define DMAMUX1_ADC3 (115)
|
||||
/* DMAMUX1 116-127: Reserved */
|
||||
|
||||
/* DMAMUX2 mapping ****************************************************/
|
||||
|
||||
/* NOTE: DMAMUX2 channels 0 to 7 are connected to BDMA channels 0 to 7 */
|
||||
|
||||
#define DMAMUX2_REQ_GEN0 (1)
|
||||
#define DMAMUX2_REQ_GEN1 (2)
|
||||
#define DMAMUX2_REQ_GEN2 (3)
|
||||
#define DMAMUX2_REQ_GEN3 (4)
|
||||
#define DMAMUX2_REQ_GEN4 (5)
|
||||
#define DMAMUX2_REQ_GEN5 (6)
|
||||
#define DMAMUX2_REQ_GEN6 (7)
|
||||
#define DMAMUX2_REQ_GEN7 (8)
|
||||
#define DMAMUX2_LPUART1_RX (9)
|
||||
#define DMAMUX2_LPUART1_TX (10)
|
||||
#define DMAMUX2_SPI6_RX (11)
|
||||
#define DMAMUX2_SPI6_TX (12)
|
||||
#define DMAMUX2_I2C4_RX (13)
|
||||
#define DMAMUX2_I2C4_TX (14)
|
||||
#define DMAMUX2_SAI4A (15)
|
||||
#define DMAMUX2_SAI4B (16)
|
||||
#define DMAMUX2_ADC3 (17)
|
||||
/* DMAMUX2 18-32: Reserved */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H */
|
||||
Loading…
Reference in New Issue
Block a user