Update ARMv7-R system control register definitions from TRM
This commit is contained in:
Gregory Nutt
parent
67604e661f
commit
b9feaf13b0
@ -47,22 +47,6 @@
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#ifdef CONFIG_ARCH_FPU
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_copyarmstate
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*
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@ -76,7 +60,7 @@ void up_copyarmstate(uint32_t *dest, uint32_t *src)
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{
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int i;
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/* In the Cortex-M model, the state is copied from the stack to the TCB,
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/* In the Cortex-R model, the state is copied from the stack to the TCB,
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* but only a reference is passed to get the state from the TCB. So the
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* following check avoids copying the TCB save area onto itself:
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*/
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@ -55,7 +55,12 @@
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#undef CPU_CACHE_ROUND_ROBIN
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#undef CPU_DCACHE_DISABLE
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#undef CPU_ICACHE_DISABLE
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#undef CPU_AFE_ENABLE
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#define CPU_SCTLR_CCP15BEN 1
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#define CPU_BACKGROUND_REGION 1
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#undef CPU_DIV0_FAULT
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#undef CPU_FAST_INTERRUPT
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#undef CPU_IMPL_VECTORS
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#undef CPU_NONMASKABLE_FIQ
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/* There are three operational memory configurations:
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*
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@ -145,32 +150,72 @@ __start:
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* example, we get here via a bootloader and the control register is in some
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* unknown state.
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*
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* SCTLR_A Bit 1: Strict alignment disabled (reset value)
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* SCTLR_C Bit 2: DCache disabled (reset value)
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* SCTLR_A Bit 1: Strict alignment disabled
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* SCTLR_C Bit 2: DCache disabled
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* SCTLR_CCP15BEN Bit 5: CP15 barrier enable
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* SCTLR_B Bit 7: Should be zero on ARMv7R */
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*
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* SCTLR_SW Bit 10: SWP/SWPB not enabled (reset value)
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* SCTLR_I Bit 12: ICache disabled (reset value)
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* SCTLR_V Bit 13: Assume low vectors (reset value)
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* SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random
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* replacement strategy.
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* SCTLR_HA Bit 17: Not supported by A5
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* SCTLR_SW Bit 10: SWP/SWPB not enabled
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* SCTLR_I Bit 12: ICache disabled
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* SCTLR_V Bit 13: Assume low vectors
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* SCTLR_RR Bit 14: Round-robin replacement strategy.
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*
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* SCTLR_EE Bit 25: Little endian (reset value).
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* SCTLR_TRE Bit 28: No memory region remapping (reset value)
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* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
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* SCTLR_TE Bit 30: All exceptions handled in ARM state (reset value).
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* SCTLR_BR Bit 17: Background Region bit
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* SCTLR_DZ Bit 19: Divide by Zero fault enable bit
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* SCTLR_FI Bit 21: Fast interrupts configuration enable bit
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* SCTLR_U Bit 22: Unaligned access model (always one)
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*
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* SCTLR_VE Bit 24: Interrupt Vectors Enable bit
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* SCTLR_EE Bit 25: Little endian.
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* SCTLR_NMFI Bit 27: Non-maskable FIQ (NMFI) support
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* SCTLR_TE Bit 30: All exceptions handled in ARM state.
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* SCTLR_IE Bit 31: Instruction endian-ness.
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*/
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bic r0, r0, #(SCTLR_A | SCTLR_C)
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bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR | SCTLR_HA)
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bic r0, r0, #(SCTLR_EE | SCTLR_TRE | SCTLR_AFE | SCTLR_TE)
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/* Clear all configurable bits */
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/* Set bits to enable the MMU
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bic r0, r0, #(SCTLR_A | SCTLR_C | SCTLR_CCP15BEN | SCTLR_B)
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bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR)
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bic r0, r0, #(SCTLR_BR | SCTLR_DZ | SCTLR_FI | SCTLR_U)
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bic r0, r0, #(SCTLR_VE | SCTLR_EE | SCTLR_NMFI | SCTLR_TE | SCLTR_IE)
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/* Set configured bits */
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#ifdef CPU_ALIGNMENT_TRAP
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/* Alignment abort enable
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*
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* SCTLR_Z Bit 11: Program flow prediction control
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* SCTLR_A Bit 1: Strict alignment enabled
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*/
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orr r0, r0, #(SCTLR_Z)
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orr r0, r0, #(SCTLR_A)
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#endif
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#ifndef CPU_DCACHE_DISABLE
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/* Dcache enable
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*
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* SCTLR_C Bit 2: DCache enable
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*/
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orr r0, r0, #(SCTLR_C)
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#endif
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#define CPU_SCTLR_CCP15BEN 1
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/* Enable memory barriers
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*
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* SCTLR_CCP15BEN Bit 5: CP15 barrier enable
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*/
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orr r0, r0, #(SCTLR_CCP15BEN)
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#endif
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#ifndef CPU_ICACHE_DISABLE
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/* Icache enable
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*
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* SCTLR_I Bit 12: ICache enable
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*/
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orr r0, r0, #(SCTLR_I)
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#endif
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#ifndef CONFIG_ARCH_LOWVECTORS
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/* Position vectors to 0xffff0000 if so configured.
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@ -184,50 +229,55 @@ __start:
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#ifdef CPU_CACHE_ROUND_ROBIN
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/* Round Robin cache replacement
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*
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* SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random
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* replacement strategy.
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* SCTLR_RR Bit 14: Round-robin replacement strategy.
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*/
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orr r0, r0, #(SCTLR_RR)
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#endif
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#ifndef CPU_DCACHE_DISABLE
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/* Dcache enable
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#define CPU_BACKGROUND_REGION 1
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/* Allow PL1 access to back region when MPU is enabled
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*
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* SCTLR_C Bit 2: DCache enable
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* SCTLR_BR Bit 17: Background Region bit
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*/
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orr r0, r0, #(SCTLR_C)
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orr r0, r0, #(SCTLR_BR)
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#endif
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#ifndef CPU_ICACHE_DISABLE
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/* Icache enable
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#ifdef CPU_DIV0_FAULT
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/* Enable divide by zero faults
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*
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* SCTLR_I Bit 12: ICache enable
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* SCTLR_DZ Bit 19: Divide by Zero fault enable bit
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*/
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orr r0, r0, #(SCTLR_I)
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orr r0, r0, #(SCTLR_DZ)
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#endif
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#ifdef CPU_ALIGNMENT_TRAP
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/* Alignment abort enable
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#ifdef CPU_FAST_INTERRUPT
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/* Fast interrupts configuration enable bit
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*
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* SCTLR_A Bit 1: Strict alignment enabled
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* SCTLR_FI Bit 21: Fast interrupts configuration enable bit
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*/
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orr r0, r0, #(SCTLR_A)
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orr r0, r0, #(SCTLR_FI)
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#endif
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#ifdef CPU_AFE_ENABLE
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/* AP[0:2] Permissions model
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#ifdef CPU_IMPL_VECTORS
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/* Implementation defined interrupt vectors
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*
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* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
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*
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* When AFE=1, the page table AP[0] is used as an access flag and AP[2:1]
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* control. When AFE=0, AP[2:0] control access permissions.
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* SCTLR_VE Bit 24: Interrupt Vectors Enable bit
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*/
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orr r0, r0, #(SCTLR_AFE)
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orr r0, r0, #(SCTLR_VE)
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#endif
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#ifdef CPU_NONMASKABLE_FIQ
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/* Non-maskable FIQ support
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*
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* SCTLR_NMFI Bit 27: Non-maskable FIQ (NMFI) support
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*/
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orr r0, r0, #(SCTLR_NMFI)
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#endif
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/* Then write the configured control register */
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@ -74,8 +74,8 @@
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*
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* Description:
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* Shouldn't happen. This exception handler is in a separate file from
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* other vector handlers because some processors (e.g., Cortex-A5) do not
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* support the Address Exception vector.
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* other vector handlers because some processors do not support the
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* Address Exception vector.
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*
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****************************************************************************/
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@ -7,9 +7,7 @@
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*
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* References:
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*
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* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1, Copyright © 2010
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* ARM. All rights reserved. ARM DDI 0434B (ID101810)
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* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright ©
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* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright
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* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.b (ID072512)
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*
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* Redistribution and use in source and binary forms, with or without
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@ -51,172 +49,317 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Reference: Cortex-A5™ MPCore Paragraph 4.2, "Register summary." */
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/* CP15 c0 Registers ****************************************************************/
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/* Main ID Register (MIDR) */
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/* TODO: To be provided */
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/* Cache Type Register (CTR) */
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/* TODO: To be provided */
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/* TCM Type Register
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*
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* The Cortex-A5 MPCore processor does not implement instruction or data Tightly
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* Coupled Memory (TCM), so this register always Reads-As-Zero (RAZ).
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*
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* TLB Type Register
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*
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* The Cortex-A5 MPCore processor does not implement instruction or data Tightly
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* CoupledMemory (TCM), so this register always Reads-As-Zero (RAZ).
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/* Main ID Register (MIDR): CRn=c0, opc1=0, CRm=c0, opc2=0
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* TODO: To be provided
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*/
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/* Multiprocessor Affinity Register (MPIDR) */
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/* TODO: To be provided */
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/* Cache Type Register (CTR): CRn=c0, opc1=0, CRm=c0, opc2=1
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* TODO: To be provided
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*/
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/* Processor Feature Register 0 (ID_PFR0) */
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/* TODO: To be provided */
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/* TCM Type Register (TCMTR): CRn=c0, opc1=0, CRm=c0, opc2=2
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* Details implementation defined.
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*/
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/* Processor Feature Register 1 (ID_PFR1) */
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/* TODO: To be provided */
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/* Aliases of Main ID register (MIDR): CRn=c0, opc1=0, CRm=c0, opc2=3,7
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* TODO: To be provided
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*/
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/* Debug Feature Register 0 (ID_DFR0) */
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/* TODO: To be provided */
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/* MPU Type Register (MPUIR): CRn=c0, opc1=0, CRm=c0, opc2=4
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* TODO: To be provided
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*/
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/* Auxiliary Feature Register 0 (ID_AFR0) */
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/* TODO: To be provided */
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/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5
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* TODO: To be provided
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*/
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/* Memory Model Features Register 0 (ID_MMFR0) */
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/* Memory Model Features Register 1 (ID_MMFR1) */
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/* Memory Model Features Register 2 (ID_MMFR2) */
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/* Memory Model Features Register 3 (ID_MMFR3) */
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/* TODO: To be provided */
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/* Revision ID Register (REVIDR): CRn=c0, opc1=0, CRm=c0, opc2=6
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* TODO: To be provided
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*/
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/* Instruction Set Attributes Register 0 (ID_ISAR0) */
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/* Instruction Set Attributes Register 1 (ID_ISAR1) */
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/* Instruction Set Attributes Register 2 (ID_ISAR2) */
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/* Instruction Set Attributes Register 3 (ID_ISAR3) */
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/* Instruction Set Attributes Register 4 (ID_ISAR4) */
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/* Instruction Set Attributes Register 5 (ID_ISAR5) */
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/* Instruction Set Attributes Register 6-7 (ID_ISAR6-7). Reserved. */
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/* TODO: Others to be provided */
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/* Processor Feature Register 0 (ID_PFR0): CRn=c0, opc1=0, CRm=c1, opc2=0
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* Processor Feature Register 1 (ID_PFR1): CRn=c0, opc1=0, CRm=c1, opc2=1
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* TODO: To be provided
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*/
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/* Cache Size Identification Register (CCSIDR) */
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/* TODO: To be provided */
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/* Debug Feature Register 0 (ID_DFR0): CRn=c0, opc1=0, CRm=c1, opc2=2
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* TODO: To be provided
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*/
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/* Cache Level ID Register (CLIDR) */
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/* TODO: To be provided */
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/* Auxiliary Feature Register 0 (ID_AFR0): CRn=c0, opc1=0, CRm=c1, opc2=3
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* TODO: To be provided
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*/
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/* Auxiliary ID Register (AIDR) */
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/* TODO: To be provided */
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/* Memory Model Features Register 0 (ID_MMFR0): CRn=c0, opc1=0, CRm=c1, opc2=4
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* Memory Model Features Register 1 (ID_MMFR1): CRn=c0, opc1=0, CRm=c1, opc2=5
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* Memory Model Features Register 2 (ID_MMFR2): CRn=c0, opc1=0, CRm=c1, opc2=6
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* Memory Model Features Register 3 (ID_MMFR3): CRn=c0, opc1=0, CRm=c1, opc2=7
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* TODO: To be provided
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*/
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/* Cache Size Selection Register (CSSELR) */
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/* TODO: To be provided */
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/* Instruction Set Attributes Register 0 (ID_ISAR0): CRn=c0, opc1=0, CRm=c2, opc2=0
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* Instruction Set Attributes Register 1 (ID_ISAR1): CRn=c0, opc1=0, CRm=c2, opc2=1
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* Instruction Set Attributes Register 2 (ID_ISAR2): CRn=c0, opc1=0, CRm=c2, opc2=2
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* Instruction Set Attributes Register 3 (ID_ISAR3): CRn=c0, opc1=0, CRm=c2, opc2=3
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* Instruction Set Attributes Register 4 (ID_ISAR4): CRn=c0, opc1=0, CRm=c2, opc2=4
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* Instruction Set Attributes Register 5 (ID_ISAR5): CRn=c0, opc1=0, CRm=c2, opc2=5
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* Instruction Set Attributes Register 6-7 (ID_ISAR6-7). Reserved.
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* TODO: Others to be provided
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*/
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/* System Control Register (SCTLR)
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*
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* NOTES:
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* (1) Always enabled on A5
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* (2) Not available on A5
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/* Reserved: CRn=c0, opc1=0, CRm=c3-c7, opc2=* */
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/* Cache Size Identification Register (CCSIDR): CRn=c0, opc1=1, CRm=c0, opc2=0
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* TODO: To be provided
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*/
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/* Cache Level ID Register (CLIDR): CRn=c0, opc1=1, CRm=c0, opc2=1
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* TODO: To be provided
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*/
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/* Auxiliary ID Register (AIDR): CRn=c0, opc1=1, CRm=c0, opc2=7
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* TODO: To be provided
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*/
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/* Cache Size Selection Register (CSSELR): CRn=c0, opc1=2, CRm=c0, opc2=0
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* TODO: To be provided
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*/
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/* CP15 c1 Registers ****************************************************************/
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/* System Control Register (SCTLR): CRn=c1, opc1=0, CRm=c0, opc2=0
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*/
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#define SCTLR_A (1 << 1) /* Bit 1: Enables strict alignment of data */
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#define SCTLR_C (1 << 2) /* Bit 2: Determines if data can be cached */
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/* Bits 3-9: Reserved */
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/* Bits 3-4: Reserved */
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#define SCTLR_CCP15BEN (1 << 5) /* Bit 5: CP15 barrier enable */
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/* Bit 6: Reserved */
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#define SCTLR_B (1 << 7) /* Bit 7: Should be zero on ARMv7R */
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/* Bits 8-9: Reserved */
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#define SCTLR_SW (1 << 10) /* Bit 10: SWP/SWPB Enable bit */
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#define SCTLR_Z (1 << 11) /* Bit 11: Program flow prediction control (1) */
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#define SCTLR_Z (1 << 11) /* Bit 11: Program flow prediction control */
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#define SCTLR_I (1 << 12) /* Bit 12: Determines if instructions can be cached */
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#define SCTLR_V (1 << 13) /* Bit 13: Vectors bit */
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#define SCTLR_RR (1 << 14) /* Bit 14: Cache replacement strategy (2) */
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#define SCTLR_RR (1 << 14) /* Bit 14: Cache replacement strategy */
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/* Bits 15-16: Reserved */
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#define SCTLR_HA (1 << 17) /* Bit 17: Hardware management access disabled (2) */
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/* Bits 18-24: Reserved */
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#define SCTLR_BR (1 << 17) /* Bit 17: Background Region bit */
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/* Bit 18: Reserved */
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#define SCTLR_DZ (1 << 19) /* Bit 19: Divide by Zero fault enable bit */
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/* Bit 20: Reserved */
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#define SCTLR_FI (1 << 21) /* Bit 21: Fast interrupts configuration enable bit */
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#define SCTLR_U (1 << 22) /* Bit 22: Unaligned access model (always one) */
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#define SCTLR_VE (1 << 24) /* Bit 24: Interrupt Vectors Enable bit */
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#define SCTLR_EE (1 << 25) /* Bit 25: Determines the value the CPSR.E */
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/* Bits 26-27: Reserved */
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#define SCTLR_TRE (1 << 28) /* Bit 28: TEX remap */
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#define SCTLR_AFE (1 << 29) /* Bit 29: Access Flag Enable bit */
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#define SCTLR_NMFI (1 << 27) /* Bit 27: Non-maskable FIQ (NMFI) support */
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/* Bits 28-29: Reserved */
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#define SCTLR_TE (1 << 30) /* Bit 30: Thumb exception enable */
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/* Bit 31: Reserved */
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#define SCTLR_IE (1 << 31) /* Bit 31: Instruction endian-ness */
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/* Auxiliary Control Register (ACTLR) */
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/* TODO: To be provided */
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/* Auxiliary Control Register (ACTLR): CRn=c1, opc1=0, CRm=c0, opc2=1
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* TODO: To be provided
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*/
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/* Coprocessor Access Control Register (CPACR) */
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/* TODO: To be provided */
|
||||
/* Coprocessor Access Control Register (CPACR): CRn=c1, opc1=0, CRm=c0, opc2=2
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Secure Configuration Register (SCR) */
|
||||
/* TODO: To be provided */
|
||||
/* CP15 c2-c4 Registers *************************************************************/
|
||||
/* Not used on ARMv7R */
|
||||
|
||||
/* Secure Debug Enable Register (SDER) */
|
||||
/* TODO: To be provided */
|
||||
/* CP15 c5 Registers ****************************************************************/
|
||||
/* Data Fault Status Register (DFSR): CRn=c5, opc1=0, CRm=c0, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Non-secure Access Control Register (NSACR) */
|
||||
/* Instruction Fault Status Register (IFSR): CRn=c5, opc1=0, CRm=c0, opc2=1
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Bits 0-9: Reserved */
|
||||
#define NSACR_CP10 (1 << 10) /* Bit 10: Permission to access coprocessor 10 */
|
||||
#define NSACR_CP11 (1 << 11) /* Bit 11: Permission to access coprocessor 11 */
|
||||
/* Bits 12-13: Reserved */
|
||||
#define NSACR_NSD32DIS (1 << 14) /* Bit 14: Disable the Non-secure use of VFP D16-D31 */
|
||||
#define NSACR_NSASEDIS (1 << 15) /* Bit 15: Disable Non-secure Advanced SIMD Extension */
|
||||
/* Bits 16-17: Reserved */
|
||||
#define NSACR_NSSMP (1 << 18) /* Bit 18: ACR SMP bit writable */
|
||||
/* Bits 19-31: Reserved */
|
||||
/* Auxiliary DFSR (ADFSR): CRn=c5, opc1=0, CRm=c1, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Virtualization Control Register (VCR) */
|
||||
/* TODO: To be provided */
|
||||
/* Auxiliary IFSR (AIFSR): CRn=c5, opc1=0, CRm=c1, opc2=1
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Auxiliary Data Fault Status Register (ADFSR). Not used in this implementation. */
|
||||
/* CP15 c6 Registers ****************************************************************/
|
||||
|
||||
/* Data Fault Address Register(DFAR)
|
||||
/* Data Fault Address Register(DFAR): CRn=c6, opc1=0, CRm=c0, opc2=0
|
||||
*
|
||||
* Holds the MVA of the faulting address when a synchronous fault occurs
|
||||
*
|
||||
* Instruction Fault Address Register(IFAR)
|
||||
*/
|
||||
|
||||
/* Instruction Fault Address Register(IFAR): CRn=c6, opc1=0, CRm=c0, opc2=1
|
||||
*
|
||||
* Holds the MVA of the faulting address of the instruction that caused a prefetch
|
||||
* abort.
|
||||
*
|
||||
* NOP Register
|
||||
*
|
||||
* The use of this register is optional and deprecated. Use the NOP instruction
|
||||
* instead.
|
||||
*
|
||||
* Physical Address Register (PAR)
|
||||
*
|
||||
* Holds:
|
||||
* - the PA after a successful translation
|
||||
* - the source of the abort for an unsuccessful translation
|
||||
*
|
||||
* Instruction Synchronization Barrier
|
||||
*
|
||||
* The use of ISB is optional and deprecated. Use the instruction ISB instead.
|
||||
*
|
||||
* Data Memory Barrier
|
||||
* The use of DMB is deprecated and, on Cortex-A5 MPCore, behaves as NOP. Use the
|
||||
* instruction DMB instead.
|
||||
*/
|
||||
|
||||
/* Vector Base Address Register (VBAR) */
|
||||
/* Data Region Base Address Register (DRBAR): CRn=c6, opc1=0, CRm=c1, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
#define VBAR_MASK (0xffffffe0)
|
||||
/* Instruction Region Base Address Register (IRBAR): CRn=c6, opc1=0, CRm=c1, opc2=1
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Monitor Vector Base Address Register (MVBAR) */
|
||||
/* TODO: To be provided */
|
||||
/* Data Region Size and Enable Register (DRSR): CRn=c6, opc1=0, CRm=c1, opc2=2
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Interrupt Status Register (ISR) */
|
||||
/* TODO: To be provided */
|
||||
/* Instruction Region Size and Enable Register (IRSR): CRn=c6, opc1=0, CRm=c1, opc2=3
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Virtualization Interrupt Register (VIR) */
|
||||
/* TODO: To be provided */
|
||||
/* Data Region Access Control Register (DRACR): CRn=c6, opc1=0, CRm=c1, opc2=4
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Context ID Register (CONTEXTIDR) */
|
||||
/* Instruction Region Access Control Register (IRACR): CRn=c6, opc1=0, CRm=c1, opc2=5
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
#define CONTEXTIDR_ASID_SHIFT (0) /* Bits 0-7: Address Space Identifier */
|
||||
#define CONTEXTIDR_ASID_MASK (0xff << CONTEXTIDR_ASID_SHIFT)
|
||||
#define CONTEXTIDR_PROCID_SHIFT (8) /* Bits 8-31: Process Identifier */
|
||||
#define CONTEXTIDR_PROCID_MASK (0x00ffffff << CONTEXTIDR_PROCID_SHIFT)
|
||||
/* MPU Region Number Register (RGNR): CRn=c6, opc1=0, CRm=c2, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Configuration Base Address Register (CBAR) */
|
||||
/* TODO: To be provided */
|
||||
/* CP15 c7 Registers ****************************************************************/
|
||||
/* See cp15_cacheops.h */
|
||||
|
||||
/* CP15 c8 Registers ****************************************************************/
|
||||
/* Not used on ARMv7R */
|
||||
|
||||
/* CP15 c9 Registers ****************************************************************/
|
||||
/* 32-bit Performance Monitors Control Register (PMCR): CRn=c9, opc1=0, CRm=c0, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Count Enable Set register (PMCNTENSET): CRn=c9, opc1=0, CRm=c12, opc2=1
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Count Enable Clear register (PMCNTENCLR): CRn=c9, opc1=0, CRm=c12, opc2=2
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Overflow Flag Status Register (PMOVSR): CRn=c9, opc1=0, CRm=c12, opc2=3
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Software Increment register (PMSWINC): CRn=c9, opc1=0, CRm=c12, opc2=4
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Event Counter Selection Register (PMSELR): CRn=c9, opc1=0, CRm=c12, opc2=5
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Common Event Identification (PMCEID0): CRn=c9, opc1=0, CRm=c12, opc2=6
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Common Event Identification (PMCEID1): CRn=c9, opc1=0, CRm=c12, opc2=7
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Cycle Count Register (PMCCNTR): CRn=c9, opc1=0, CRm=c13, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Event Type Select Register (PMXEVTYPER): CRn=c9, opc1=0, CRm=c13, opc2=1
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Event Count Register (PMXEVCNTR): CRn=c9, opc1=0, CRm=c13, opc2=2
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors User Enable Register (PMUSERENR): CRn=c9, opc1=0, CRm=c14, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Interrupt Enable Set register (PMINTENSET): CRn=c9, opc1=0, CRm=c14, opc2=1
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 32-bit Performance Monitors Interrupt Enable Clear register (PMINTENCLR): CRn=c9, opc1=0, CRm=c14, opc2=2
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* CP15 c10 Registers ***************************************************************/
|
||||
/* Not used on ARMv7R */
|
||||
|
||||
/* CP15 c11 Registers ***************************************************************/
|
||||
/* Reserved for implementation defined DMA functions */
|
||||
|
||||
/* CP15 c12 Registers ***************************************************************/
|
||||
/* Not used on ARMv7R */
|
||||
|
||||
/* CP15 c13 Registers ***************************************************************/
|
||||
|
||||
/* Context ID Register (CONTEXTIDR): CRn=c13, opc1=0, CRm=c0, opc2=1
|
||||
* 32-Bit ContextID value.
|
||||
*/
|
||||
|
||||
/* User Read/Write (TPIDRURW): CRn=c13, opc1=0, CRm=c0, opc2=2
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* User Read Only (TPIDRURO): CRn=c13, opc1=0, CRm=c0, opc2=3
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* PL1 only (TPIDRPRW): CRn=c13, opc1=0, CRm=c0, opc2=4
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* CP15 c14 Registers ***************************************************************/
|
||||
|
||||
/* Counter Frequency register (CNTFRQ): CRn=c14, opc1=0, CRm=c0, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Timer PL1 Control register (CNTKCTL): CRn=c14, opc1=0, CRm=c1, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* PL1 Physical TimerValue register (CNTP_TVAL): CRn=c14, opc1=0, CRm=c2, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* PL1 Physical Timer Control register (CNTP_CTL): CRn=c14, opc1=0, CRm=c2, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Virtual TimerValue register (CNTV_TVAL): CRn=c14, opc1=0, CRm=c3, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Virtual Timer Control register (CNTV_CTL): CRn=c14, opc1=0, CRm=c3, opc2=0
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* 64-bit Physical Count register (CNTPCT): CRn=c14, opc1=0, CRm=c14, opc2=n
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Virtual Count register (CNTVCT): CRn=c14, opc1=1, CRm=c14, opc2=n
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* PL1 Physical Timer CompareValue register (CNTP_CVAL): CRn=c14, opc1=2, CRm=c14, opc2=n
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* Virtual Timer CompareValue register (CNTV_CVAL): CRn=c14, opc1=3, CRm=c14, opc2=n
|
||||
* TODO: To be provided
|
||||
*/
|
||||
|
||||
/* CP15 c15 Registers ***************************************************************/
|
||||
/* Implementation defined */
|
||||
|
||||
/************************************************************************************
|
||||
* Assemby Macros
|
||||
|
||||
@ -72,7 +72,7 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Cortex M3 system calls ***********************************************************/
|
||||
/* Cortex-R system calls ************************************************************/
|
||||
|
||||
/* SYS call 0:
|
||||
*
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user