SAMD21: Update GCLKs for SAMD21
This commit is contained in:
Gregory Nutt
parent
9fc91cfa5a
commit
ba1f9e2272
@ -1,12 +1,14 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/samd_gclk.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
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* Datasheet", 42129J–SAM–12/2013
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* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
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* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -48,7 +50,7 @@
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
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/********************************************************************************************
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* Pre-processor Definitions
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@ -84,6 +86,8 @@
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#define GCLK_CLKCTRL_ID_SHIFT (0) /* Bits 0-5: Generic Clock Selection ID */
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#define GCLK_CLKCTRL_ID_MASK (0x3f << GCLK_CLKCTRL_ID_SHIFT)
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# define GCLK_CLKCTRL_ID(n) ((n) << GCLK_CLKCTRL_ID_SHIFT)
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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# define GCLK_CLKCTRL_ID_DFLL48M (0 << GCLK_CLKCTRL_ID_SHIFT) /* DFLL48M Reference */
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# define GCLK_CLKCTRL_ID_WDT (1 << GCLK_CLKCTRL_ID_SHIFT) /* WDT */
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# define GCLK_CLKCTRL_ID_RTC (2 << GCLK_CLKCTRL_ID_SHIFT) /* RTC */
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@ -114,6 +118,49 @@
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# define GCLK_CLKCTRL_ID_ACANA (25 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
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# define GCLK_CLKCTRL_ID_DAC (26 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
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# define GCLK_CLKCTRL_ID_PTC (27 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
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#endif
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define GCLK_CLKCTRL_ID_DFLL48M (0 << GCLK_CLKCTRL_ID_SHIFT) /* DFLL48M Reference */
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# define GCLK_CLKCTRL_ID_DPLL (1 << GCLK_CLKCTRL_ID_SHIFT) /* FDPLL96M input clock source for reference */
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# define GCLK_CLKCTRL_ID_DPLL32K (2 << GCLK_CLKCTRL_ID_SHIFT) /* FDPLL96M 32kHz clock for FDPLL96M internal lock timer */
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# define GCLK_CLKCTRL_ID_WDT (3 << GCLK_CLKCTRL_ID_SHIFT) /* WDT */
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# define GCLK_CLKCTRL_ID_RTC (4 << GCLK_CLKCTRL_ID_SHIFT) /* RTC */
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# define GCLK_CLKCTRL_ID_EIC (5 << GCLK_CLKCTRL_ID_SHIFT) /* EIC */
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# define GCLK_CLKCTRL_ID_EVSYS(n) (((n)+7) << GCLK_CLKCTRL_ID_SHIFT)
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# define GCLK_CLKCTRL_ID_EVSYS0 (7 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_0 */
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# define GCLK_CLKCTRL_ID_EVSYS1 (8 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_1 */
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# define GCLK_CLKCTRL_ID_EVSYS2 (9 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_2 */
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# define GCLK_CLKCTRL_ID_EVSYS3 (10 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_3 */
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# define GCLK_CLKCTRL_ID_EVSYS4 (11 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_4 */
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# define GCLK_CLKCTRL_ID_EVSYS5 (12 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_5 */
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# define GCLK_CLKCTRL_ID_EVSYS6 (13 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_6 */
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# define GCLK_CLKCTRL_ID_EVSYS7 (14 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_7 */
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# define GCLK_CLKCTRL_ID_EVSYS8 (15 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_8 */
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# define GCLK_CLKCTRL_ID_EVSYS9 (16 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_9 */
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# define GCLK_CLKCTRL_ID_EVSYS10 (17 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_10 */
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# define GCLK_CLKCTRL_ID_EVSYS11 (18 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_11 */
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# define GCLK_CLKCTRL_ID_SERCOMS (19 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOMx_SLOW */
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# define GCLK_CLKCTRL_ID_SERCOMC(n) (((n)+20) << GCLK_CLKCTRL_ID_SHIFT)
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# define GCLK_CLKCTRL_ID_SERCOM0C (20 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM0_CORE */
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# define GCLK_CLKCTRL_ID_SERCOM1C (21 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM1_CORE */
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# define GCLK_CLKCTRL_ID_SERCOM2C (22 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM2_CORE */
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# define GCLK_CLKCTRL_ID_SERCOM3C (23 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM3_CORE */
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# define GCLK_CLKCTRL_ID_SERCOM4C (24 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM4_CORE */
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# define GCLK_CLKCTRL_ID_SERCOM5C (25 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM5_CORE */
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# define GCLK_CLKCTRL_ID_TCC01 (26 << GCLK_CLKCTRL_ID_SHIFT) /* TCC0,TCC1 */
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# define GCLK_CLKCTRL_ID_TCC23 (27 << GCLK_CLKCTRL_ID_SHIFT) /* TCC2,TC3 */
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# define GCLK_CLKCTRL_ID_TC45 (28 << GCLK_CLKCTRL_ID_SHIFT) /* TC4,TC5 */
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# define GCLK_CLKCTRL_ID_TC67 (29 << GCLK_CLKCTRL_ID_SHIFT) /* TC6,TC7 */
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# define GCLK_CLKCTRL_ID_ADC (30 << GCLK_CLKCTRL_ID_SHIFT) /* ADC */
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# define GCLK_CLKCTRL_ID_ACDIG (31 << GCLK_CLKCTRL_ID_SHIFT) /* AC_DIG */
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# define GCLK_CLKCTRL_ID_ACANA (32 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
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# define GCLK_CLKCTRL_ID_DAC (33 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
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# define GCLK_CLKCTRL_ID_PTC (34 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
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# define GCLK_CLKCTRL_I2S0_PTC (35 << GCLK_CLKCTRL_ID_SHIFT) /* I2S0 */
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# define GCLK_CLKCTRL_I2S1_PTC (36 << GCLK_CLKCTRL_ID_SHIFT) /* I2S1 */
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#endif
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#define GCLK_CLKCTRL_GEN_SHIFT (8) /* Bits 8-11: Generic Clock Generator */
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#define GCLK_CLKCTRL_GEN_MASK (15 << GCLK_CLKCTRL_GEN_SHIFT)
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# define GCLK_CLKCTRL_GEN(n) ((n) << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator n */
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@ -125,6 +172,11 @@
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# define GCLK_CLKCTRL_GEN5 (5 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 5 */
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# define GCLK_CLKCTRL_GEN6 (6 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 6 */
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# define GCLK_CLKCTRL_GEN7 (7 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 7 */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define GCLK_CLKCTRL_GEN8 (8 << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator 8 */
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#endif
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#define GCLK_CLKCTRL_CLKEN (1 << 14) /* Bit 14: Clock Enable */
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#define GCLK_CLKCTRL_WRTLOCK (1 << 15) /* Bit 15: Write Lock */
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@ -141,6 +193,11 @@
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# define GCLK_GENCTRL_ID5 (5 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 5 */
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# define GCLK_GENCTRL_ID6 (6 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 6 */
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# define GCLK_GENCTRL_ID7 (7 << GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 7 */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define GCLK_GENCTRL_ID8 (78<< GCLK_GENCTRL_ID_SHIFT) /* Generic clock generator 8 */
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#endif
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#define GCLK_GENCTRL_SRC_SHIFT (8) /* Bits 8-12: Source Select */
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#define GCLK_GENCTRL_SRC_MASK (31 << GCLK_GENCTRL_SRC_SHIFT)
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# define GCLK_GENCTRL_SRC_XOSC (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC oscillator output */
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@ -187,5 +244,5 @@
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_GCLK_H */
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@ -7,6 +7,8 @@
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* References:
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* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
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* Datasheet", 42129J–SAM–12/2013
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* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
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* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -1,13 +1,15 @@
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/****************************************************************************
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* arch/arm/src/samdl/samd_clockconfig.c
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
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* Datasheet", 42129J–SAM–12/2013
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* 2. Atmel sample code for the SAMD20. This code has an ASF license
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* 2. "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
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* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
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* 3. Atmel sample code for the SAMD20. This code has an ASF license
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* with is compatible with the NuttX BSD license, but includes the
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* provision that this code not be used in non-Atmel products. That
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* sample code was used only as a reference so I believe that only the
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@ -66,7 +68,7 @@
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#include "samd_periphclks.h"
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#include "sam_clockconfig.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
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/****************************************************************************
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* Pre-processor Definitions
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@ -216,6 +218,23 @@ static const struct sam_gclkconfig_s g_gclkconfig[] =
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.clksrc = (uint8_t)(BOARD_GCLK7_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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/* GCLK generator 8 */
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#ifdef BOARD_GCLK8_ENABLE
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,
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{
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.gclk = 8,
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#ifdef BOARD_GCLK8_RUN_IN_STANDBY
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.runstandby = true;
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#endif
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#ifdef BOARD_GCLK8_OUTPUT_ENABLE
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.output = true;
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#endif
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.prescaler = BOARD_GCLK8_PRESCALER,
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.clksrc = (uint8_t)(BOARD_GCLK8_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT),
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}
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#endif
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};
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#define NGCLKS_ENABLED (sizeof(g_gclkconfig) / sizeof(struct sam_gclkconfig_s))
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@ -869,4 +888,4 @@ void sam_clockconfig(void)
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sam_dividers();
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}
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21*/
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