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Merge remote-tracking branch 'origin/master' into mcan

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This commit is contained in:
Gregory Nutt 2015-08-05 08:57:29 -06:00
commit ba23314cbf
6 changed files with 89 additions and 10 deletions
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9
arch/arm/include/samv7/samv71_irq.h
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@ -278,7 +278,8 @@
#endif
#ifdef CONFIG_SAMV7_GPIOC_IRQ
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
SAM_NGPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
@ -317,7 +318,8 @@
#endif
#ifdef CONFIG_SAMV7_GPIOD_IRQ
# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)
# define SAM_IRQ_PD0 (SAM_IRQ_GPIOD_PINS+0) /* GPIOD, PIN 0 */
# define SAM_IRQ_PD1 (SAM_IRQ_GPIOD_PINS+1) /* GPIOD, PIN 1 */
# define SAM_IRQ_PD2 (SAM_IRQ_GPIOD_PINS+2) /* GPIOD, PIN 2 */
@ -356,7 +358,8 @@
#endif
#ifdef CONFIG_SAMV7_GPIOE_IRQ
# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + SAM_NGPIODIRQS)
# define SAM_IRQ_PE0 (SAM_IRQ_GPIOE_PINS+0) /* GPIOE, PIN 0 */
# define SAM_IRQ_PE1 (SAM_IRQ_GPIOE_PINS+1) /* GPIOE, PIN 1 */
# define SAM_IRQ_PE2 (SAM_IRQ_GPIOE_PINS+2) /* GPIOE, PIN 2 */

3
arch/arm/src/moxart/Kconfig
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@ -4,3 +4,6 @@
#
comment "MoxART Configuration Options"
config UART_MOXA_MODE_REG
hex "16550 UART mode register address"

71
arch/arm/src/moxart/moxart_16550.c
View File

@ -40,11 +40,15 @@
#include <nuttx/config.h>
#include <errno.h>
#include <stdio.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include <nuttx/serial/serial.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/serial/uart_16550.h>
#include <nuttx/serial/mxser.h>
#include "arm.h"
#include "up_arch.h"
@ -62,3 +66,70 @@ void uart_putreg(uart_addrwidth_t base, unsigned int offset, uart_datawidth_t va
{
*((volatile uart_addrwidth_t *)base + offset) = value;
}
#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL
int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
{
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
struct u16550_s *priv = (struct u16550_s*)dev->priv;
int ret = -ENOTTY;
uint32_t vmode;
unsigned int opmode;
int bitm_off;
/*
* TODO: calculate bit offset from UART_BASE address.
* E.g.:
* 0x9820_0000 -> 0
* 0x9820_0020 -> 1
* 0x9820_0040 -> 2
*/
/* HARD: coded value for UART1 */
bitm_off = 1;
switch (cmd)
{
case MOXA_SET_OP_MODE:
{
irqstate_t flags;
opmode = *(unsigned long *)arg;
/* Check for input data */
if (opmode & ~OP_MODE_MASK)
{
ret = -EINVAL;
break;
}
flags = irqsave();
/* Update mode register with requested mode */
vmode = getreg32(CONFIG_UART_MOXA_MODE_REG);
putreg32(CONFIG_UART_MOXA_MODE_REG, (vmode & ~(OP_MODE_MASK << 2 * bitm_off)) | ((opmode << 2 * bitm_off) & 0xffff));
irqrestore(flags);
break;
}
case MOXA_GET_OP_MODE:
{
irqstate_t flags;
flags = irqsave();
/* Read from mode register */
opmode = (getreg32(CONFIG_UART_MOXA_MODE_REG) >> 2 * bitm_off) & OP_MODE_MASK;
irqrestore(flags);
*(unsigned long *)arg = opmode;
break;
}
}
return ret;
}
#endif

2
arch/arm/src/sama5/sam_can.c
View File

@ -1183,7 +1183,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
regval = CAN_MCR_MDLC(msg->cm_hdr.ch_dlc) | CAN_MCR_MTCR;
can_putreg(priv, SAM_CAN_MnCR_OFFSET(mbndx), regval);
/* If we have not been asked to suppress TX interrupts, then dnable
/* If we have not been asked to suppress TX interrupts, then enable
* interrupts from this mailbox now.
*/

2
arch/arm/src/stm32/Kconfig
View File

@ -3114,7 +3114,7 @@ config STM32_TIM14_DAC2
endchoice
menu "ADC Configuration"
depends on STM32_ADC1
depends on STM32_ADC
config STM32_ADC1_DMA
bool "ADC1 DMA"

12
arch/arm/src/stm32/stm32_adc.c
View File

@ -1596,7 +1596,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_NODMA);
}
regval |= (((uint32_t)priv->nchannels-1) << ADC_SQR1_L_SHIFT);
regval |= (((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT);
adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
/* Set the channel index of the first conversion */
@ -2284,6 +2284,7 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
}
#else
priv->nchannels = priv->cchannels;
regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED;
for (i = 0, offset = 0; i < priv->nchannels && i < 6; i++, offset += 5)
{
@ -2320,10 +2321,11 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
break;
}
regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED;
regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED;
regval &= ~(ADC_SQR1_L_MASK);
adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval);
priv->current = i;
priv->current = i;
priv->nchannels = 1;
return ret;
}
@ -2761,7 +2763,7 @@ void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev,
* Input Parameters:
* intf - Could be {1,2,3} for ADC1, ADC2, or ADC3
* chanlist - The list of channels
* nchannels - Number of channels
* cchannels - Number of channels
*
* Returned Value:
* Valid ADC device structure reference on succcess; a NULL on failure
@ -2774,7 +2776,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
FAR struct adc_dev_s *dev;
FAR struct stm32_dev_s *priv;
allvdbg("intf: %d nchannels: %d\n", intf, cchannels);
allvdbg("intf: %d cchannels: %d\n", intf, cchannels);
#ifdef CONFIG_STM32_ADC1
if (intf == 1)