SAMV7: Add RTC register definition header file
This commit is contained in:
Gregory Nutt
parent
d14e08a187
commit
ba55e8c7d8
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/****************************************************************************************
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* arch/arm/src/samat/chip/sam_rtc.h
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* arch/arm/src/sama5d/chip/sam_rtc.h
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* Real-time Clock (RTC) definitions for the SAMA5D3
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*
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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270
arch/arm/src/samv7/chip/sam_rtc.h
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270
arch/arm/src/samv7/chip/sam_rtc.h
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/****************************************************************************************
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* arch/arm/src/samv7/chip/sam_rtc.h
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* Real-time Clock (RTC) definitions for the SAMV71
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RTC_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RTC_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* RTC register offsets *****************************************************************/
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#define SAM_RTC_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_RTC_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_RTC_TIMR_OFFSET 0x0008 /* Time Register */
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#define SAM_RTC_CALR_OFFSET 0x000c /* Calendar Register */
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#define SAM_RTC_TIMALR_OFFSET 0x0010 /* Time Alarm Register */
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#define SAM_RTC_CALALR_OFFSET 0x0014 /* Calendar Alarm Register */
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#define SAM_RTC_SR_OFFSET 0x0018 /* Status Register */
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#define SAM_RTC_SCCR_OFFSET 0x001c /* Status Clear Command Register */
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#define SAM_RTC_IER_OFFSET 0x0020 /* Interrupt Enable Register */
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#define SAM_RTC_IDR_OFFSET 0x0024 /* Interrupt Disable Register */
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#define SAM_RTC_IMR_OFFSET 0x0028 /* Interrupt Mask Register */
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#define SAM_RTC_VER_OFFSET 0x002c /* Valid Entry Register */
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/* RTC register addresses ***************************************************************/
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#define SAM_RTC_CR (SAM_RTCC_VBASE+SAM_RTC_CR_OFFSET)
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#define SAM_RTC_MR (SAM_RTCC_VBASE+SAM_RTC_MR_OFFSET)
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#define SAM_RTC_TIMR (SAM_RTCC_VBASE+SAM_RTC_TIMR_OFFSET)
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#define SAM_RTC_CALR (SAM_RTCC_VBASE+SAM_RTC_CALR_OFFSET)
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#define SAM_RTC_TIMALR (SAM_RTCC_VBASE+SAM_RTC_TIMALR_OFFSET)
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#define SAM_RTC_CALALR (SAM_RTCC_VBASE+SAM_RTC_CALALR_OFFSET)
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#define SAM_RTC_SR (SAM_RTCC_VBASE+SAM_RTC_SR_OFFSET)
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#define SAM_RTC_SCCR (SAM_RTCC_VBASE+SAM_RTC_SCCR_OFFSET)
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#define SAM_RTC_IER (SAM_RTCC_VBASE+SAM_RTC_IER_OFFSET)
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#define SAM_RTC_IDR (SAM_RTCC_VBASE+SAM_RTC_IDR_OFFSET)
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#define SAM_RTC_IMR (SAM_RTCC_VBASE+SAM_RTC_IMR_OFFSET)
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#define SAM_RTC_VER (SAM_RTCC_VBASE+SAM_RTC_VER_OFFSET)
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/* RTC register bit definitions *********************************************************/
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/* RTC Control Register */
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#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */
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#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */
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#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */
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#define RTC_CR_TIMEVSEL_MASK (3 << RTC_CR_TIMEVSEL_SHIFT)
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# define RTC_CR_TIMEVSEL_MIN (0 << RTC_CR_TIMEVSEL_SHIFT)
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# define RTC_CR_TIMEVSEL_HOUR (1 << RTC_CR_TIMEVSEL_SHIFT)
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# define RTC_CR_TIMEVSEL_MIDNIGHT (2 << RTC_CR_TIMEVSEL_SHIFT)
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# define RTC_CR_TIMEVSEL_NOON (3 << RTC_CR_TIMEVSEL_SHIFT)
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#define RTC_CR_CALEVSEL_SHIFT (16) /* Bits 16-17: Calendar Event Selection */
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#define RTC_CR_CALEVSEL_MASK (3 << RTC_CR_CALEVSEL_SHIFT)
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# define RTC_CR_CALEVSEL_WEEK (0 << RTC_CR_CALEVSEL_SHIFT)
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# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT)
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# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT)
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/* RTC Mode Register */
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#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */
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#define RTC_MR_PERSIAN (1 << 1) /* Bit 1: PERSIAN Calendar */
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#define RTC_MR_NEGPPM (1 << 4) /* Bit 4: NEGative PPM Correction */
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#define RTC_MR_CORRECTION_SHIFT (8) /* Bits 8-14: Slow Clock Correction */
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#define RTC_MR_CORRECTION_MASK (0x7f << RTC_MR_CORRECTION_SHIFT)
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# define RTC_MR_CORRECTION_NONE (0 << RTC_MR_CORRECTION_SHIFT)
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# define RTC_MR_CORRECTION(n) ((uint8_t)(n) << RTC_MR_CORRECTION_SHIFT)
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#define RTC_MR_HIGHPPM (1 << 15) /* Bit 15: HIGH PPM Correction */
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#define RTC_MR_OUT0_SHIFT (16) /* Bits 16-18: RTCOUT0 OutputSource Selection */
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#define RTC_MR_OUT0_MASK (7 << RTC_MR_OUT0_SHIFT)
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# define RTC_MR_OUT0_NO_WAVE (0 << RTC_MR_OUT0_SHIFT) /* No waveform, stuck at 0 */
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# define RTC_MR_OUT0_FREQ1HZ (1 << RTC_MR_OUT0_SHIFT) /* 1 Hz square wave */
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# define RTC_MR_OUT0_FREQ32HZ (2 << RTC_MR_OUT0_SHIFT) /* 32 Hz square wave */
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# define RTC_MR_OUT0_FREQ64HZ (3 << RTC_MR_OUT0_SHIFT) /* 64 Hz square wave */
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# define RTC_MR_OUT0_FREQ512HZ (4 << RTC_MR_OUT0_SHIFT) /* 512 Hz square wave */
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# define RTC_MR_OUT0_ALARM_TOGGLE (5 << RTC_MR_OUT0_SHIFT) /* Output toggles when alarm flag rises */
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# define RTC_MR_OUT0_ALARM_FLAG (6 << RTC_MR_OUT0_SHIFT) /* Output is a copy of the alarm flag */
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# define RTC_MR_OUT0_PROG_PULSE (7 << RTC_MR_OUT0_SHIFT) /* Duty cycle programmable pulse */
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#define RTC_MR_OUT1_SHIFT (10) /* Bits 20-22: RTCOUT1 Output Source Selection */
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#define RTC_MR_OUT1_MASK (7 << RTC_MR_OUT1_SHIFT)
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# define RTC_MR_OUT1_NO_WAVE (0 << RTC_MR_OUT1_SHIFT) /* No waveform, stuck at 0 */
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# define RTC_MR_OUT1_FREQ1HZ (1 << RTC_MR_OUT1_SHIFT) /* 1 Hz square wave */
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# define RTC_MR_OUT1_FREQ32HZ (2 << RTC_MR_OUT1_SHIFT) /* 32 Hz square wave */
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# define RTC_MR_OUT1_FREQ64HZ (3 << RTC_MR_OUT1_SHIFT) /* 64 Hz square wave */
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# define RTC_MR_OUT1_FREQ512HZ (4 << RTC_MR_OUT1_SHIFT) /* 512 Hz square wave */
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# define RTC_MR_OUT1_ALARM_TOGGLE (5 << RTC_MR_OUT1_SHIFT) /* Output toggles when alarm flag rises */
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# define RTC_MR_OUT1_ALARM_FLAG (6 << RTC_MR_OUT1_SHIFT) /* Output is a copy of the alarm flag */
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# define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */
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#define RTC_MR_THIGH_SHIFT (24) /* Bits 24-16: High Duration of the Output Pulse */
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#define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT)
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# define RTC_MR_THIGH_31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
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# define RTC_MR_THIGH_16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
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# define RTC_MR_THIGH_4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
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# define RTC_MR_THIGH_976US (3 << RTC_MR_THIGH_SHIFT) /* 976 μs */
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# define RTC_MR_THIGH_488US (4 << RTC_MR_THIGH_SHIFT) /* 488 μs */
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# define RTC_MR_THIGH_122US (5 << RTC_MR_THIGH_SHIFT) /* 122 μs */
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# define RTC_MR_THIGH_30US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 μs */
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# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 μs */
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#define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */
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#define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT)
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# define RTC_MR_TPERIOD_ 1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */
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# define RTC_MR_TPERIOD_ 500MS (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */
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# define RTC_MR_TPERIOD_ 250MS (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */
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# define RTC_MR_TPERIOD_ 125MS (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */
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/* RTC Time Register */
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#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */
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#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT)
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# define RTC_TIMR_SEC(n) ((uint32_t)(n) << RTC_TIMR_SEC_SHIFT)
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#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */
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#define RTC_TIMR_MIN_MASK (0x7f << RTC_TIMR_MIN_SHIFT)
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# define RTC_TIMR_MIN(n) ((uint32_t)(n) << RTC_TIMR_MIN_SHIFT)
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#define RTC_TIMR_HOUR_SHIFT (16) /* Bits 16-21: Current Hour */
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#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT)
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# define RTC_TIMR_HOUR(n) ((uint32_t)(n) << RTC_TIMR_HOUR_SHIFT)
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#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */
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/* RTC Calendar Register */
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#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */
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#define RTC_CALR_CENT_MASK (0x7f << RTC_CALR_CENT_SHIFT)
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# define RTC_CALR_CENT(n) ((uint32_t)(n) << RTC_TIMR_HOUR_SHIFT)
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#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */
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#define RTC_CALR_YEAR_MASK (0xff << RTC_CALR_YEAR_SHIFT)
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# define RTC_CALR_YEAR(n) ((uint32_t)(n) << RTC_CALR_YEAR_SHIFT)
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#define RTC_CALR_MONTH_SHIFT (16) /* Bits 16-20: Current Month */
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#define RTC_CALR_MONTH_MASK (0x1f << RTC_CALR_MONTH_SHIFT)
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# define RTC_CALR_MONTH(n) ((uint32_t)(n) << RTC_CALR_MONTH_SHIFT)
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#define RTC_CALR_DAY_SHIFT (21) /* Bits 21-23: Current Day in Current Week */
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#define RTC_CALR_DAY_MASK (7 << RTC_CALR_DAY_SHIFT)
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# define RTC_CALR_DAY(n) ((uint32_t)(n) << RTC_CALR_DAY_SHIFT)
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#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */
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#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT)
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# define RTC_CALR_DATE(n) ((uint32_t)(n) << RTC_CALR_DATE_SHIFT)
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/* RTC Time Alarm Register */
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#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */
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#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT)
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# define RTC_TIMALR_SEC(n) ((uint32_t)(n) << RTC_TIMALR_SEC_SHIFT)
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#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */
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#define RTC_TIMALR_MIN_SHIFT (8) /* Bits 8-14: Minute Alarm */
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#define RTC_TIMALR_MIN_MASK (0x7f << RTC_TIMALR_MIN_SHIFT)
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# define RTC_TIMALR_MIN(n) ((uint32_t)(n) << RTC_TIMALR_MIN_SHIFT)
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#define RTC_TIMALR_MINEN (1 << 15) /* Bit 15: Minute Alarm Enable */
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#define RTC_TIMALR_HOUR_SHIFT (16) /* Bits 16-21: Hour Alarm */
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#define RTC_TIMALR_HOUR_MASK (0x3f << RTC_TIMALR_HOUR_SHIFT)
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# define RTC_TIMALR_HOUR(n) ((uint32_t)(n) << RTC_TIMALR_HOUR_SHIFT)
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#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */
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#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */
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/* RTC Calendar Alarm Register */
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#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */
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#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT)
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# define RTC_CALALR_MONTH(n) ((uint32_t)(n) << RTC_CALALR_MONTH_SHIFT)
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#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */
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#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */
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#define RTC_CALALR_DATE_MASK (0x3f << RTC_CALALR_DATE_SHIFT)
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# define RTC_CALALR_DATE(n) ((uint32_t)(n) << RTC_CALALR_DATE_SHIFT)
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#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */
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/* RTC Status Register */
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#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */
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#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */
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#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */
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#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */
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#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */
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#define RTC_SR_TDERR (1 << 5) /* Bit 5: Time and/or Date Free Running Error */
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/* RTC Status Clear Command Register */
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#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */
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#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */
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#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */
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#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */
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#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */
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#define RTC_SCCR_TDERRCLR (1 << 5) /* Bit 5: Time and/or Date Free Running Error Clear */
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/* RTC Interrupt Enable Register */
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#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */
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#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */
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#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */
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#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */
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#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */
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#define RTC_IER_TDERREN (1 << 5) /* Bit 5: Time and/or Date Free Running Error Enable */
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/* RTC Interrupt Disable Register */
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#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */
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#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */
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#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */
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#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */
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#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */
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#define RTC_IDR_TDERRDIS (1 << 5) /* Bit 5: Time and/or Date Free Running Error Disable */
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/* RTC Interrupt Mask Register */
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#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */
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#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */
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#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */
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#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */
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#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */
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#define RTC_IMR_TDERR (1 << 5) /* Bit 5: Time and/or Date Free Running Error Mask */
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/* RTC Valid Entry Register */
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#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */
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#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */
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#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */
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#define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RTC_H */
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