Make sure that all references to up_prioritize_irq() are conditioned on CONFIG_ARCH_IRQPRIO. Noted by Make Smith

arch/arm/src/kinetis/kinetis_enet.c

@@ -1465,12 +1465,14 @@ int kinetis_netinitialize(int intf)
   kinetis_pinconfig(PIN_RMII0_TXEN);
 #endif
 
+#ifdef CONFIG_ARCH_IRQPRIO
   /* Set interrupt priority levels */
 
   up_prioritize_irq(KINETIS_IRQ_EMACTMR, CONFIG_KINETIS_EMACTMR_PRIO);
   up_prioritize_irq(KINETIS_IRQ_EMACTX, CONFIG_KINETIS_EMACTX_PRIO);
   up_prioritize_irq(KINETIS_IRQ_EMACRX, CONFIG_KINETIS_EMACRX_PRIO);
   up_prioritize_irq(KINETIS_IRQ_EMACMISC, CONFIG_KINETIS_EMACMISC_PRIO);
+#endif
 
   /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */
 

arch/arm/src/kinetis/kinetis_sdhc.c

@@ -1688,9 +1688,11 @@ static int kinetis_attach(FAR struct sdio_dev_s *dev)
       putreg32(0,            KINETIS_SDHC_IRQSIGEN);
       putreg32(SDHC_INT_ALL, KINETIS_SDHC_IRQSTAT);
 
+#ifdef CONFIG_ARCH_IRQPRIO
       /* Set the interrupt priority */
 
       up_prioritize_irq(KINETIS_IRQ_SDHC, CONFIG_KINETIS_SDHC_PRIO);
+#endif
 
       /* Enable SDIO interrupts at the NVIC.  They can now be enabled at
        * the SDIO controller as needed.

arch/arm/src/kinetis/kinetis_serial.c

@@ -623,12 +623,15 @@ static int up_setup(struct uart_dev_s *dev)
 
   up_restoreuartint(priv, 0);
 
+#ifdef CONFIG_ARCH_IRQPRIO
   /* Set up the interrupt priority */
 
   up_prioritize_irq(priv->irqs, priv->irqprio);
 #ifdef CONFIG_DEBUG
   up_prioritize_irq(priv->irqe, priv->irqprio);
 #endif
+#endif
+
   return OK;
 }
 

arch/arm/src/kl/Make.defs

@@ -68,13 +68,17 @@ CMN_CSRCS += up_dumpnvic.c
 endif
 
 CHIP_ASRCS  =
-CHIP_CSRCS  = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_irqprio.c kl_lowgetc.c
+CHIP_CSRCS  = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_lowgetc.c
 CHIP_CSRCS += kl_lowputc.c kl_serial.c kl_start.c kl_timerisr.c kl_cfmconfig.c
 
 ifeq ($(CONFIG_NUTTX_KERNEL),y)
 CHIP_CSRCS += kl_userspace.c
 endif
 
+ifeq ($(CONFIG_ARCH_IRQPRIO),y)
+CHIP_CSRCS += kl_irqprio.c
+endif
+
 ifeq ($(CONFIG_KL_SPI0),y)
 CHIP_CSRCS += kl_spi.c
 else

arch/arm/src/samd/Make.defs

@@ -76,10 +76,10 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y)
 CHIP_CSRCS += sam_userspace.c
 endif
 
-ifeq ($(CONFIG_SAMD_HAVE_SPI),y)
-CHIP_CSRCS += sam_spi.c
-endif
-
 ifeq ($(CONFIG_ARCH_IRQPRIO),y)
 CHIP_CSRCS += sam_irqprio.c
 endif
+
+ifeq ($(CONFIG_SAMD_HAVE_SPI),y)
+CHIP_CSRCS += sam_spi.c
+endif

arch/arm/src/stm32/stm32_tim.c

@@ -398,6 +398,7 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
 
   up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
 #endif
+
   return OK;
 }
 

arch/arm/src/str71x/str71x_irq.c

@@ -208,6 +208,7 @@ void up_maskack_irq(int irq)
  *
  ****************************************************************************/
 
+#ifdef CONFIG_ARCH_IRQPRIO
 int up_prioritize_irq(int irq, int priority)
 {
   uint32_t addr;
@@ -229,4 +230,5 @@ int up_prioritize_irq(int irq, int priority)
 
   return -EINVAL;
 }
+#endif
 

arch/arm/src/str71x/str71x_serial.c

@@ -628,10 +628,13 @@ static int up_attach(struct uart_dev_s *dev)
 
        up_enable_irq(priv->irq);
 
+#ifdef CONFIG_ARCH_IRQPRIO
        /* Set the uart interrupt priority (the default value is one) */
 
        up_prioritize_irq(priv->irq, CONFIG_UART_PRI);
     }
+#endif
+
   return ret;
 }
 

arch/arm/src/str71x/str71x_timerisr.c

@@ -198,9 +198,11 @@ void up_timerinit(void)
   putreg16(OCAR_VALUE, STR71X_TIMER0_OCAR);
   putreg16(0xfffc, STR71X_TIMER0_CNTR);
 
+#ifdef CONFIG_ARCH_IRQPRIO
   /* Set the timer interrupt priority */
 
   up_prioritize_irq(STR71X_IRQ_SYSTIMER, CONFIG_TIM_PRI);
+#endif
 
   /* Attach the timer interrupt vector */
 

arch/mips/src/pic32mx/pic32mx-irq.c

@@ -80,6 +80,10 @@ volatile uint32_t *current_regs;
  * Private Functions
  ****************************************************************************/
 
+#ifndef CONFIG_ARCH_IRQPRIO
+static int up_prioritize_irq(int irq, int priority);
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -436,7 +440,9 @@ void up_clrpend_irq(int irq)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_ARCH_IRQPRIO
+#ifndef CONFIG_ARCH_IRQPRIO
+static
+#endif
 int up_prioritize_irq(int irq, int priority)
 {
   int regndx;
@@ -467,4 +473,3 @@ int up_prioritize_irq(int irq, int priority)
 
   return -EINVAL;
 }
-#endif

arch/mips/src/pic32mx/pic32mx-serial.c

@@ -362,9 +362,12 @@ static int up_setup(struct uart_dev_s *dev)
                         priv->bits, priv->stopbits2);
 #endif
 
+#ifdef CONFIG_ARCH_IRQPRIO
   /* Set up the interrupt priority */
 
   up_prioritize_irq(priv->irq, priv->irqprio);
+#endif
+
   return OK;
 }
 

arch/mips/src/pic32mx/pic32mx-spi.c

@@ -1007,6 +1007,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
   up_enable_irq(priv->txirq);
   up_enable_irq(priv->rxirq);
 
+#ifdef CONFIG_ARCH_IRQPRIO
   /* Set the SPI interrupt priority */
 
   ret = up_prioritize_irq(priv->vector, CONFIG_PIC32MX_SPI_PRIORITY)
@@ -1015,6 +1016,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
       spidbg("up_prioritize_irq failed: %d\n", ret);
       goto errout;
     }
+#endif
 #endif
 
   /* Enable interrupts at the interrupt controller */

arch/mips/src/pic32mx/pic32mx-timerisr.c

@@ -181,7 +181,9 @@ void up_timerinit(void)
   /* Configure the timer interrupt */
 
   up_clrpend_irq(PIC32MX_IRQSRC_T1);
+#ifdef CONFIG_ARCH_IRQPRIO
   (void)up_prioritize_irq(PIC32MX_IRQ_T1, CONFIG_PIC32MX_T1PRIO);
+#endif
 
   /* Attach the timer interrupt vector */
 

arch/sh/src/sh1/sh1_irq.c

@@ -96,6 +96,7 @@ void up_irqinitialize(void)
  *
  ****************************************************************************/
 
+#ifdef CONFIG_ARCH_IRQPRIO
 void up_prioritize_irq(int irq, int priority)
 {
   uint16_t mask;
@@ -282,4 +283,4 @@ void up_prioritize_irq(int irq, int priority)
   reg16 |= (priority << shift);
   putreg16(reg16, reg);
 }
-
+#endif /* CONFIG_ARCH_IRQPRIO */

arch/sh/src/sh1/sh1_serial.c

@@ -499,10 +499,11 @@ static int up_attach(struct uart_dev_s *dev)
           ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt);
           if (ret == OK)
             {
+#ifdef CONFIG_ARCH_IRQPRIO
               /* All SCI0 interrupts share the same prioritization */
 
               up_prioritize_irq(priv->irq, 7);  /* Set SCI priority midway */
-
+#endif
               /* Return OK on success */
 
               return OK;
@@ -545,11 +546,13 @@ static void up_detach(struct uart_dev_s *dev)
   (void)irq_detach(priv->irq + SH1_ERI_IRQ_OFFSET);
   (void)irq_detach(priv->irq + SH1_RXI_IRQ_OFFSET);
 
+#ifdef CONFIG_ARCH_IRQPRIO
   /* Set the interrupt priority to zero (masking all SCI interrupts).  NOTE
    * that all SCI0 interrupts share the same prioritization.
    */
 
   up_prioritize_irq(priv->irq, 0);
+#endif
 }
 
 /****************************************************************************

arch/sh/src/sh1/sh1_timerisr.c

@@ -193,9 +193,11 @@ void up_timerinit(void)
 
   putreg8(SH1_ITUTIER_IMIEA, SH1_ITU0_TIER);
 
+#ifdef CONFIG_ARCH_IRQPRIO
   /* Set the interrupt priority */
 
   up_prioritize_irq(SH1_SYSTIMER_IRQ, 7);  /* Set ITU priority midway */
+#endif
 
   /* Start the timer */
 

arch/z16/src/z16f/z16f_irq.c

@@ -209,10 +209,11 @@ void up_maskack_irq(int irq)
  *
  ****************************************************************************/
 
+#ifdef CONFIG_ARCH_IRQPRIO
 int up_prioritize_irq(int irq, int priority)
 {
   /* To be provided */
 
   return -ENOSYS;
 }
-
+#endif