arch/xmc4: Added pwm driver

arch/arm/src/xmc4/CMakeLists.txt

@@ -51,4 +51,8 @@ if(CONFIG_XMC4_USCI_SPI)
   list(APPEND SRCS xmc4_spi.c)
 endif()
 
+if(CONFIG_XMC4_PWM)
+  list(APPEND SRCS xmc4_pwm.c)
+endif()
+
 target_sources(arch PRIVATE ${SRCS})

arch/arm/src/xmc4/Kconfig

@@ -194,6 +194,12 @@ config XMC4_ECAT_P1
 	default n
 	depends on XMC4_ECAT
 
+config XMC4_PWM
+	bool "Enable Capture Compare Units 4 (CCU4x) for PWM"
+	default n
+	---help---
+		Support CCU4x
+
 endmenu
 
 menu "XMC4xxx USIC Configuration"
@@ -255,7 +261,7 @@ config XMC4_USIC0_CHAN0_TX_BUFFER_SIZE
 	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 config XMC4_USIC0_CHAN0_RX_BUFFER_SIZE
@@ -264,7 +270,7 @@ config XMC4_USIC0_CHAN0_RX_BUFFER_SIZE
 	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 endmenu # USIC0 Channel 0 Configuration
@@ -318,7 +324,7 @@ config XMC4_USIC0_CHAN1_ISI2S
 	---help---
 		Configure USIC0 Channel 1 for I2S audio
 
-endchoice # USIC0 Channel 1 Protocol 
+endchoice # USIC0 Channel 1 Protocol
 
 config XMC4_USIC0_CHAN1_TX_BUFFER_SIZE
 	int "Tx Fifo Buffer Size"
@@ -326,7 +332,7 @@ config XMC4_USIC0_CHAN1_TX_BUFFER_SIZE
 	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 config XMC4_USIC0_CHAN1_RX_BUFFER_SIZE
@@ -335,7 +341,7 @@ config XMC4_USIC0_CHAN1_RX_BUFFER_SIZE
 	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 endmenu # USIC0 Channel 1 Configuration
@@ -388,7 +394,7 @@ config XMC4_USIC1_CHAN0_ISI2S
 	---help---
 		Configure USIC1 Channel 0 for I2S audio
 
-endchoice # USIC1 Channel 0 Protocol 
+endchoice # USIC1 Channel 0 Protocol
 
 config XMC4_USIC1_CHAN0_TX_BUFFER_SIZE
 	int "Tx Fifo Buffer Size"
@@ -396,7 +402,7 @@ config XMC4_USIC1_CHAN0_TX_BUFFER_SIZE
 	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 config XMC4_USIC1_CHAN0_RX_BUFFER_SIZE
@@ -405,10 +411,10 @@ config XMC4_USIC1_CHAN0_RX_BUFFER_SIZE
 	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
-endmenu # USIC1 Channel 0 Configuration 
+endmenu # USIC1 Channel 0 Configuration
 
 menu "USIC1 Channel 1 Configuration"
 	depends on XMC4_USIC
@@ -463,19 +469,19 @@ endchoice # USIC1 Channel 1 Protocol
 config XMC4_USIC1_CHAN1_TX_BUFFER_SIZE
 	int "Tx Fifo Buffer Size"
 	depends on XMC4_USIC1_CHAN1_ISUART
-	default 16 
+	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 config XMC4_USIC1_CHAN1_RX_BUFFER_SIZE
 	int "Rx Fifo Buffer Size"
 	depends on XMC4_USIC1_CHAN1_ISUART
-	default 16 
+	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 endmenu # USIC1 Channel 1 Configuration
@@ -533,19 +539,19 @@ endchoice # USIC2 Channel 0 Protocol
 config XMC4_USIC2_CHAN0_TX_BUFFER_SIZE
 	int "Tx Fifo Buffer Size"
 	depends on XMC4_USIC2_CHAN0_ISUART
-	default 16 
+	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 config XMC4_USIC2_CHAN0_RX_BUFFER_SIZE
 	int "Rx Fifo Buffer Size"
 	depends on XMC4_USIC2_CHAN0_ISUART
-	default 16 
+	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 endmenu # USIC2 Channel 0 Configuration
@@ -605,7 +611,7 @@ config XMC4_USIC2_CHAN1_TX_BUFFER_SIZE
 	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 config XMC4_USIC2_CHAN1_RX_BUFFER_SIZE
@@ -614,9 +620,150 @@ config XMC4_USIC2_CHAN1_RX_BUFFER_SIZE
 	default 16
 	---help---
 		Should be a power of 2 between 2 and 64
-		The sum of Rx and Tx buffers sizes of both 
+		The sum of Rx and Tx buffers sizes of both
 		channels should be inferior to 64
 
 endmenu # USIC2 Channel 1 Configuration
 
 endmenu # XMC4xxx USIC Configuration
+
+menu "XMC4xxx PWM Configuration"
+depends on XMC4_PWM
+
+	config XMC4_CCU40
+		bool "Enable CCU40"
+		default n
+		---help---
+			Support CCU40
+
+		config XMC4_CCU40_CC40
+			bool "Enable CCU40 Slice 0 (not compatible with tickless)"
+			default n
+			depends on XMC4_CCU40 && !CONFIG_SCHED_TICKLESS
+			---help---
+				Support CCU40 CC40, cannot be activated when tickless OS is enabled
+
+		config XMC4_CCU40_CC41
+			bool "Enable CCU40 Slice 1"
+			default n
+			depends on XMC4_CCU40
+			---help---
+				Support CCU40 CC41
+
+		config XMC4_CCU40_CC42
+			bool "Enable CCU40 Slice 2"
+			default n
+			depends on XMC4_CCU40
+			---help---
+				Support CCU40 CC42
+
+		config XMC4_CCU40_CC43
+			bool "Enable CCU40 Slice 3"
+			default n
+			depends on XMC4_CCU40
+			---help---
+				Support CCU40 CC43
+
+	config XMC4_CCU41
+		bool "Enable CCU41"
+		default n
+		---help---
+			Support CCU41
+
+		config XMC4_CCU41_CC40
+			bool "Enable CCU41 Slice 0 (not compatible with tickless)"
+			default n
+			depends on XMC4_CCU41 && !CONFIG_SCHED_TICKLESS
+			---help---
+				Support CCU41 CC40, cannot be activated when tickless OS is enabled
+
+		config XMC4_CCU41_CC41
+			bool "Enable CCU41 Slice 1"
+			default n
+			depends on XMC4_CCU41
+			---help---
+				Support CCU41 CC41
+
+		config XMC4_CCU41_CC42
+			bool "Enable CCU41 Slice 2"
+			default n
+			depends on XMC4_CCU41
+			---help---
+				Support CCU41 CC42
+
+		config XMC4_CCU41_CC43
+			bool "Enable CCU41 Slice 3"
+			default n
+			depends on XMC4_CCU41
+			---help---
+				Support CCU41 CC43
+
+	config XMC4_CCU42
+		bool "Enable CCU42"
+		default n
+		---help---
+			Support CCU42
+
+		config XMC4_CCU42_CC40
+			bool "Enable CCU42 Slice 0"
+			default n
+			depends on XMC4_CCU42
+			---help---
+				Support CCU42 CC40
+
+		config XMC4_CCU42_CC41
+			bool "Enable CCU42 Slice 1"
+			default n
+			depends on XMC4_CCU42
+			---help---
+				Support CCU42 CC41
+
+		config XMC4_CCU42_CC42
+			bool "Enable CCU42 Slice 2"
+			default n
+			depends on XMC4_CCU42
+			---help---
+				Support CCU42 CC42
+
+		config XMC4_CCU42_CC43
+			bool "Enable CCU42 Slice 3"
+			default n
+			depends on XMC4_CCU42
+			---help---
+				Support CCU42 CC43
+
+	config XMC4_CCU43
+		bool "Enable CCU43"
+		default n
+		---help---
+			Support CCU43
+
+		config XMC4_CCU43_CC40
+			bool "Enable CCU43 Slice 0"
+			default n
+			depends on XMC4_CCU43
+			---help---
+				Support CCU43 CC40
+
+		config XMC4_CCU43_CC41
+			bool "Enable CCU43 Slice 1"
+			default n
+			depends on XMC4_CCU43
+			---help---
+				Support CCU43 CC41
+
+		config XMC4_CCU43_CC42
+			bool "Enable CCU43 Slice 2"
+			default n
+			depends on XMC4_CCU43
+			---help---
+				Support CCU43 CC42
+
+		config XMC4_CCU43_CC43
+			bool "Enable CCU43 Slice 3"
+			default n
+			depends on XMC4_CCU43
+			---help---
+				Support CCU43 CC43
+
+endmenu # XMC4xxx PWM Configuration

arch/arm/src/xmc4/Make.defs

@@ -55,3 +55,7 @@ endif
 ifeq ($(CONFIG_XMC4_ECAT),y)
 CHIP_CSRCS += xmc4_ecat.c
 endif
+
+ifeq ($(CONFIG_XMC4_PWM),y)
+CHIP_CSRCS += xmc4_pwm.c
+endif

arch/arm/src/xmc4/hardware/xmc4_ccu4.h

@@ -783,9 +783,9 @@
 #define CCU4_GSTAT_S2I_SHIFT          (2)                            /* Bits 2: CC42 IDLE status */
 #define CCU4_GSTAT_S2I_MASK           (1 << CCU4_GSTAT_S2I_SHIFT)
 #define CCU4_GSTAT_S3I_SHIFT          (3)                            /* Bits 3: CC43 IDLE status */
-#define CCU4_GSTAT_S3I_MASK           (1 << CCU4_GSTAT_SI_SHIFT)
+#define CCU4_GSTAT_S3I_MASK           (1 << CCU4_GSTAT_S3I_SHIFT)
 #define CCU4_GSTAT_PRB_SHIFT          (8)                            /* Bits 8: Prescaler Run Bit */
-#define CCU4_GSTAT_PRB_MASK           (1 << CCU4_GSTAT_SI_SHIFT)
+#define CCU4_GSTAT_PRB_MASK           (1 << CCU4_GSTAT_PRB_SHIFT)
 
 /* Global Idle Set (GIDLS) */
 
@@ -934,7 +934,7 @@
 /* Input Selector Configuration (CC4yINS) */
 
 #define CCU4_CC4_INS_EV0IS_SHIFT                (0)                                     /* Bits 0-3: Event 0 signal selection */
-#define CCU4_CC4_INS_EV0IS_MASK                 (15 << CCU4_CC4_INS_EV0IS_SHIFT)        
+#define CCU4_CC4_INS_EV0IS_MASK                 (15 << CCU4_CC4_INS_EV0IS_SHIFT)
 #   define CCU4_CC4_INS_EV0IS_INA               (0 << CCU4_CC4_INS_EV0IS_SHIFT)         /* CCU4x.INyA */
 #   define CCU4_CC4_INS_EV0IS_INB               (1 << CCU4_CC4_INS_EV0IS_SHIFT)         /* CCU4x.INyB */
 #   define CCU4_CC4_INS_EV0IS_INC               (2 << CCU4_CC4_INS_EV0IS_SHIFT)         /* CCU4x.INyC */
@@ -952,7 +952,7 @@
 #   define CCU4_CC4_INS_EV0IS_INO               (14 << CCU4_CC4_INS_EV0IS_SHIFT)        /* CCU4x.INyO */
 #   define CCU4_CC4_INS_EV0IS_INP               (15 << CCU4_CC4_INS_EV0IS_SHIFT)        /* CCU4x.INyP */
 #define CCU4_CC4_INS_EV1IS_SHIFT                (4)                                     /* Bits 4-7: Event 1 signal selection */
-#define CCU4_CC4_INS_EV1IS_MASK                 (15 << CCU4_CC4_INS_EV1IS_SHIFT)        
+#define CCU4_CC4_INS_EV1IS_MASK                 (15 << CCU4_CC4_INS_EV1IS_SHIFT)
 #   define CCU4_CC4_INS_EV1IS_INA               (0 << CCU4_CC4_INS_EV1IS_SHIFT)         /* CCU4x.INyA */
 #   define CCU4_CC4_INS_EV1IS_INB               (1 << CCU4_CC4_INS_EV1IS_SHIFT)         /* CCU4x.INyB */
 #   define CCU4_CC4_INS_EV1IS_INC               (2 << CCU4_CC4_INS_EV1IS_SHIFT)         /* CCU4x.INyC */
@@ -970,7 +970,7 @@
 #   define CCU4_CC4_INS_EV1IS_INO               (14 << CCU4_CC4_INS_EV1IS_SHIFT)        /* CCU4x.INyO */
 #   define CCU4_CC4_INS_EV1IS_INP               (15 << CCU4_CC4_INS_EV1IS_SHIFT)        /* CCU4x.INyP */
 #define CCU4_CC4_INS_EV2IS_SHIFT                (8)                                     /* Bits 8-11: Event 2 signal selection */
-#define CCU4_CC4_INS_EV2IS_MASK                 (15 << CCU4_CC4_INS_EV2IS_SHIFT)        
+#define CCU4_CC4_INS_EV2IS_MASK                 (15 << CCU4_CC4_INS_EV2IS_SHIFT)
 #   define CCU4_CC4_INS_EV2IS_INA               (0 << CCU4_CC4_INS_EV2IS_SHIFT)         /* CCU4x.INyA */
 #   define CCU4_CC4_INS_EV2IS_INB               (1 << CCU4_CC4_INS_EV2IS_SHIFT)         /* CCU4x.INyB */
 #   define CCU4_CC4_INS_EV2IS_INC               (2 << CCU4_CC4_INS_EV2IS_SHIFT)         /* CCU4x.INyC */

arch/arm/src/xmc4/xmc4_clockconfig.h

@@ -72,4 +72,15 @@ uint32_t xmc4_get_coreclock(void);
 
 uint32_t xmc4_get_periphclock(void);
 
+/****************************************************************************
+ * Name: xmc4_get_ccuclock
+ *
+ * Description:
+ *   The ccu clock is either fCPU or fCPU/2, depending on the state
+ *   of the peripheral divider.
+ *
+ ****************************************************************************/
+
+uint32_t xmc4_get_ccuclock(void);
+
 #endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */

arch/arm/src/xmc4/xmc4_clockutils.c

@@ -186,3 +186,20 @@ uint32_t xmc4_get_periphclock(void)
 
   return periphclock;
 }
+
+/****************************************************************************
+ * Name: xmc4_get_ccuclock
+ *
+ * Description:
+ *   The ccu clock is either fCPU or fCPU/2, depending on the state
+ *   of the peripheral divider.
+ *
+ ****************************************************************************/
+
+uint32_t xmc4_get_ccuclock(void)
+{
+  uint32_t f_cpu = xmc4_get_coreclock();
+  uint32_t f_ccu =
+    f_cpu >> ((uint32_t)(getreg32(XMC4_SCU_CCUCLKCR) & SCU_CCUCLKCR_CCUDIV));
+  return  f_ccu;
+}

arch/arm/src/xmc4/xmc4_pwm.h

@@ -29,6 +29,10 @@
 
 #include "chip.h"
 
+#include <nuttx/timers/pwm.h>
+
+#include <arch/board/board.h>
+
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -73,7 +77,7 @@ extern "C"
  *
  ****************************************************************************/
 
-struct pwm_lowerhalf_s *xmc4_pwm_initialize(int timer);
+struct pwm_lowerhalf_s *xmc4_pwminitialize(int module, int slice);
 
 #undef EXTERN
 #if defined(__cplusplus)
@@ -81,5 +85,4 @@ struct pwm_lowerhalf_s *xmc4_pwm_initialize(int timer);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* CONFIG_XMC4_FTMx_PWM */
+#endif /* __ARCH_ARM_SRC_XMC4_XMC4_PWM_H */
-#endif /* __ARCH_ARM_SRC_XMC4_XMC4_PWM_H */