diff --git a/ChangeLog b/ChangeLog index 60d7be5be5..72aec7ccaf 100644 --- a/ChangeLog +++ b/ChangeLog @@ -4938,7 +4938,8 @@ to the SAM4L Xplained Pro board configuration (2013-6-9). * arm/src/sam34/chip/sam_irq.c: Extend IRQ support to handle the larger number of NVIC interrupts used by the SAM4L (2013-6-9). - * arch/srcm/sam45/chip: Beginning updates of SAM3U header files - to include support for the SAM4S: WDT, SUPC, EEFC, MATRIX, and PMC - (2013-6-10). - + * arch/arm/src/sam45/chip: Beginning updates of SAM3U header files + to include support for the SAM4S: WDT, SUPC, EEFC, MATRIX, PMC, + UARTs, USARTs, HSMCI, SPI (2013-6-10). + * arch/arm/src/chip/sam4s_memorymap.h, sam4s_irq.h, and sam4s_vectors.h: + Add SAM4S memory map and interrupt definitions (2013-6-10) diff --git a/arch/arm/include/sam34/irq.h b/arch/arm/include/sam34/irq.h index ea93b22b7d..4925273eb2 100644 --- a/arch/arm/include/sam34/irq.h +++ b/arch/arm/include/sam34/irq.h @@ -81,6 +81,8 @@ # include #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include #else # error Unrecognized SAM architecture #endif diff --git a/arch/arm/include/sam34/sam4s_irq.h b/arch/arm/include/sam34/sam4s_irq.h new file mode 100644 index 0000000000..7dc095748b --- /dev/null +++ b/arch/arm/include/sam34/sam4s_irq.h @@ -0,0 +1,284 @@ +/**************************************************************************************** + * arch/arm/include/sam34/sam4s_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H +#define __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Definitions + ****************************************************************************************/ + +/* SAM3U Peripheral Identifiers */ + +#define SAM_PID_SUPC (0) /* Supply Controller */ +#define SAM_PID_RSTC (1) /* Reset Controller */ +#define SAM_PID_RTC (2) /* Real Time Clock */ +#define SAM_PID_RTT (3) /* Real Time Timer */ +#define SAM_PID_WDT (4) /* Watchdog Timer */ +#define SAM_PID_PMC (5) /* Power Management Controller */ +#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */ +#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */ +#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter 0 */ +#define SAM_PID_UART1 (9) /* Universal Asynchronous Receiver Transmitter 1 */ +#define SAM_PID_SMC (10) /* Static Memory Controller */ +#define SAM_PID_PIOA (11) /* Parallel I/O Controller A */ +#define SAM_PID_PIOB (12) /* Parallel I/O Controller B */ +#define SAM_PID_PIOC (13) /* Parallel I/O Controller C */ +#define SAM_PID_USART0 (14) /* USART 0 */ +#define SAM_PID_USART1 (15) /* USART 1 */ +#define SAM_PID_RESERVED_16 (16) /* Reserved */ +#define SAM_PID_RESERVED_17 (17) /* Reserved */ +#define SAM_PID_HSMCI (18) /* High Speed Multimedia Card Interface */ +#define SAM_PID_TWI0 (19) /* Two-Wire Interface 0 */ +#define SAM_PID_TWI1 (20) /* Two-Wire Interface 1 */ +#define SAM_PID_SSC (22) /* Synchronous Serial Controller */ +#define SAM_PID_TC0 (23) /* Timer Counter 0 */ +#define SAM_PID_TC1 (24) /* Timer Counter 1 */ +#define SAM_PID_TC2 (25) /* Timer Counter 2 */ +#define SAM_PID_TC3 (26) /* Timer Counter 3 */ +#define SAM_PID_TC4 (27) /* Timer Counter 4 */ +#define SAM_PID_TC5 (28) /* Timer Counter 5 */ +#define SAM_PID_ADC (29) /* Analog To Digital Converter */ +#define SAM_PID_DACC (30) /* Digital To Analog Converter */ +#define SAM_PID_PWM (31) /* Pulse Width Modulation */ +#define SAM_PID_CRCCU (32) /* CRC Calculation Unit */ +#define SAM_PID_ACC (33) /* Analog Comparator */ +#define SAM_PID_UDP (34) /* USB Device Port */ +#define NR_PIDS (35) /* Number of peripheral identifiers */ + +/* External interrupts (vectors >= 16) */ + +#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* PID 0: Supply Controller */ +#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* PID 1: Reset Controller */ +#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* PID 2: Real Time Clock */ +#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* PID 3: Real Time Timer */ +#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* PID 4: Watchdog Timer */ +#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* PID 5: Power Management Controller */ +#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* PID 6: Enhanced Embedded Flash Controller 0 */ +#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* PID 7: Enhanced Embedded Flash Controller 1 */ +#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* PID 8: Universal Asynchronous Receiver Transmitter 0 */ +#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* PID 9: Universal Asynchronous Receiver Transmitter 1 */ +#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* PID 10: Static Memory Controller */ +#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* PID 11: Parallel I/O Controller A */ +#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* PID 12: Parallel I/O Controller B */ +#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* PID 13: Parallel I/O Controller C */ +#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* PID 14: USART 0 */ +#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* PID 15: USART 1 */ +#define SAM_IRQ_RESERVED_16 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_16) /* PID 16: Reserved */ +#define SAM_IRQ_RESERVED_17 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_17) /* PID 17: Reserved */ +#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* PID 18: High Speed Multimedia Card Interface */ +#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* PID 19: Two-Wire Interface 0 */ +#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* PID 20: Two-Wire Interface 1 */ +#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* PID 22: Synchronous Serial Controller */ +#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* PID 23: Timer Counter 0 */ +#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* PID 24: Timer Counter 1 */ +#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* PID 25: Timer Counter 2 */ +#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* PID 26: Timer Counter 3 */ +#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* PID 27: Timer Counter 4 */ +#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* PID 28: Timer Counter 5 */ +#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* PID 29: Analog To Digital Converter */ +#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+SAM_PID_DACC) /* PID 30: Digital To Analog Converter */ +#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PID 31: Pulse Width Modulation */ +#define SAM_IRQ_CRCCU (SAM_IRQ_EXTINT+SAM_PID_CRCCU) /* PID 32: CRC Calculation Unit */ +#define SAM_IRQ_ACC (SAM_IRQ_EXTINT+SAM_PID_ACC) /* PID 33: Analog Comparator */ +#define SAM_IRQ_UDP (SAM_IRQ_EXTINT+SAM_PID_UDP) /* PID 34: USB Device Port */ + +#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */ +#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT + NR_PIDS) /* The number of real IRQs */ + +/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */ + +#ifdef CONFIG_GPIOA_IRQ +# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT) +# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */ +# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */ +# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */ +# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */ +# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */ +# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */ +# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */ +# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */ +# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */ +# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */ +# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */ +# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */ +# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */ +# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */ +# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */ +# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */ +# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */ +# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */ +# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */ +# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */ +# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */ +# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */ +# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */ +# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */ +# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */ +# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */ +# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */ +# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */ +# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */ +# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */ +# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */ +# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOAIRQS 0 +#endif + +#ifdef CONFIG_GPIOB_IRQ +# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_IRQ_GPIOA_PINS) +# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ +# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ +# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ +# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */ +# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */ +# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */ +# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */ +# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */ +# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */ +# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */ +# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */ +# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */ +# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */ +# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */ +# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */ +# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */ +# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */ +# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */ +# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */ +# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */ +# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */ +# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */ +# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */ +# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */ +# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */ +# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */ +# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */ +# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */ +# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */ +# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ +# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ +# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOBIRQS 0 +#endif + +#ifdef CONFIG_GPIOC_IRQ +# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_IRQ_GPIOA_PINS + SAM_IRQ_GPIOB_PINS) +# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ +# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ +# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ +# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */ +# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */ +# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */ +# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */ +# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */ +# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */ +# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */ +# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */ +# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */ +# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */ +# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */ +# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */ +# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */ +# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */ +# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */ +# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */ +# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */ +# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */ +# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */ +# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */ +# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */ +# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */ +# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */ +# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */ +# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */ +# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */ +# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ +# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ +# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOCIRQS 0 +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT + \ + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Variables + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H */ + diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index 0ac0e3d58b..8a3a606e06 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -212,11 +212,17 @@ config SAM34_TWIM3 default n depends on ARCH_CHIP_SAM4L -config SAM34_UART - bool "UART" +config SAM34_UART0 + bool "UART0" default y - depends on ARCH_CHIP_SAM3U - select ARCH_HAVE_UART + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + select ARCH_HAVE_UART0 + +config SAM43_UART1 + bool "UART1" + default y + depends on ARCH_CHIP_SAM4S + select ARCH_HAVE_UART1 config SAM34_PICOUART bool "PicoUART" diff --git a/arch/arm/src/sam34/chip/sam3u_memorymap.h b/arch/arm/src/sam34/chip/sam3u_memorymap.h index 7e66c0b50f..f393364009 100644 --- a/arch/arm/src/sam34/chip/sam3u_memorymap.h +++ b/arch/arm/src/sam34/chip/sam3u_memorymap.h @@ -91,7 +91,7 @@ # define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */ /* 0x400e2600-0x400fffff: Reserved */ /* 0x40100000-0x41ffffff: Reserved */ -# define SAM_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ +# define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ /* 0x44000000-0x5fffffff: Reserved */ #define SAM_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */ # define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ @@ -111,7 +111,7 @@ #define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ #define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ #define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ -#define SAM_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */ +#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */ #define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ #define SAM_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/ # define SAM_EEFCN_BASE(n) (0x400e0800+((n)<<9)) diff --git a/arch/arm/src/sam34/chip/sam3u_uart.h b/arch/arm/src/sam34/chip/sam3u_uart.h index bd2dc23c27..bf2dbff2d2 100644 --- a/arch/arm/src/sam34/chip/sam3u_uart.h +++ b/arch/arm/src/sam34/chip/sam3u_uart.h @@ -1,5 +1,7 @@ /************************************************************************************************ * arch/arm/src/sam34/chip/sam3u_uart.h + * Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous + * Receiver Transmitter (USART) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -56,14 +58,14 @@ #define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ #define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ #define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ -#define SAM_UART_SR_OFFSET 0x0014 /* Status Register (Common) */ +#define SAM_UART_SR_OFFSET 0x0014 /* [Channel] Status Register (Common) */ #define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ #define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ #define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ /* 0x0024-0x003c: Reserved (UART) */ #define SAM_UART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ #define SAM_UART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ - /* 0x002c-0x003c: Reserved (UART) */ + /* 0x002c-0x003c: Reserved (USART) */ #define SAM_UART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ #define SAM_UART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ /* 0x0048: Reserved (USART) */ @@ -71,21 +73,31 @@ #define SAM_UART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ #define SAM_UART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ #define SAM_UART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ - /* 0x005c-0xf008: Reserved (USART) */ + /* 0x005c-0xf8: Reserved (USART) */ #define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ /* 0x0100-0x0124: PDC Area (Common) */ /* UART register adresses ***********************************************************************/ -#define SAM_UART_CR (SAM_UART_BASE+SAM_UART_CR_OFFSET) -#define SAM_UART_MR (SAM_UART_BASE+SAM_UART_MR_OFFSET) -#define SAM_UART_IER (SAM_UART_BASE+SAM_UART_IER_OFFSET) -#define SAM_UART_IDR (SAM_UART_BASE+SAM_UART_IDR_OFFSET) -#define SAM_UART_IMR (SAM_UART_BASE+SAM_UART_IMR_OFFSET) -#define SAM_UART_SR (SAM_UART_BASE+SAM_UART_SR_OFFSET) -#define SAM_UART_RHR (SAM_UART_BASE+SAM_UART_RHR_OFFSET) -#define SAM_UART_THR (SAM_UART_BASE+SAM_UART_THR_OFFSET) -#define SAM_UART_BRGR (SAM_UART_BASE+SAM_UART_BRGR_OFFSET) +#define SAM_UART0_CR (SAM_UART0_BASE+SAM_UART_CR_OFFSET) +#define SAM_UART0_MR (SAM_UART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_UART0_IER (SAM_UART0_BASE+SAM_UART_IER_OFFSET) +#define SAM_UART0_IDR (SAM_UART0_BASE+SAM_UART_IDR_OFFSET) +#define SAM_UART0_IMR (SAM_UART0_BASE+SAM_UART_IMR_OFFSET) +#define SAM_UART0_SR (SAM_UART0_BASE+SAM_UART_SR_OFFSET) +#define SAM_UART0_RHR (SAM_UART0_BASE+SAM_UART_RHR_OFFSET) +#define SAM_UART0_THR (SAM_UART0_BASE+SAM_UART_THR_OFFSET) +#define SAM_UART0_BRGR (SAM_UART0_BASE+SAM_UART_BRGR_OFFSET) + +#define SAM_UART1_CR (SAM_UART1_BASE+SAM_UART_CR_OFFSET) +#define SAM_UART1_MR (SAM_UART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_UART1_IER (SAM_UART1_BASE+SAM_UART_IER_OFFSET) +#define SAM_UART1_IDR (SAM_UART1_BASE+SAM_UART_IDR_OFFSET) +#define SAM_UART1_IMR (SAM_UART1_BASE+SAM_UART_IMR_OFFSET) +#define SAM_UART1_SR (SAM_UART1_BASE+SAM_UART_SR_OFFSET) +#define SAM_UART1_RHR (SAM_UART1_BASE+SAM_UART_RHR_OFFSET) +#define SAM_UART1_THR (SAM_UART1_BASE+SAM_UART_THR_OFFSET) +#define SAM_UART1_BRGR (SAM_UART1_BASE+SAM_UART_BRGR_OFFSET) #define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) #define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) @@ -201,11 +213,11 @@ #define UART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ #define UART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ #define UART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ -#define UART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */ +#define UART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART SPI mode only) */ #define UART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ -#define UART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */ +#define UART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART SPI mode only) */ -/* UART Mode Register */ +/* UART Mode Register and USART Mode Register (UART MODE) */ #define UART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ #define UART_MR_MODE_MASK (15 << UART_MR_MODE_SHIFT) @@ -215,8 +227,8 @@ # define UART_MR_MODE_ISO7816_0 (4 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ # define UART_MR_MODE_ISO7816_1 (6 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ # define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */ -# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master */ -# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave */ +# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master (SPI mode only) */ +# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave (SPI mode only) */ #define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ #define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) # define UART_MR_USCLKS_MCK (0 << UART_MR_USCLKS_SHIFT) /* MCK */ @@ -229,7 +241,7 @@ # define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */ # define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ #define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ -#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */ +#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART SPI mode only) */ #define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ #define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) # define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ @@ -250,11 +262,16 @@ # define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ # define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ #define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first (USART only) */ -#define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity (USART only) */ +#define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity (USART SPI mode only) */ #define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ #define UART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ #define UART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ #define UART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_MR_WRDBT (1 << 20) /* Bit 20: Wait Read Data Before Transfer (SPI mode only) */ +#endif + #define UART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ #define UART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ #define UART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ @@ -280,11 +297,26 @@ #define UART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ #define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ #define UART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ -#define UART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */ +#define UART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART SPI mode only) */ #define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ #define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ #define UART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_INT_RIIC (1 << 16) /* Bit 16: Ring Indicator Input Change Enable */ +# define UART_INT_DSRIC (1 << 17) /* Bit 17: Data Set Ready Input Change Enable */ +# define UART_INT_DCDIC (1 << 18) /* Bit 18: Data Carrier Detect Input Change Interrupt Enable */ +#endif + #define UART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_SR_RI (1 << 20) /* Bit 20: Image of RI Input */ +# define UART_SR_DSR (1 << 21) /* Bit 21: Image of DSR Input */ +# define UART_SR_DCD (1 << 22) /* Bit 22: Image of DCD Input */ +# define UART_SR_CTS (1 << 23) /* Bit 23: Image of CTS Input */ +#endif + #define UART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ /* UART Receiver Holding Register */ @@ -359,6 +391,11 @@ # define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ #define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define UART_MAN_ONE (1 << 29) /* Bit 29: Must Be Set to 1 */ +#endif + #define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ /* USART Write Protect Mode Register (USART only) */ @@ -366,6 +403,7 @@ #define UART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ #define UART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ #define UART_WPMR_WPKEY_MASK (0x00ffffff << UART_WPMR_WPKEY_SHIFT) +# define UART_WPMR_WPKEY (0x00555341 << UART_WPMR_WPKEY_SHIFT) /* USART Write Protect Status Register (USART only) */ diff --git a/arch/arm/src/sam34/chip/sam4l_usart.h b/arch/arm/src/sam34/chip/sam4l_usart.h index f7fb7e3572..feaf4b48c5 100644 --- a/arch/arm/src/sam34/chip/sam4l_usart.h +++ b/arch/arm/src/sam34/chip/sam4l_usart.h @@ -1,5 +1,6 @@ /************************************************************************************************ * arch/arm/src/sam34/chip/sam4l_uart.h + * Universal Synchronous Asynchronous Receiver Transmitter (USART) definitions for the SAM4L * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/sam34/chip/sam4s_memorymap.h b/arch/arm/src/sam34/chip/sam4s_memorymap.h new file mode 100644 index 0000000000..f3f2bce224 --- /dev/null +++ b/arch/arm/src/sam34/chip/sam4s_memorymap.h @@ -0,0 +1,152 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4s_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Address regions */ + +#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ +#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */ +#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ +#define SAM_EXTRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External RAM */ +#define SAM_EXTDEV_BASE 0xa0000000 /* 0xa0000000-0xdfffffff: External device */ +#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */ + +/* Code memory region */ + +#define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x003fffff: Boot Memory */ +#define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */ +#define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */ + /* 0x00c00000-0x1fffffff: Reserved */ +/* Internal SRAM memory region */ + +#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */ + /* 0x24000000-0x3fffffff: Undefined */ + +/* Peripherals address region */ + +#define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ +#define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ +#define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ + /* 0x4000c000-0x4000ffff: Reserved */ +#define SAM_TC_BASE 0x40010000 /* 0x40010000-0x40017fff: Timer Counters */ +# define SAM_TC0_BASE 0x40080000 /* 0x40010000-0x4001003f: Timer Counter 0 */ +# define SAM_TC1_BASE 0x40080040 /* 0x40010040-0x4001007f: Timer Counter 1 */ +# define SAM_TC2_BASE 0x40080080 /* 0x40010080-0x400100bf: Timer Counter 2 */ + /* 0x400100c0-0x40013fff Reserved */ +# define SAM_TC3_BASE 0x40080000 /* 0x40014000-0x4001403f: Timer Counter 3 */ +# define SAM_TC4_BASE 0x40080040 /* 0x40014040-0x4001407f: Timer Counter 4 */ +# define SAM_TC5_BASE 0x40080080 /* 0x40014080-0x400140bf: Timer Counter 5 */ +#define SAM_TWI_BASE 0x40018000 /* 0x40018000-0x4001ffff: Two-Wire Interface */ +# define SAM_TWI0_BASE 0x40018000 /* 0x40018000-0x4001bfff: Two-Wire Interface 0 */ +# define SAM_TWI1_BASE 0x4001c000 /* 0x4001c000-0x4001ffff: Two-Wire Interface 1 */ +#define SAM_PWM_BASE 0x40020000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */ +#define SAM_USART_BASE 0x40024000 /* 0x40024000-0x4002bfff: USART */ +# define SAM_USART0_BASE 0x40024000 /* 0x40024000-0x40023fff: USART0 */ +# define SAM_USART1_BASE 0x40028000 /* 0x40028000-0x4002bfff: USART1 */ + /* 0x4002C000-0x4002ffff: Reserved */ + /* 0x40030000-0x40033fff: Reserved */ +#define SAM_UDP_BASE 0x40034000 /* 0x40034000-0x40037fff: USB 2.0 Device */ +#define SAM_ADC_BASE 0x40038000 /* 0x40038000-0x4003bfff: Analog To Digital Converter */ +#define SAM_DACCBASE 0x400cC000 /* 0x4003c000-0x4003ffff: Digital To Analog Converter */ +#define SAM_ACC_BASE 0x40040000 /* 0x40040000-0x40043fff: Analog Comparator */ +#define SAM_CRCCU_BASE 0x40044000 /* 0x40040000-0x40047fff: CRC Calculation Unit */ + /* 0x40048000-0x400dffff: Reserved */ +#define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System Controller */ + /* 0x400e2600-0x400fffff: Reserved */ + /* 0x40100000-0x4002ffff: Reserved */ +#define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32MB bit-band region */ + /* 0x44000000-0x5fffffff: Reserved */ +/* System Controller Register Blocks: 0x400e0000-0x4007ffff */ + +#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ +#define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ +#define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ +#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */ +#define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ +#define SAM_UART1_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: UART 1 */ +#define SAM_EEFC_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controllers*/ +# define SAM_EEFC0_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 0 */ +# define SAM_EEFC1_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Enhanced Embedded Flash Controller 1 */ +#define SAM_PIO_BASE 0x400e0e00 /* 0x400e0e00-0x400e13ff: Parallel I/O Controllers */ +# define SAM_PIOA_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller A */ +# define SAM_PIOB_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller B */ +# define SAM_PIOC_BASE 0x400e1200 /* 0x400e1200-0x400e13ff: Parallel I/O Controller C */ +#define SAM_RSTC_BASE 0x400e1400 /* 0x400e1400-0x400e140f: Reset Controller */ +#define SAM_SUPC_BASE 0x400e1410 /* 0x400e1410-0x400e142f: Supply Controller */ +#define SAM_RTT_BASE 0x400e1430 /* 0x400e1430-0x400e144f: Real Time Timer */ +#define SAM_WDT_BASE 0x400e1450 /* 0x400e1250-0x400e145f: Watchdog Timer */ +#define SAM_RTC_BASE 0x400e1460 /* 0x400e1460-0x400e148f: Real Time Clock */ +#define SAM_GPBR_BASE 0x400e1490 /* 0x400e1490-0x400e15ff: GPBR */ + /* 0x400e1600-0x4007ffff: Reserved */ +/* External RAM memory region */ + +#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ +# define SAM_EXTCSN_BASE(n) (0x60000000*((n)<<24)) +# define SAM_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */ +# define SAM_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */ +# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ +# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ + /* 0x64000000-0x9fffffff: Reserved */ +/* System memory region */ + +#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ +#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H */ diff --git a/arch/arm/src/sam34/chip/sam4s_vectors.h b/arch/arm/src/sam34/chip/sam4s_vectors.h new file mode 100644 index 0000000000..3dc9bdc386 --- /dev/null +++ b/arch/arm/src/sam34/chip/sam4s_vectors.h @@ -0,0 +1,91 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam42_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ +/* This file is included by sam_vectors.S. It provides the macro VECTOR that + * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h. + * sam_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 35 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 35 + +#else + VECTOR(sam_SUPC, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */ + VECTOR(sam_RSTC, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */ + VECTOR(sam_RTC, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */ + VECTOR(sam_RTT, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */ + VECTOR(sam_WDT, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */ + VECTOR(sam_PMC, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */ + VECTOR(sam_EEFC0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */ + VECTOR(sam_EEFC1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */ + VECTOR(sam_UART0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter 0 */ + VECTOR(sam_UART1, SAM_IRQ_UART1) /* Vector 16+9: Universal Asynchronous Receiver Transmitter 1 */ + VECTOR(sam_SMC, SAM_IRQ_SMC) /* Vector 16+10: Static Memory Controller */ + VECTOR(sam_PIOA, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */ + VECTOR(sam_PIOB, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */ + VECTOR(sam_PIOB, SAM_IRQ_PIOB) /* Vector 16+13: Parallel I/O Controller C */ + VECTOR(sam_USART0, SAM_IRQ_USART0) /* Vector 16+14: USART 0 */ + VECTOR(sam_USART1, SAM_IRQ_USART0) /* Vector 16+15: USART 1 */ + UNUSED(SAM_IRQ_RESERVED_16) /* Vector 16+16: Reserved */ + UNUSED(SAM_IRQ_RESERVED_17) /* Vector 16+17: Reserved */ + VECTOR(sam_HSMCI, SAM_IRQ_HSMCI) /* Vector 16+18: High Speed Multimedia Card Interface */ + VECTOR(sam_TWI0, SAM_IRQ_TWI0) /* Vector 16+19: Two-Wire Interface 0 */ + VECTOR(sam_TWI1, SAM_IRQ_TWI1) /* Vector 16+20: Two-Wire Interface 1 */ + VECTOR(sam_SSC, SAM_IRQ_SSC) /* Vector 16+22: Synchronous Serial Controller */ + VECTOR(sam_TC0, SAM_IRQ_TC0) /* Vector 16+23: Timer Counter 0 */ + VECTOR(sam_TC1, SAM_IRQ_TC1) /* Vector 16+24: Timer Counter 1 */ + VECTOR(sam_TC2, SAM_IRQ_TC2) /* Vector 16+25: Timer Counter 2 */ + VECTOR(sam_TC3, SAM_IRQ_TC3) /* Vector 16+26: Timer Counter 3 */ + VECTOR(sam_TC4, SAM_IRQ_TC4) /* Vector 16+27: Timer Counter 4 */ + VECTOR(sam_TC5, SAM_IRQ_TC5) /* Vector 16+28: Timer Counter 5 */ + VECTOR(sam_ADC, SAM_IRQ_ADC) /* Vector 16+29: Analog To Digital Converter */ + VECTOR(sam_DACC, SAM_IRQ_DACC) /* Vector 16+30: Digital To Analog Converter */ + VECTOR(sam_PWM, SAM_IRQ_PWM) /* Vector 16+31: Pulse Width Modulation */ + VECTOR(sam_CRCCU, SAM_IRQ_CRCCU) /* Vector 16+32: CRC Calculation Unit */ + VECTOR(sam_ACC, SAM_IRQ_ACC) /* Vector 16+33: Analog Comparator */ + VECTOR(sam_UDP, SAM_IRQ_UDP) /* Vector 16+34: USB Device Port */ +#endif diff --git a/arch/arm/src/sam34/chip/sam_chipid.h b/arch/arm/src/sam34/chip/sam_chipid.h index c98130efec..fd5fc977a3 100644 --- a/arch/arm/src/sam34/chip/sam_chipid.h +++ b/arch/arm/src/sam34/chip/sam_chipid.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_chipid.h + * CHIPID Register Definitions for the SAM3U, SAM4S, and SAM4L * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -100,10 +101,11 @@ #define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) # define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ # define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */ +# define CHIPID_CIDR_SRAMSIZ_192KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 192K bytes (SAM4S) */ # define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */ # define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */ # define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */ -# define CHIPID_CIDR_SRAMSIZ_24KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 24K bytes */ +# define CHIPID_CIDR_SRAMSIZ_24KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 24K bytes (SAM4S, SAM4L) */ # define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */ # define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */ # define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */ @@ -142,27 +144,32 @@ # define CHIPID_CIDR_ARCH_SAM3XXE (0x85 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxE Series (144-pin version) */ # define CHIPID_CIDR_ARCH_SAM3XXG (0x86 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxG Series (208/217-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxA Series (48-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4SxA Series (48-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM34xB Series (64-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM4SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM4SxC Series (100-pin version) */ # define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */ # define CHIPID_CIDR_ARCH_SAM3NXA (0x93 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxA Series (48-pin version) */ # define CHIPID_CIDR_ARCH_SAM3NXB (0x94 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxB Series (64-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3NxC (0x95 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxC Series (100-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3NXC (0x99 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxB SAM3SDxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3NXC (0x95 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3DXB (0x99 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxB SAM3SDxB Series (64-pin version) */ # define CHIPID_CIDR_ARCH_SAM3SDXC (0x9a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxC Series (100-pin version) */ # define CHIPID_CIDR_ARCH_SAM5A (0xa5 << CHIPID_CIDR_ARCH_SHIFT) /* SAM5A */ -# define CHIPID_CIDR_ARCH_SAM4L (0xb0 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4Lxx Series */ +# define CHIPID_CIDR_ARCH_SAM4LA (0xb0 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxA Series */ +# define CHIPID_CIDR_ARCH_SAM4LB (0xb1 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxB Series */ +# define CHIPID_CIDR_ARCH_SAM4LC (0xb2 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxC Series */ # define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ #define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ #define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) -# define CHIPID_CIDR_NVPTYP ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ -# define CHIPID_CIDR_NVPTYP FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ -# define CHIPID_CIDR_NVPTYP SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ -# define CHIPID_CIDR_NVPTYP EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ -# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP_ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ +# define CHIPID_CIDR_NVPTYP_FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ +# define CHIPID_CIDR_NVPTYP_SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ +# define CHIPID_CIDR_NVPTYP_EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP_REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ #define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ -/* Chip ID Extension Register */ +/* Chip ID Extension Register (32-bit value for SAM3U and SAM4S) */ #ifdef CONFIG_ARCH_CHIP_SAM4L # define CHIPID_EXID_AES (1 << 0) /* Bit 0: AES Option */ diff --git a/arch/arm/src/sam34/chip/sam_hsmci.h b/arch/arm/src/sam34/chip/sam_hsmci.h index dfee208c31..887d561ca1 100644 --- a/arch/arm/src/sam34/chip/sam_hsmci.h +++ b/arch/arm/src/sam34/chip/sam_hsmci.h @@ -70,13 +70,17 @@ #define SAM_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */ #define SAM_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */ #define SAM_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */ -#define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ +#endif + #define SAM_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */ /* 0x0058-0x00e0: Reserved */ #define SAM_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */ #define SAM_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ /* 0x00ec-0x00fc: Reserved */ - /* 0x0100-0x0124: Reserved */ + /* 0x0100-0x0124: Reserved for PCD registers */ #define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */ /* HSMCI register adresses **************************************************************/ @@ -99,7 +103,11 @@ #define SAM_HSMCI_IER (SAM_MCI_BASE+SAM_HSMCI_IER_OFFSET) #define SAM_HSMCI_IDR (SAM_MCI_BASE+SAM_HSMCI_IDR_OFFSET) #define SAM_HSMCI_IMR (SAM_MCI_BASE+SAM_HSMCI_IMR_OFFSET) -#define SAM_HSMCI_DMA (SAM_MCI_BASE+SAM_HSMCI_DMA_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_HSMCI_DMA (SAM_MCI_BASE+SAM_HSMCI_DMA_OFFSET) +#endif + #define SAM_HSMCI_CFG (SAM_MCI_BASE+SAM_HSMCI_CFG_OFFSET) #define SAM_HSMCI_WPMR (SAM_MCI_BASE+SAM_HSMCI_WPMR_OFFSET) #define SAM_HSMCI_WPSR (SAM_MCI_BASE+SAM_HSMCI_WPSR_OFFSET) @@ -126,8 +134,15 @@ #define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */ #define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */ #define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */ -#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ -#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_MR_PDCMODE (1 << 15) /* Bit 15: PDC-oriented Mode */ +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +# define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) +#endif /* HSMCI Data Timeout Register */ @@ -157,6 +172,8 @@ # define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT) # define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT) +/* HSMCI Argument Register (32-bit value) */ + /* HSMCI Command Register */ #define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */ @@ -200,7 +217,7 @@ # define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ # define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ #define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */ +#define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */ /* HSMCI Block Register */ @@ -224,6 +241,10 @@ # define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT) # define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) +/* HSMCI Response Registers (32-bit data) */ +/* HSMCI Receive Data Registers (32-bit data) */ +/* HSMCI Transmit Data Registers (32-bit data) */ + /* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable * Register, and HSMCI Interrupt Mask Register common bit-field definitions */ @@ -234,9 +255,21 @@ #define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */ #define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */ #define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_INT_ENDRX (1 << 6) /* Bit 6: End of RX Buffer */ +# define HSMCI_INT_ENDTX (1 << 7) /* Bit 7: End of TX Buffer */ +#endif + #define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */ #define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */ #define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define HSMCI_INT_RXBUFF (1 << 14) /* Bit 14: RXBUFF: RX Buffer Full */ +# define HSMCI_INT_TXBUFE (1 << 15) /* Bit 15: TXBUFE: TX Buffer Empty */ +#endif + #define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */ #define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */ #define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */ @@ -245,8 +278,12 @@ #define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */ #define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */ #define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */ -#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ -#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ +# define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ +#endif + #define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */ #define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */ #define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */ @@ -256,11 +293,13 @@ /* HSMCI DMA Configuration Register */ -#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ -#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) -#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ -#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ -#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ +# define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) +# define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ +# define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ +# define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ +#endif /* HSMCI Configuration Register */ @@ -274,13 +313,18 @@ #define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ #define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */ #define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT) +# define HSMCI_WPMR_WP_KEY (0x004d4349 << HSMCI_WPMR_WP_KEY_SHIFT) /* HSMCI Write Protect Status Register */ -#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT) -#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ -#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT) +#define HSMCI_WPSR_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define HSMCI_WPSR_VS_MASK (15 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_NONE (0 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_WRITE (1 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_RESET (2 << HSMCI_WPSR_VS_SHIFT) +# define HSMCI_WPSR_VS_BOTH (3 << HSMCI_WPSR_VS_SHIFT) +#define HSMCI_WPSR_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define HSMCI_WPSR_VSRC_MASK (0xffff << HSMCI_WPSR_VSRC_SHIFT) /**************************************************************************************** * Public Types diff --git a/arch/arm/src/sam34/chip/sam_memorymap.h b/arch/arm/src/sam34/chip/sam_memorymap.h index a1fe603823..05e53ec8ee 100644 --- a/arch/arm/src/sam34/chip/sam_memorymap.h +++ b/arch/arm/src/sam34/chip/sam_memorymap.h @@ -47,6 +47,8 @@ # include "chip/sam3u_memorymap.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_memorymap.h" #else # error Unrecognized SAM architecture #endif diff --git a/arch/arm/src/sam34/chip/sam_pinmap.h b/arch/arm/src/sam34/chip/sam_pinmap.h index 0028cb6bab..74538cdaf1 100644 --- a/arch/arm/src/sam34/chip/sam_pinmap.h +++ b/arch/arm/src/sam34/chip/sam_pinmap.h @@ -47,6 +47,8 @@ # include "chip/sam3u_pinmap.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_pinmap.h" #else # error Unrecognized SAM architecture #endif diff --git a/arch/arm/src/sam34/chip/sam_spi.h b/arch/arm/src/sam34/chip/sam_spi.h index 91720647fd..0704e6d818 100644 --- a/arch/arm/src/sam34/chip/sam_spi.h +++ b/arch/arm/src/sam34/chip/sam_spi.h @@ -67,7 +67,8 @@ /* 0x40-0xe0: Reserved */ #define SAM_SPI_WPCR_OFFSET 0xe4 /* Write Protection Control Register */ #define SAM_SPI_WPSR_OFFSET 0xe8 /* Write Protection Status Register */ - /* 0xec-0xf8: Reserved*/ + /* 0xec-0xfc: Reserved */ + /* 0x100-0x124 Reserved for PDC Registers */ /* SPI register adresses ****************************************************************/ @@ -105,6 +106,10 @@ #define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */ #define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT) +# define SPI_MR_PCS0 (0 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ #define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */ #define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT) @@ -114,6 +119,10 @@ #define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT) #define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT) +# define SPI_RDR_PCS0 (0 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_RDR_PCS1 (1 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_RDR_PCS2 (3 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_RDR_PCS3 (7 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ /* SPI Transmit Data Register */ @@ -121,6 +130,10 @@ #define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT) #define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ #define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT) +# define SPI_TDR_PCS0 (0 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1100 (w/PCSDEC=0) */ +# define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ #define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ /* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register, @@ -131,6 +144,14 @@ #define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */ #define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */ #define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SPI_INT_ENDRX (1 << 4) /* Bit 4: End of RX buffer */ +# define SPI_INT_ENDTX (1 << 5) /* Bit 5: End of TX buffer */ +# define SPI_INT_RXBUFF (1 << 6) /* Bit 6: RX Buffer Full */ +# define SPI_INT_TXBUFE (1 << 7) /* Bit 7: TX Buffer Empty */ +#endif + #define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */ #define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */ #define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */ @@ -163,16 +184,17 @@ /* SPI Write Protection Control Register */ -#define SPI_WPCR_SPIWPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */ -#define SPI_WPCR_SPIWPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */ -#define SPI_WPCR_SPIWPKEY_MASK (0x00ffffff << SPI_WPCR_SPIWPKEY_SHIFT) +#define SPI_WPCR_WPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */ +#define SPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */ +#define SPI_WPCR_WPKEY_MASK (0x00ffffff << SPI_WPCR_WPKEY_SHIFT) +# define SPI_WPCR_WPKEY (0x00535049 << SPI_WPCR_WPKEY_SHIFT) /* SPI Write Protection Status Register */ -#define SPI_WPSR_SPIWPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVS_MASK (7 << SPI_WPSR_SPIWPVS_SHIFT) -#define SPI_WPSR_SPIWPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ -#define SPI_WPSR_SPIWPVSRC_MASK (0xff << SPI_WPSR_SPIWPVSRC_SHIFT) +#define SPI_WPSR_WPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */ +#define SPI_WPSR_WPVS_MASK (7 << SPI_WPSR_WPVS_SHIFT) +#define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ +#define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT) /**************************************************************************************** * Public Types diff --git a/arch/arm/src/sam34/sam_lowputc.c b/arch/arm/src/sam34/sam_lowputc.c index 53fe8fae7a..8add135871 100644 --- a/arch/arm/src/sam34/sam_lowputc.c +++ b/arch/arm/src/sam34/sam_lowputc.c @@ -87,7 +87,7 @@ /* Is there a serial console? It could be on the UART, or USARTn */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -145,12 +145,12 @@ /* Select USART parameters for the selected console */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) -# define SAM_CONSOLE_BASE SAM_UART_BASE -# define SAM_CONSOLE_BAUD CONFIG_UART_BAUD -# define SAM_CONSOLE_BITS CONFIG_UART_BITS -# define SAM_CONSOLE_PARITY CONFIG_UART_PARITY -# define SAM_CONSOLE_2STOP CONFIG_UART_2STOP +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define SAM_CONSOLE_BASE SAM_UART0_BASE +# define SAM_CONSOLE_BAUD CONFIG_UART0_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART0_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART0_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART0_2STOP #elif defined(CONFIG_USART0_SERIAL_CONSOLE) # define SAM_CONSOLE_BASE SAM_USART0_BASE # define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD @@ -269,7 +269,7 @@ void sam_lowsetup(void) { /* Enable clocking for all selected UART/USARTs */ -#ifdef CONFIG_SAM34_UART +#ifdef CONFIG_SAM34_UART0 sam_uart_enableclk(); #endif #ifdef CONFIG_SAM34_USART0 @@ -287,7 +287,7 @@ void sam_lowsetup(void) /* Configure UART pins for all selected UART/USARTs */ -#ifdef CONFIG_SAM34_UART +#ifdef CONFIG_SAM34_UART0 (void)sam_configgpio(GPIO_UART_RXD); (void)sam_configgpio(GPIO_UART_TXD); #endif diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index f2289d356d..5133ec25f1 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -93,7 +93,7 @@ /* Is there a USART/USART enabled? */ -#if !defined(CONFIG_SAM34_UART) && !defined(CONFIG_SAM34_USART0) && \ +#if !defined(CONFIG_SAM34_UART0) && !defined(CONFIG_SAM34_USART0) && \ !defined(CONFIG_SAM34_USART1) && !defined(CONFIG_SAM34_USART2) && \ !defined(CONFIG_SAM34_USART3) # error "No USARTs enabled" @@ -106,39 +106,39 @@ /* Is there a serial console? */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3) -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #else # warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" -# undef CONFIG_UART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -154,7 +154,7 @@ /* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? */ -#if defined(CONFIG_UART_SERIAL_CONSOLE) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) # define CONSOLE_DEV g_uartport /* UART=console */ # define TTYS0_DEV g_uartport /* UART=ttyS0 */ # ifdef CONFIG_SAM34_USART0 @@ -236,7 +236,7 @@ #elif defined(CONFIG_USART0_SERIAL_CONSOLE) # define CONSOLE_DEV g_usart0port /* USART0=console */ # define TTYS0_DEV g_usart0port /* USART0=ttyS0 */ -# ifdef CONFIG_SAM34_UART +# ifdef CONFIG_SAM34_UART0 # define TTYS1_DEV g_uartport /* USART0=ttyS0;UART=ttyS1 */ # ifdef CONFIG_SAM34_USART1 # define TTYS2_DEV g_usart1port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2 */ @@ -315,7 +315,7 @@ #elif defined(CONFIG_USART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_usart1port /* USART1=console */ # define TTYS0_DEV g_usart1port /* USART1=ttyS0 */ -# ifdef CONFIG_SAM34_UART +# ifdef CONFIG_SAM34_UART0 # define TTYS1_DEV g_uartport /* USART1=ttyS0;UART=ttyS1 */ # ifdef CONFIG_SAM34_USART0 # define TTYS2_DEV g_usart0port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2 */ @@ -394,7 +394,7 @@ #elif defined(CONFIG_USART2_SERIAL_CONSOLE) # define CONSOLE_DEV g_usart2port /* USART2=console */ # define TTYS0_DEV g_usart2port /* USART2=ttyS0 */ -# ifdef CONFIG_SAM34_UART +# ifdef CONFIG_SAM34_UART0 # define TTYS1_DEV g_uartport /* USART2=ttyS0;UART=ttyS1 */ # ifdef CONFIG_SAM34_USART0 # define TTYS2_DEV g_usart0port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2 */ @@ -473,7 +473,7 @@ #elif defined(CONFIG_USART3_SERIAL_CONSOLE) # define CONSOLE_DEV g_usart3port /* USART3=console */ # define TTYS0_DEV g_usart3port /* USART3=ttyS0 */ -# ifdef CONFIG_SAM34_UART +# ifdef CONFIG_SAM34_UART0 # define TTYS1_DEV g_uartport /* USART3=ttyS0;UART=ttyS1 */ # ifdef CONFIG_SAM34_USART0 # define TTYS2_DEV g_usart0port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2 */ @@ -624,9 +624,9 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ -#ifdef CONFIG_SAM34_UART -static char g_uartrxbuffer[CONFIG_UART_RXBUFSIZE]; -static char g_uarttxbuffer[CONFIG_UART_TXBUFSIZE]; +#ifdef CONFIG_SAM34_UART0 +static char g_uartrxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uarttxbuffer[CONFIG_UART0_TXBUFSIZE]; #endif #ifdef CONFIG_SAM34_USART0 static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; @@ -647,27 +647,27 @@ static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; /* This describes the state of the UART port. */ -#ifdef CONFIG_SAM34_UART +#ifdef CONFIG_SAM34_UART0 static struct up_dev_s g_uartpriv = { - .usartbase = SAM_UART_BASE, - .baud = CONFIG_UART_BAUD, + .usartbase = SAM_UART0_BASE, + .baud = CONFIG_UART0_BAUD, .irq = SAM_IRQ_UART, - .parity = CONFIG_UART_PARITY, - .bits = CONFIG_UART_BITS, - .stopbits2 = CONFIG_UART_2STOP, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, }; static uart_dev_t g_uartport = { .recv = { - .size = CONFIG_UART_RXBUFSIZE, + .size = CONFIG_UART0_RXBUFSIZE, .buffer = g_uartrxbuffer, }, .xmit = { - .size = CONFIG_UART_TXBUFSIZE, + .size = CONFIG_UART0_TXBUFSIZE, .buffer = g_uarttxbuffer, }, .ops = &g_uart_ops, @@ -913,7 +913,7 @@ static int up_setup(struct uart_dev_s *dev) regval |= UART_MR_CHRL_7BITS; /* 7 bits */ } #ifdef HAVE_USART -#ifdef CONFIG_SAM34_UART +#ifdef CONFIG_SAM34_UART0 /* UART does not support 9bit mode */ else if (priv->bits == 9 && priv->usartbase != SAM_UART_BASE) @@ -1067,7 +1067,7 @@ static int up_interrupt(int irq, void *context) int passes; bool handled; -#ifdef CONFIG_SAM34_UART +#ifdef CONFIG_SAM34_UART0 if (g_uartpriv.irq == irq) { dev = &g_uartport; diff --git a/configs/sam3u-ek/README.txt b/configs/sam3u-ek/README.txt index fbda5d92c7..4f176929bd 100644 --- a/configs/sam3u-ek/README.txt +++ b/configs/sam3u-ek/README.txt @@ -317,7 +317,7 @@ SAM3U-EK-specific Configuration Options CONFIG_SAM34_HSMCI CONFIG_SAM34_NAND CONFIG_SAM34_SPI - CONFIG_SAM34_UART + CONFIG_SAM34_UART0 CONFIG_SAM34_USART0 CONFIG_SAM34_USART1 CONFIG_SAM34_USART2 diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index 82bb5d0219..d2f4cc23be 100644 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -112,7 +112,7 @@ CONFIG_ARCH_CHIP_SAM3U=y # CONFIG_SAM34_DMA is not set # CONFIG_SAM34_NAND is not set # CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set @@ -297,21 +297,21 @@ CONFIG_SDIO_BLOCKSETUP=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index ef2475c1bb..de9ba69355 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -80,6 +80,7 @@ CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="sam34" # CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARCH_HAVE_FPU is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set @@ -93,29 +94,55 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # -# AT91SAM3/SAM4 Configuration Options +# AT91SAM3/4 Configuration Options # CONFIG_ARCH_CHIP_AT91SAM3U4E=y +# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S16C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S8B is not set CONFIG_ARCH_CHIP_SAM3U=y +# CONFIG_ARCH_CHIP_SAM4L is not set +# CONFIG_ARCH_CHIP_SAM4S is not set # -# AT91SAM3 Peripheral Support +# AT91SAM3/4 Peripheral Support # -# CONFIG_SAM34_DMA is not set -# CONFIG_SAM34_NAND is not set -# CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +# CONFIG_SAM34_SPI is not set +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set # CONFIG_SAM34_USART3 is not set +# CONFIG_SAM34_NAND is not set +# CONFIG_SAM34_DMA is not set +# CONFIG_SAM34_WDT is not set +# CONFIG_SAM34_HSMCI is not set # -# AT91SAM3 UART Configuration +# AT91SAM3/4 USART Configuration # # -# AT91SAM3 GPIO Interrupt Configuration +# AT91SAM3/4 GPIO Interrupt Configuration # # CONFIG_GPIOA_IRQ is not set # CONFIG_GPIOB_IRQ is not set @@ -137,7 +164,8 @@ CONFIG_ARCH_IRQPRIO=y CONFIG_ARCH_HAVE_VFORK=y CONFIG_ARCH_STACKDUMP=y # CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +# CONFIG_ARCH_RAMFUNCS is not set CONFIG_ARCH_HAVE_RAMVECTORS=y # CONFIG_ARCH_RAMVECTORS is not set @@ -273,21 +301,25 @@ CONFIG_DEV_NULL=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set @@ -556,6 +588,7 @@ CONFIG_NSH_LIBRARY=y CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 +CONFIG_NSH_MAXARGUMENTS=6 CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLEBG is not set diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 7329bd2a40..d1cf4ebca6 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_SAM3U=y # CONFIG_SAM34_DMA is not set # CONFIG_SAM34_NAND is not set # CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set @@ -299,21 +299,21 @@ CONFIG_LCD_LANDSCAPE=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set diff --git a/configs/sam3u-ek/ostest/defconfig b/configs/sam3u-ek/ostest/defconfig index 9152a05289..622ece5de8 100644 --- a/configs/sam3u-ek/ostest/defconfig +++ b/configs/sam3u-ek/ostest/defconfig @@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_SAM3U=y # CONFIG_SAM34_DMA is not set # CONFIG_SAM34_NAND is not set # CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set @@ -272,20 +272,20 @@ CONFIG_DEV_NULL=y CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set diff --git a/configs/sam3u-ek/touchscreen/defconfig b/configs/sam3u-ek/touchscreen/defconfig index f2d933864f..bc2e2286cd 100644 --- a/configs/sam3u-ek/touchscreen/defconfig +++ b/configs/sam3u-ek/touchscreen/defconfig @@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_SAM3U=y # CONFIG_SAM34_DMA is not set # CONFIG_SAM34_NAND is not set # CONFIG_SAM34_HSMCI is not set -CONFIG_SAM34_UART=y +CONFIG_SAM34_UART0=y # CONFIG_SAM34_USART0 is not set # CONFIG_SAM34_USART1 is not set # CONFIG_SAM34_USART2 is not set @@ -316,21 +316,21 @@ CONFIG_LCD_PORTRAIT=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set -CONFIG_ARCH_HAVE_UART=y +CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y -CONFIG_UART_SERIAL_CONSOLE=y +CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set # -# UART Configuration +# UART0 Configuration # -CONFIG_UART_RXBUFSIZE=256 -CONFIG_UART_TXBUFSIZE=256 -CONFIG_UART_BAUD=115200 -CONFIG_UART_BITS=8 -CONFIG_UART_PARITY=0 -CONFIG_UART_2STOP=0 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_WIRELESS is not set