arch/arm/src/stm32/stm32_oneshot.c: Corrects error introduced by commit 2fcf682316
also affect stm32_oneshot.c (I noticed that ps on my STM32F4 did not show any CPU load in nuttx-7.27 onward).
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parent
5bfa7a8df4
commit
bb23ac43ce
@ -100,9 +100,9 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg)
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*/
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STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0);
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STM32_TIM_DISABLEINT(oneshot->tch, 0);
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STM32_TIM_DISABLEINT(oneshot->tch, ATIM_DIER_UIE);
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STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED);
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STM32_TIM_ACKINT(oneshot->tch, 0);
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STM32_TIM_ACKINT(oneshot->tch, ATIM_SR_UIF);
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/* The timer is no longer running */
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@ -326,8 +326,8 @@ int stm32_oneshot_start(struct stm32_oneshot_s *oneshot,
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STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE);
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STM32_TIM_ACKINT(oneshot->tch, 0);
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STM32_TIM_ENABLEINT(oneshot->tch, 0);
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STM32_TIM_ACKINT(oneshot->tch, ATIM_SR_UIF);
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STM32_TIM_ENABLEINT(oneshot->tch, ATIM_DIER_UIE);
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/* Enable interrupts. We should get the callback when the interrupt
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* occurs.
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@ -118,12 +118,12 @@ static void up_lcddispcontrol(bool on)
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if (on)
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{
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stm32_gpiowrite(GPIO_MEMLCD_DISP, 1);
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STM32_TIM_ENABLEINT(tim, ATIM_SR_UIF);
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STM32_TIM_ENABLEINT(tim, ATIM_DIER_UIE);
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}
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else
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{
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stm32_gpiowrite(GPIO_MEMLCD_DISP, 0);
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STM32_TIM_DISABLEINT(tim, ATIM_SR_UIF);
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STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE);
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}
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}
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