arch/arm/src/stm32/stm32_oneshot.c: Corrects error introduced by commit 2fcf682316 also affect stm32_oneshot.c (I noticed that ps on my STM32F4 did not show any CPU load in nuttx-7.27 onward).

This commit is contained in:
Maximilian Kriegleder 2019-03-22 07:43:15 -06:00 committed by Gregory Nutt
parent 5bfa7a8df4
commit bb23ac43ce
2 changed files with 6 additions and 6 deletions

View File

@ -100,9 +100,9 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg)
*/
STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0);
STM32_TIM_DISABLEINT(oneshot->tch, 0);
STM32_TIM_DISABLEINT(oneshot->tch, ATIM_DIER_UIE);
STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED);
STM32_TIM_ACKINT(oneshot->tch, 0);
STM32_TIM_ACKINT(oneshot->tch, ATIM_SR_UIF);
/* The timer is no longer running */
@ -326,8 +326,8 @@ int stm32_oneshot_start(struct stm32_oneshot_s *oneshot,
STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE);
STM32_TIM_ACKINT(oneshot->tch, 0);
STM32_TIM_ENABLEINT(oneshot->tch, 0);
STM32_TIM_ACKINT(oneshot->tch, ATIM_SR_UIF);
STM32_TIM_ENABLEINT(oneshot->tch, ATIM_DIER_UIE);
/* Enable interrupts. We should get the callback when the interrupt
* occurs.

View File

@ -118,12 +118,12 @@ static void up_lcddispcontrol(bool on)
if (on)
{
stm32_gpiowrite(GPIO_MEMLCD_DISP, 1);
STM32_TIM_ENABLEINT(tim, ATIM_SR_UIF);
STM32_TIM_ENABLEINT(tim, ATIM_DIER_UIE);
}
else
{
stm32_gpiowrite(GPIO_MEMLCD_DISP, 0);
STM32_TIM_DISABLEINT(tim, ATIM_SR_UIF);
STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE);
}
}