cache: add up_get_xcache_linesize() support

Signed-off-by: ligd <liguiding1@xiaomi.com>

arch/arm/src/arm/arm_cache.S

@@ -72,6 +72,22 @@
  * the corresponding I-Cache lines.
  */
 
+	.globl	up_get_dcache_linesize
+	.type   up_get_dcache_linesize, function
+
+up_get_dcache_linesize:
+	mov		r0, #CACHE_DLINESIZE
+	mov		pc, lr
+	.size   up_get_dcache_linesize, .-up_get_dcache_linesize
+
+	.globl	up_get_icache_linesize
+	.type   up_get_icache_linesize, function
+
+up_get_icache_linesize:
+	mov		r0, #CACHE_DLINESIZE
+	mov		pc, lr
+	.size   up_get_icache_linesize, .-up_get_icache_linesize
+
 	.globl	up_coherent_dcache
 	.type	up_coherent_dcache, function
 

arch/arm/src/armv7-a/arm_cache.c

@@ -25,17 +25,71 @@
 #include <nuttx/config.h>
 #include <nuttx/cache.h>
 #include <nuttx/irq.h>
+#include <sys/param.h>
 
 #include "cp15_cacheops.h"
 #include "barriers.h"
 #include "l2cc.h"
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_ICACHE) || defined(CONFIG_ARCH_DCACHE)
+
+/****************************************************************************
+ * Name: up_get_cache_linesize
+ *
+ * Description:
+ *   Get cache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+static size_t up_get_cache_linesize(void)
+{
+  static uint32_t clsize;
+
+  if (clsize == 0)
+    {
+      clsize = MAX(cp15_cache_linesize(), l2cc_get_linesize());
+    }
+
+  return clsize;
+}
+
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
 
 #ifdef CONFIG_ARCH_ICACHE
 
+/****************************************************************************
+ * Name: up_get_icache_linesize
+ *
+ * Description:
+ *   Get icache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+size_t up_get_icache_linesize(void)
+{
+  return up_get_cache_linesize();
+}
+
 /****************************************************************************
  * Name: up_invalidate_icache_all
  *
@@ -119,6 +173,25 @@ void up_disable_icache(void)
 
 #ifdef CONFIG_ARCH_DCACHE
 
+/****************************************************************************
+ * Name: up_get_dcache_linesize
+ *
+ * Description:
+ *   Get dcache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+size_t up_get_dcache_linesize(void)
+{
+  return up_get_cache_linesize();
+}
+
 /****************************************************************************
  * Name: up_invalidate_dcache
  *

arch/arm/src/armv7-a/arm_l2cc_pl310.c

@@ -396,6 +396,25 @@ void arm_l2ccinitialize(void)
         PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
 }
 
+/****************************************************************************
+ * Name: l2cc_get_linesize
+ *
+ * Description:
+ *    Get L2CC-P310 L2 cache linesize
+ *
+ * Input Parameters:
+ *    None
+ *
+ * Returned Value:
+ *    L2 cache linesize
+ *
+ ****************************************************************************/
+
+uint32_t l2cc_get_linesize(void)
+{
+  return PL310_CACHE_LINE_SIZE;
+}
+
 /****************************************************************************
  * Name: l2cc_enable
  *

arch/arm/src/armv7-a/cp15_cacheops.c

@@ -269,3 +269,8 @@ uint32_t cp15_cache_size(void)
 
   return sets * ways * line;
 }
+
+uint32_t cp15_cache_linesize(void)
+{
+  return cp15_cache_get_info(NULL, NULL);
+}

arch/arm/src/armv7-a/cp15_cacheops.h

@@ -1106,6 +1106,22 @@ void cp15_flush_dcache_all(void);
 
 uint32_t cp15_cache_size(void);
 
+/****************************************************************************
+ * Name: cp15_cache_linesize
+ *
+ * Description:
+ *   Get cp15 cache linesize in byte
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache linesize in byte
+ *
+ ****************************************************************************/
+
+uint32_t cp15_cache_linesize(void);
+
 #undef EXTERN
 #ifdef __cplusplus
 }

arch/arm/src/armv7-a/l2cc.h

@@ -70,6 +70,22 @@ extern "C"
 void arm_l2ccinitialize(void);
 #endif
 
+/****************************************************************************
+ * Name: l2cc_get_linesize
+ *
+ * Description:
+ *    Get L2 cache linesize
+ *
+ * Input Parameters:
+ *    None
+ *
+ * Returned Value:
+ *    L2 cache linesize
+ *
+ ****************************************************************************/
+
+uint32_t l2cc_get_linesize(void);
+
 /****************************************************************************
  * Name: l2cc_enable
  *
@@ -229,6 +245,7 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
    * compilation in one place.
    */
 
+#  define l2cc_get_linesize() 0
 #  define l2cc_enable()
 #  define l2cc_disable()
 #  define l2cc_sync()

arch/arm/src/armv7-m/arm_cache.c

@@ -100,10 +100,68 @@ static inline uint32_t arm_clz(unsigned int value)
 }
 #endif
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_get_cache_linesize
+ *
+ * Description:
+ *   Get cache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_ARMV7M_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
+static size_t up_get_cache_linesize(void)
+{
+  static uint32_t clsize;
+
+  if (clsize == 0)
+    {
+      uint32_t ccsidr;
+      uint32_t sshift;
+
+      ccsidr = getreg32(NVIC_CCSIDR);
+      sshift = CCSIDR_LSSHIFT(ccsidr) + 4;   /* log2(cache-line-size-in-bytes) */
+      clsize = 1 << sshift;
+    }
+
+  return clsize;
+}
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: up_get_icache_linesize
+ *
+ * Description:
+ *   Get icache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV7M_ICACHE
+size_t up_get_icache_linesize(void)
+{
+  return up_get_cache_linesize();
+}
+#endif
+
 /****************************************************************************
  * Name: up_enable_icache
  *
@@ -196,20 +254,10 @@ void up_disable_icache(void)
 #ifdef CONFIG_ARMV7M_ICACHE
 void up_invalidate_icache(uintptr_t start, uintptr_t end)
 {
-  uint32_t ccsidr;
-  uint32_t sshift;
-  uint32_t ssize;
+  uint32_t ssize = up_get_icache_linesize();
 
-  /* Get the characteristics of the I-Cache */
-
-  ccsidr = getreg32(NVIC_CCSIDR);
-  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;   /* log2(cache-line-size-in-bytes) */
-
-  /* Invalidate the I-Cache containing this range of addresses */
-
-  ssize  = (1 << sshift);
-
-  /* Round down the start address to the nearest cache line boundary.
+  /* Invalidate the I-Cache containing this range of addresses.
+   * Round down the start address to the nearest cache line boundary.
    *
    *   sshift = 5      : Offset to the beginning of the set field
    *   (ssize - 1)  = 0x007f : Mask of the set field
@@ -279,6 +327,27 @@ void up_invalidate_icache_all(void)
 }
 #endif
 
+/****************************************************************************
+ * Name: up_get_dcache_linesize
+ *
+ * Description:
+ *   Get dcache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV7M_DCACHE
+size_t up_get_dcache_linesize(void)
+{
+  return up_get_cache_linesize();
+}
+#endif
+
 /****************************************************************************
  * Name: up_enable_dcache
  *
@@ -459,20 +528,10 @@ void up_disable_dcache(void)
 #ifdef CONFIG_ARMV7M_DCACHE
 void up_invalidate_dcache(uintptr_t start, uintptr_t end)
 {
-  uint32_t ccsidr;
-  uint32_t sshift;
-  uint32_t ssize;
+  uint32_t ssize = up_get_dcache_linesize();
 
-  /* Get the characteristics of the D-Cache */
-
-  ccsidr = getreg32(NVIC_CCSIDR);
-  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;   /* log2(cache-line-size-in-bytes) */
-
-  /* Invalidate the D-Cache containing this range of addresses */
-
-  ssize  = (1 << sshift);
-
-  /* Round down the start address to the nearest cache line boundary.
+  /* Invalidate the D-Cache containing this range of addresses
+   * Round down the start address to the nearest cache line boundary.
    *
    *   sshift = 5      : Offset to the beginning of the set field
    *   (ssize - 1)  = 0x007f : Mask of the set field

arch/arm/src/armv7-r/arm_cache.c

@@ -25,17 +25,71 @@
 #include <nuttx/config.h>
 #include <nuttx/cache.h>
 #include <nuttx/irq.h>
+#include <sys/param.h>
 
 #include "cp15_cacheops.h"
 #include "barriers.h"
 #include "l2cc.h"
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_ICACHE) || defined(CONFIG_ARCH_DCACHE)
+
+/****************************************************************************
+ * Name: up_get_cache_linesize
+ *
+ * Description:
+ *   Get cache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+static size_t up_get_cache_linesize(void)
+{
+  static uint32_t clsize;
+
+  if (clsize == 0)
+    {
+      clsize = MAX(cp15_cache_linesize(), l2cc_get_linesize());
+    }
+
+  return clsize;
+}
+
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
 
 #ifdef CONFIG_ARCH_ICACHE
 
+/****************************************************************************
+ * Name: up_get_icache_linesize
+ *
+ * Description:
+ *   Get icache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+size_t up_get_icache_linesize(void)
+{
+  return up_get_cache_linesize();
+}
+
 /****************************************************************************
  * Name: up_invalidate_icache_all
  *
@@ -119,6 +173,25 @@ void up_disable_icache(void)
 
 #ifdef CONFIG_ARCH_DCACHE
 
+/****************************************************************************
+ * Name: up_get_dcache_linesize
+ *
+ * Description:
+ *   Get dcache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+size_t up_get_dcache_linesize(void)
+{
+  return up_get_cache_linesize();
+}
+
 /****************************************************************************
  * Name: up_invalidate_dcache
  *

arch/arm/src/armv7-r/arm_l2cc_pl310.c

@@ -396,6 +396,25 @@ void arm_l2ccinitialize(void)
           PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
 }
 
+/****************************************************************************
+ * Name: l2cc_get_linesize
+ *
+ * Description:
+ *    Get L2CC-P310 L2 cache linesize
+ *
+ * Input Parameters:
+ *    None
+ *
+ * Returned Value:
+ *    L2 cache linesize
+ *
+ ****************************************************************************/
+
+uint32_t l2cc_get_linesize(void)
+{
+  return PL310_CACHE_LINE_SIZE;
+}
+
 /****************************************************************************
  * Name: l2cc_enable
  *

arch/arm/src/armv7-r/cp15_cacheops.c

@@ -269,3 +269,8 @@ uint32_t cp15_cache_size(void)
 
   return sets * ways * line;
 }
+
+uint32_t cp15_cache_linesize(void)
+{
+  return cp15_cache_get_info(NULL, NULL);
+}

arch/arm/src/armv7-r/cp15_cacheops.h

@@ -1113,6 +1113,22 @@ void cp15_flush_dcache_all(void);
 
 uint32_t cp15_cache_size(void);
 
+/****************************************************************************
+ * Name: cp15_cache_linesize
+ *
+ * Description:
+ *   Get cp15 cache linesize in byte
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache linesize in byte
+ *
+ ****************************************************************************/
+
+uint32_t cp15_cache_linesize(void);
+
 #undef EXTERN
 #ifdef __cplusplus
 }

arch/arm/src/armv7-r/l2cc.h

@@ -70,6 +70,22 @@ extern "C"
 void arm_l2ccinitialize(void);
 #endif
 
+/****************************************************************************
+ * Name: l2cc_get_linesize
+ *
+ * Description:
+ *    Get L2 cache linesize
+ *
+ * Input Parameters:
+ *    None
+ *
+ * Returned Value:
+ *    L2 cache linesize
+ *
+ ****************************************************************************/
+
+uint32_t l2cc_get_linesize(void);
+
 /****************************************************************************
  * Name: l2cc_enable
  *
@@ -229,6 +245,7 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
    * compilation in one place.
    */
 
+#  define l2cc_get_linesize() 0
 #  define l2cc_enable()
 #  define l2cc_disable()
 #  define l2cc_sync()

arch/arm/src/armv8-m/arm_cache.c

@@ -100,10 +100,68 @@ static inline uint32_t arm_clz(unsigned int value)
 }
 #endif
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_get_cache_linesize
+ *
+ * Description:
+ *   Get cache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_ARMV8M_ICACHE) || defined(CONFIG_ARMV8M_DCACHE)
+static size_t up_get_cache_linesize(void)
+{
+  static uint32_t clsize;
+
+  if (clsize == 0)
+    {
+      uint32_t ccsidr;
+      uint32_t sshift;
+
+      ccsidr = getreg32(NVIC_CCSIDR);
+      sshift = CCSIDR_LSSHIFT(ccsidr) + 4;   /* log2(cache-line-size-in-bytes) */
+      clsize = 1 << sshift;
+    }
+
+  return clsize;
+}
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: up_get_icache_linesize
+ *
+ * Description:
+ *   Get icache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV8M_ICACHE
+size_t up_get_icache_linesize(void)
+{
+  return up_get_cache_linesize();
+}
+#endif
+
 /****************************************************************************
  * Name: up_enable_icache
  *
@@ -196,20 +254,10 @@ void up_disable_icache(void)
 #ifdef CONFIG_ARMV8M_ICACHE
 void up_invalidate_icache(uintptr_t start, uintptr_t end)
 {
-  uint32_t ccsidr;
-  uint32_t sshift;
-  uint32_t ssize;
+  uint32_t ssize = up_get_icache_linesize();
 
-  /* Get the characteristics of the I-Cache */
-
-  ccsidr = getreg32(NVIC_CCSIDR);
-  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;   /* log2(cache-line-size-in-bytes) */
-
-  /* Invalidate the I-Cache containing this range of addresses */
-
-  ssize  = (1 << sshift);
-
-  /* Round down the start address to the nearest cache line boundary.
+  /* Invalidate the I-Cache containing this range of addresses.
+   * Round down the start address to the nearest cache line boundary.
    *
    *   sshift = 5      : Offset to the beginning of the set field
    *   (ssize - 1)  = 0x007f : Mask of the set field
@@ -279,6 +327,27 @@ void up_invalidate_icache_all(void)
 }
 #endif
 
+/****************************************************************************
+ * Name: up_get_dcache_linesize
+ *
+ * Description:
+ *   Get dcache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV8M_DCACHE
+size_t up_get_dcache_linesize(void)
+{
+  return up_get_cache_linesize();
+}
+#endif
+
 /****************************************************************************
  * Name: up_enable_dcache
  *
@@ -459,20 +528,10 @@ void up_disable_dcache(void)
 #ifdef CONFIG_ARMV8M_DCACHE
 void up_invalidate_dcache(uintptr_t start, uintptr_t end)
 {
-  uint32_t ccsidr;
-  uint32_t sshift;
-  uint32_t ssize;
+  uint32_t ssize = up_get_dcache_linesize();
 
-  /* Get the characteristics of the D-Cache */
-
-  ccsidr = getreg32(NVIC_CCSIDR);
-  sshift = CCSIDR_LSSHIFT(ccsidr) + 4;   /* log2(cache-line-size-in-bytes) */
-
-  /* Invalidate the D-Cache containing this range of addresses */
-
-  ssize  = (1 << sshift);
-
-  /* Round down the start address to the nearest cache line boundary.
+  /* Invalidate the D-Cache containing this range of addresses
+   * Round down the start address to the nearest cache line boundary.
    *
    *   sshift = 5      : Offset to the beginning of the set field
    *   (ssize - 1)  = 0x007f : Mask of the set field

arch/arm64/src/common/arm64_cache.c

@@ -266,6 +266,25 @@ static inline int arm64_dcache_all(int op)
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: up_get_icache_linesize
+ *
+ * Description:
+ *   Get icache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+size_t up_get_icache_linesize(void)
+{
+  return g_dcache_line_size;
+}
+
 /****************************************************************************
  * Name: up_invalidate_dcache
  *
@@ -335,6 +354,25 @@ void up_invalidate_icache_all(void)
   __ic_ialluis();
 }
 
+/****************************************************************************
+ * Name: up_get_dcache_linesize
+ *
+ * Description:
+ *   Get dcache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+size_t up_get_dcache_linesize(void)
+{
+  return g_dcache_line_size;
+}
+
 /****************************************************************************
  * Name: up_clean_dcache
  *

arch/xtensa/src/common/xtensa_cache.c

@@ -40,6 +40,27 @@
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: up_get_icache_linesize
+ *
+ * Description:
+ *   Get icache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_XTENSA_ICACHE
+size_t up_get_icache_linesize(void)
+{
+  return XCHAL_ICACHE_LINESIZE;
+}
+#endif
+
 /****************************************************************************
  * Name: up_enable_icache
  *
@@ -245,6 +266,27 @@ void up_unlock_icache_all(void)
 }
 #endif
 
+/****************************************************************************
+ * Name: up_get_dcache_linesize
+ *
+ * Description:
+ *   Get dcache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_XTENSA_DCACHE
+size_t up_get_dcache_linesize(void)
+{
+  return XCHAL_DCACHE_LINESIZE;
+}
+#endif
+
 /****************************************************************************
  * Name: up_enable_dcache
  *

include/nuttx/cache.h

@@ -48,6 +48,26 @@ extern "C"
  * Public Function Prototypes
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: up_get_icache_linesize
+ *
+ * Description:
+ *   Get icache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ICACHE
+size_t up_get_icache_linesize(void);
+#else
+#  define up_get_icache_linesize() 0
+#endif
+
 /****************************************************************************
  * Name: up_enable_icache
  *
@@ -197,6 +217,26 @@ void up_unlock_icache_all(void);
 #  define up_unlock_icache_all()
 #endif
 
+/****************************************************************************
+ * Name: up_get_dcache_linesize
+ *
+ * Description:
+ *   Get dcache linesize
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Cache line size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_DCACHE
+size_t up_get_dcache_linesize(void);
+#else
+#  define up_get_dcache_linesize() 0
+#endif
+
 /****************************************************************************
  * Name: up_enable_dcache
  *