SAMV7 MAN: Flesh out interrupt logic; add RX message handling logic
This commit is contained in:
Gregory Nutt
parent
62a9aed53a
commit
bb32aa8d24
@ -640,20 +640,84 @@
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#define MAILBOX_ADDRESS(a) ((uint32_t)(a) & 0x0000fffc)
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/* Interrupts ***************************************************************/
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/* Common interrupts */
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#define MCAN_COMMON_INTS (0) /* To be provided */
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/* Mode-independent RX-related interrupts */
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#define MCAN_RXINTS (0) /* To be provided */
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/* Mode-independent TX-related interrupts
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/* Common interrupts
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*
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* MCAN_INT_TC - Transmission Completed
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* MCAN_INT_TSW - Timestamp Wraparound
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* MCAN_INT_MRAF - Message RAM Access Failure
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* MCAN_INT_TOO - Timeout Occurred
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* MCAN_INT_ELO - Error Logging Overflow
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* MCAN_INT_EP - Error Passive
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* MCAN_INT_EW - Warning Status
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* MCAN_INT_BO - Bus_Off Status
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* MCAN_INT_WDI - Watchdog Interrupt
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*/
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#define MCAN_TXINTERRUPTS MCAN_INT_TC
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#define MCAN_CMNERR_INTS (MCAN_INT_MRAF | MCAN_INT_TOO | MCAN_INT_EP | \
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MCAN_INT_BO | MCAN_INT_WDI)
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#define MCAN_COMMON_INTS MCAN_CMNERR_INTS
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/* RXFIFO mode interrupts
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*
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* MCAN_INT_RF0N - Receive FIFO 0 New Message
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* MCAN_INT_RF0W - Receive FIFO 0 Watermark Reached
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* MCAN_INT_RF0F - Receive FIFO 0 Full
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* MCAN_INT_RF0L - Receive FIFO 0 Message Lost
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* MCAN_INT_RF1N - Receive FIFO 1 New Message
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* MCAN_INT_RF1W - Receive FIFO 1 Watermark Reached
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* MCAN_INT_RF1F - Receive FIFO 1 Full
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* MCAN_INT_RF1L - Receive FIFO 1 Message Lost
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* MCAN_INT_HPM - High Priority Message Received
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*
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* Dedicated RX Buffer mode interrupts
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*
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* MCAN_INT_DRX - Message stored to Dedicated Receive Buffer
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*
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* Mode-independent RX-related interrupts
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*
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* MCAN_INT_CRCE - Receive CRC Error
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* MCAN_INT_FOE - Format Error
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* MCAN_INT_STE - Stuff Error
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*/
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#define MCAN_RXCOMMON_INTS (MCAN_INT_CRCE | MCAN_INT_FOE | MCAN_INT_STE)
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#define MCAN_RXFIFO0_INTS (MCAN_INT_RF0N | MCAN_INT_RF0W | MCAN_INT_RF0L | \
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MCAN_INT_RF0L)
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#define MCAN_RXFIFO1_INTS (MCAN_INT_RF1N | MCAN_INT_RF1W | MCAN_INT_RF1L | \
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MCAN_INT_RF1L)
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#define MCAN_RXFIFO_INTS (MCAN_RXFIFO0_INTS | MCAN_RXFIFO1_INTS | \
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MCAN_INT_HPM | MCAN_RXCOMMON_INTS)
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#define MCAN_RXDEDBUF_INTS (MCAN_INT_DRX | MCAN_RXCOMMON_INTS)
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#define MCAN_RXERR_INTS (MCAN_INT_RF0L | MCAN_INT_RF1L | MCAN_INT_CRCE | \
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MCAN_INT_FOE | MCAN_INT_STE)
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/* TX FIFOQ mode interrupts
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*
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* MCAN_INT_TFE - Tx FIFO Empty
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*
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* TX Event FIFO interrupts
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*
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* MCAN_INT_TEFN - Tx Event FIFO New Entry
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* MCAN_INT_TEFW - Tx Event FIFO Watermark Reached
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* MCAN_INT_TEFF - Tx Event FIFO Full
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* MCAN_INT_TEFL - Tx Event FIFO Element Lost
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*
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* Mode-independent TX-related interrupts
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*
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* MCAN_INT_TC - Transmission Completed
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* MCAN_INT_TCF - Transmission Cancellation Finished
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* MCAN_INT_BE - Bit Error
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* MCAN_INT_ACKE - Acknowledge Error
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*/
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#define MCAN_TXCOMMON_INTS (MCAN_INT_TC | MCAN_INT_TCF | MCAN_INT_BE | \
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MCAN_INT_ACKE)
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#define MCAN_TXFIFOQ_INTS (MCAN_INT_TFE | MCAN_TXCOMMON_INTS)
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#define MCAN_TXEVFIFO_INTS (MCAN_INT_TEFN | MCAN_INT_TEFW | MCAN_INT_TEFF | \
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MCAN_INT_TEFL)
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#define MCAN_TXDEDBUG_INTS MCAN_TXCOMMON_INTS
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#define MCAN_TXERR_INTS (MCAN_INT_TEFL | MCAN_INT_BE | MCAN_INT_ACKE)
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/* Debug ********************************************************************/
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/* Non-standard debug that may be enabled just for testing MCAN */
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@ -807,8 +871,8 @@ static bool mcan_txempty(FAR struct can_dev_s *dev);
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static bool mcan_dedicated_rxbuffer_available(FAR struct sam_mcan_s *priv,
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int bufndx);
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#endif
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static inline void mcan_rxinterrupt(FAR struct can_dev_s *dev, uint32_t msr);
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static inline void mcan_txinterrupt(FAR struct can_dev_s *dev);
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static void mcan_receive(FAR struct can_dev_s *dev,
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FAR uint32_t *rxbuffer, unsigned long nbytes);
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static void mcan_interrupt(FAR struct can_dev_s *dev);
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#ifdef CONFIG_SAMV7_MCAN0
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static int mcan0_interrupt(int irq, void *context);
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@ -1736,8 +1800,8 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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{
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flags = irqsave();
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regval = mcan_getreg(priv, SAM_MCAN_IE_OFFSET);
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regval |= MCAN_TXINTERRUPTS;
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_TXINTERRUPTS);
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regval |= priv->txints;
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, priv->txints);
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irqrestore(flags);
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}
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@ -1822,7 +1886,7 @@ static bool mcan_txempty(FAR struct can_dev_s *dev)
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* True: Data is available
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*
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***************************************************************************/
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#if 0 /* Not Used */
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bool mcan_dedicated_rxbuffer_available(FAR struct sam_mcan_s *priv, int bufndx)
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{
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@ -1842,48 +1906,79 @@ bool mcan_dedicated_rxbuffer_available(FAR struct sam_mcan_s *priv, int bufndx)
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#endif
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/****************************************************************************
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* Name: mcan_rxinterrupt
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* Name: mcan_receive
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*
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* Description:
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* MCAN receive interrupt handler
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* Receive an MCAN messages
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*
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* Input Parameters:
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* priv - MCAN-specific private data
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* msr - Applicable value from the mailbox status register
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* dev - CAN-common state data
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* rxbuffer - The RX buffer containing the received messages
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* nbytes - The length of the received message
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void mcan_rxinterrupt(FAR struct can_dev_s *dev, uint32_t msr)
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static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer,
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unsigned long nbytes)
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{
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FAR struct sam_mcan_s *priv = dev->cd_priv;
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struct can_hdr_s hdr;
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uint32_t regval;
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int ret;
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#warning Missing logic
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}
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/* Invalidate the D-Cache so that we reread the RX buffer data from memory. */
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/****************************************************************************
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* Name: mcan_txinterrupt
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*
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* Description:
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* MCAN TX interrupt handler
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*
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* Input Parameters:
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* priv - MCAN-specific private data
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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arch_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes);
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static inline void mcan_txinterrupt(FAR struct can_dev_s *dev)
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{
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FAR struct sam_mcan_s *priv = dev->cd_priv;
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/* Format the CAN header */
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/* Work R0 contains the CAN ID */
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#warning Missing logic
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regval = *rxbuffer++;
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hdr.ch_rtr = 0;
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#ifdef CONFIG_CAN_EXTID
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hdr.ch_unused = 0;
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if ((regval & BUFFER_R0_XTD) != 0)
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{
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/* Save the extended ID of the newly received message */
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hdr.ch_id = (regval & BUFFER_R0_EXTID_MASK) >> BUFFER_R0_EXTID_SHIFT;
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hdr.ch_extid = true;
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}
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else
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{
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hdr.ch_id = (regval & BUFFER_R0_STDID_MASK) >> BUFFER_R0_STDID_SHIFT;
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hdr.ch_extid = false;
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}
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#else
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if ((regval & BUFFER_R0_XTD) != 0)
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{
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/* Drop any messages with extended IDs */
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return;
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}
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/* Save the standard ID of the newly received message */
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hdr.ch_id = (regval & BUFFER_R0_STDID_MASK) >> BUFFER_R0_STDID_SHIFT;
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#endif
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/* Word R1 contains the DLC and timestamp */
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regval = *rxbuffer++;
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hdr.ch_dlc = (regval & BUFFER_R1_DLC_MASK) >> BUFFER_R1_DLC_SHIFT;
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/* And provide the CAN message to the upper half logic */
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ret = can_receive(dev, &hdr, (FAR uint8_t *)rxbuffer);
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if (ret < 0)
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{
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canlldbg("ERROR: can_receive failed: %d\n", ret);
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}
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}
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/****************************************************************************
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@ -1893,7 +1988,7 @@ static inline void mcan_txinterrupt(FAR struct can_dev_s *dev)
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* Common MCAN interrupt handler
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*
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* Input Parameters:
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* priv - MCAN-specific private data
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* dev - CAN-common state data
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*
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* Returned Value:
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* None
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@ -1903,12 +1998,16 @@ static inline void mcan_txinterrupt(FAR struct can_dev_s *dev)
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static void mcan_interrupt(FAR struct can_dev_s *dev)
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{
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FAR struct sam_mcan_s *priv = dev->cd_priv;
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FAR const struct sam_config_s *config;
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uint32_t ir;
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uint32_t ie;
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uint32_t pending;
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int i;
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uint32_t regval;
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unsigned int nelem;
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unsigned int ndx;
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DEBUGASSERT(priv && priv->config);
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config = priv->config;
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/* Get the set of pending interrupts. */
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@ -1917,19 +2016,40 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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pending = (ir & ie);
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/* Check for common errors */
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if ((pending & MCAN_CMNERR_INTS) != 0)
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{
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canlldbg("ERROR: Common %08x\n", pending & MCAN_CMNERR_INTS);
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/* Clear the error indications */
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_CMNERR_INTS);
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}
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/* Check for transmission errors */
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#warning Missing logic
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if ((pending & MCAN_TXERR_INTS) != 0)
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{
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canlldbg("ERROR: TX %08x\n", pending & MCAN_TXERR_INTS);
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/* Clear the error indications */
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_TXERR_INTS);
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}
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/* Check for successful completion of a transmission */
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if ((pending & MCAN_INT_TC) != 0)
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{
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/* Clear the pending TX completion interrupt */
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/* Clear the pending TX completion interrupt (and all
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* other TX-related interrupts)
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*/
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_INT_TC);
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, priv->txints);
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/* Indicate that there is one more buffer free in the TX FIFOQ by
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* "relasing" it. This may have the effect of waking up a thread
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* "releasing" it. This may have the effect of waking up a thread
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* that has been waiting for a free TX FIFOQ buffer.
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*
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* REVISIT: TX dedicated buffers are not supported.
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@ -1938,15 +2058,20 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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mcan_buffer_release(priv);
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DEBUGASSERT(priv->txfsem.semcount <= priv->ntxfifoq);
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}
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else if ((pending & priv->txints) != 0)
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{
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/* Clear unhandled TX events */
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/* Check for reception errors */
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#warning Missing logic
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, priv->txints);
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}
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#if 0 /* Not used */
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/* Check if a message has been stored to the dedicated RX buffer (DRX) */
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if ((pending & MCAN_INT_DRX) != 0))
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{
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int i;
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/* Clear the pending DRX interrupt */
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_INT_DRX);
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@ -1974,9 +2099,103 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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}
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#endif
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/* Check for successful reception of a message in an RXFIFO */
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#warning Missing logic
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/* Check for reception errors */
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if ((pending & MCAN_RXERR_INTS) != 0)
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{
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canlldbg("ERROR: RX %08x\n", pending & MCAN_RXERR_INTS);
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/* Clear the error indications */
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_RXERR_INTS);
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}
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/* Check for successful reception of a new message in RX FIFO0 */
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if ((pending & MCAN_INT_RF0N) != 0)
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{
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DEBUGASSERT(priv->txfsem.semcount <= priv->nrxfifo0);
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/* Clear the RX FIFO0 interrupt (and all other FIFO0-related
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* interrupts)
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*/
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_RXFIFO0_INTS);
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pending &= ~MCAN_RXFIFO0_INTS;
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/* Handle the newly received message in FIFO0 */
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regval = mcan_getreg(priv, SAM_MCAN_RXF0S_OFFSET);
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if ((regval & MCAN_RXF0S_RF0L) != 0)
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{
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canlldbg("ERROR: Message lost: %08x\n", regval);
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}
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else
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{
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ndx = (regval & MCAN_RXF0S_F0GI_MASK) >> MCAN_RXF0S_F0GI_SHIFT;
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nelem = (regval & MCAN_RXF0S_F0FL_MASK) >> MCAN_RXF0S_F0FL_SHIFT;
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if (nelem > 0)
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{
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mcan_receive(dev,
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config->msgram.rxfifo0 +
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(ndx * priv->config->rxfifo0esize),
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nelem * priv->config->rxfifo0esize);
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}
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}
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/* Acknowledge reading the FIFO entry */
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mcan_putreg(priv, SAM_MCAN_RXF0A_OFFSET, ndx);
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}
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/* Check for successful reception of a new message in RX FIFO1 */
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if ((pending & MCAN_INT_RF1N) != 0)
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{
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DEBUGASSERT(priv->txfsem.semcount <= priv->nrxfifo1);
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/* Clear the RX FIFO1 interrupt (and all other FIFO1-related
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* interrupts)
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*/
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_RXFIFO1_INTS);
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pending &= ~MCAN_RXFIFO1_INTS;
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/* Handle the newly received message in FIFO1 */
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regval = mcan_getreg(priv, SAM_MCAN_RXF1S_OFFSET);
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if ((regval & MCAN_RXF0S_RF0L) != 0)
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{
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canlldbg("ERROR: Message lost: %08x\n", regval);
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}
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else
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{
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ndx = (regval & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT;
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nelem = (regval & MCAN_RXF1S_F1FL_MASK) >> MCAN_RXF1S_F1FL_SHIFT;
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if (nelem > 0)
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{
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mcan_receive(dev,
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config->msgram.rxfifo1 +
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(ndx * priv->config->rxfifo1esize),
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nelem * priv->config->rxfifo1esize);
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}
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}
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/* Acknowledge reading the FIFO entry */
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mcan_putreg(priv, SAM_MCAN_RXF1A_OFFSET, ndx);
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}
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/* Clear unhandled RX interrupts */
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if ((pending & priv->rxints) != 0)
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{
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, priv->rxints);
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}
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}
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/****************************************************************************
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@ -2046,9 +2265,9 @@ static void mcan_configure_interrupts(FAR struct sam_mcan_s *priv)
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/* Select RX-related interrupts */
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#if 0 /* Dedicated RX buffers are not used by this driver */
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priv->rxints = MCAN_INT_DRX | MCAN_COMMON_INTS;
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priv->rxints = MCAN_RXDEDBUF_INTS | MCAN_COMMON_INTS;
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#else
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# warning Missing Logic
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priv->rxints = MCAN_RXFIFO_INTS | MCAN_COMMON_INTS;
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#endif
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/* Select RX-related interrupts */
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