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arch/arm/src/stm32f7: Fix an error introduced by the patch by Evgeniy Bobkov in Issue #114. That patch brok all STM32 F7 builds.

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This commit is contained in:
Gregory Nutt 2018-08-03 14:26:29 -06:00
parent 056d704cf9
commit bbee0d70de
3 changed files with 3 additions and 3 deletions
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2
arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h
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@ -75,7 +75,7 @@
#define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */ #define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */
#define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */ #define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */
#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x002fffff: FLASH memory (ITCM) */ #define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x002fffff: FLASH memory (ITCM) */
#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x080fffff: FLASH memory (AXIM) */ #define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory (AXIM) */
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */ #define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */
/* Information Addresses ************************************************************/ /* Information Addresses ************************************************************/

2
arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
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@ -75,7 +75,7 @@
#define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */ #define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */
#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x002fffff: FLASH memory (ITCM) */ #define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x002fffff: FLASH memory (ITCM) */
#define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */ #define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */
#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x080fffff: FLASH memory (AXIM) */ #define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory (AXIM) */
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */ #define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */
/* Information Addresses ************************************************************/ /* Information Addresses ************************************************************/

2
arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
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@ -75,7 +75,7 @@
#define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */ #define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */
#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x003fffff: FLASH memory (ITCM) */ #define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x003fffff: FLASH memory (ITCM) */
#define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */ #define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */
#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x081fffff: FLASH memory (AXIM) */ #define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory (AXIM) */
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */ #define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */
/* Information Addresses ************************************************************/ /* Information Addresses ************************************************************/