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Fixed non-UTF8 characters.

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This commit is contained in:
Fotis Panagiotopoulos 2022-09-27 15:14:07 +03:00 committed by Xiang Xiao
parent 078a0486f5
commit bbf3f2866d
120 changed files with 449 additions and 449 deletions
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8
arch/arm/src/a1x/hardware/a10_memorymap.h
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@ -46,7 +46,7 @@
#define A1X_SRAMC_PSECTION 0x01d00000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_PSECTION 0x01e00000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
#define A1X_DDR_PSECTION 0x40000000 /* DDR-II/DDR-III 0x4000:0000-0xbfff:ffff 2G */
#define A1X_BROM_PSECTION 0xfff00000 /* BROM 0xffff:0000—0xffff:7fff 32K */
#define A1X_BROM_PSECTION 0xfff00000 /* BROM 0xffff:0000-0xffff:7fff 32K */
/* A1X Offsets from the internal memory section base address */
@ -136,7 +136,7 @@
/* A1X offsets from the BRROM section base address */
#define A1X_BROM_OFFSET 0x000f0000 /* BROM 0xffff:0000—0xffff:7fff 32K */
#define A1X_BROM_OFFSET 0x000f0000 /* BROM 0xffff:0000-0xffff:7fff 32K */
/* A1X internal memory physical base addresses */
@ -239,7 +239,7 @@
#define A1X_PERIPH_SIZE 0x00050000 /* Peripherals 0x01c0:0000-0x01c4:ffff */
#define A1X_SRAMC_SIZE 0x00100000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_SIZE 0x000c0000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
#define A1X_BROM_SIZE 0x000f8000 /* BROM 0xfff0:0000—0xffff:7fff 32K */
#define A1X_BROM_SIZE 0x000f8000 /* BROM 0xfff0:0000-0xffff:7fff 32K */
/* Force configured sizes that might exceed 2GB to be unsigned long */
@ -303,7 +303,7 @@
#define A1X_SRAMC_VSECTION 0x01d00000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_VSECTION 0x01e00000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
#define A1X_DDR_VSECTION 0x40000000 /* DDR-II/DDR-III 0x4000:0000-0xbfff:ffff 2G */
#define A1X_BROM_VSECTION 0xfff00000 /* BROM 0xffff:0000—0xffff:7fff 32K */
#define A1X_BROM_VSECTION 0xfff00000 /* BROM 0xffff:0000-0xffff:7fff 32K */
#endif

8
arch/arm/src/armv7-a/arm.h
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@ -19,10 +19,10 @@
****************************************************************************/
/* References:
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* ARM DDI 0406C.b (ID072512)
*/

2
arch/arm/src/armv7-a/arm_l2cc_pl310.c
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@ -18,7 +18,7 @@
*
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*
* NOTE: This logic is incompatible with older versions of the PL310!

10
arch/arm/src/armv7-a/cp15.h
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@ -20,10 +20,10 @@
/* References:
*
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* ARM DDI 0406C.b (ID072512)
*/
@ -55,7 +55,7 @@
* <CRm> is the operational register
* <Op2> is the Opcode_2 value for the register.
*
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
*/
#ifdef __ASSEMBLY__

2
arch/arm/src/armv7-a/l2cc_pl310.h
View File

@ -18,7 +18,7 @@
*
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*/

10
arch/arm/src/armv7-a/mmu.h
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@ -19,10 +19,10 @@
****************************************************************************/
/* References:
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM.
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM.
* All rights reserved. ARM DDI 0406C.b (ID072512)
*/
@ -62,7 +62,7 @@
/* MMU CP15 Register Bit Definitions ****************************************/
/* Reference: Cortex-A5™ MPCore
/* Reference: Cortex-A5™ MPCore
* Paragraph 6.7, "MMU software accessible registers."
*/

2
arch/arm/src/armv7-r/arm_l2cc_pl310.c
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@ -18,7 +18,7 @@
*
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*
* NOTE: This logic is incompatible with older versions of the PL310!

2
arch/arm/src/armv7-r/cp15.h
View File

@ -52,7 +52,7 @@
* <CRm> is the operational register
* <Op2> is the Opcode_2 value for the register.
*
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
*/
#ifdef __ASSEMBLY__

2
arch/arm/src/armv7-r/l2cc_pl310.h
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@ -18,7 +18,7 @@
*
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*/

2
arch/arm/src/kinetis/hardware/kinetis_ewm.h
View File

@ -54,7 +54,7 @@
#define EWM_CTRL_EWMEN (1 << 0) /* Bit 0: EWM enable */
#define EWM_CTRL_ASSIN (1 << 2) /* Bit 1: EWM_in's Assertion State Select */
#define EWM_CTRL_INEN (1 << 3) /* Bit 2: Input Enable */
/* Bits 7–3: Reserved */
/* Bits 7-3: Reserved */
/* Service Register (8-bit values: 0xb4 followed by 0x2c) */

2
arch/arm/src/kinetis/hardware/kinetis_rngb.h
View File

@ -61,7 +61,7 @@
#define RNG_VER_MINOR_MASK (0xff << RNG_VER_MINOR_SHIFT)
#define RNG_VER_MAJOR_SHIFT (8) /* Bits 8-15: Major version number */
#define RNG_VER_MAJOR_MASK (0xff << RNG_VER_MAJOR_SHIFT)
/* Bits 27–16: Reserved */
/* Bits 27-16: Reserved */
#define RNG_VER_TYPE_SHIFT (28) /* Bits 28-31: Random number generator type */
#define RNG_VER_TYPE_MASK (15 << RNG_VER_TYPE_SHIFT)
# define RNG_VER_TYPE_RNGA (0 << RNG_VER_TYPE_SHIFT)

4
arch/arm/src/kinetis/hardware/kinetis_tsi.h
View File

@ -199,7 +199,7 @@
#define TSI_SCANC_EXTCHRG_SHIFT (19) /* Bits 19-23: External oscillator charge current select */
#define TSI_SCANC_EXTCHRG_MASK (31 << TSI_SCANC_EXTCHRG_SHIFT)
# define TSI_SCANC_EXTCHRG_UA(n) (((n)-1) << TSI_SCANC_EXTCHRG_SHIFT) /* n µA charge current, n=1..32 */
# define TSI_SCANC_EXTCHRG_UA(n) (((n)-1) << TSI_SCANC_EXTCHRG_SHIFT) /* n µA charge current, n=1..32 */
#define TSI_SCANC_CAPTRM_SHIFT (24) /* Bits 24-26: Internal capacitance trim value */
#define TSI_SCANC_CAPTRM_MASK (7 << TSI_SCANC_CAPTRM_SHIFT)
@ -214,7 +214,7 @@
#define TSI_SCANC_REFCHRG_SHIFT (27) /* Bits 27-31: Reference oscillator charge current select */
#define TSI_SCANC_REFCHRG_MASK (31 << TSI_SCANC_REFCHRG_SHIFT)
# define TSI_SCANC_REFCHRG_UA(n) (((n)-1) << TSI_SCANC_REFCHRG_SHIFT) /* n µA charge current, n=1..32 */
# define TSI_SCANC_REFCHRG_UA(n) (((n)-1) << TSI_SCANC_REFCHRG_SHIFT) /* n µA charge current, n=1..32 */
/* Pin enable register */

4
arch/arm/src/kinetis/hardware/kinetis_wdog.h
View File

@ -67,7 +67,7 @@
/* Watchdog Status and Control Register High (16-bit) */
#define WDOG_STCTRLH_WDOGEN (1 << 0) /* Bit 0: Enables or disables the WDOG’s operation */
#define WDOG_STCTRLH_WDOGEN (1 << 0) /* Bit 0: Enables or disables the WDOG's operation */
#define WDOG_STCTRLH_CLKSRC (1 << 1) /* Bit 1: Selects clock source for the WDOG timer */
#define WDOG_STCTRLH_IRQRSTEN (1 << 2) /* Bit 2: Enable the debug breadcrumbs feature */
#define WDOG_STCTRLH_WINEN (1 << 3) /* Bit 3: Enable windowing mode */
@ -88,7 +88,7 @@
# define WDOG_STCTRLH_BYTESEL_BYTE2 (2 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 2 selected */
# define WDOG_STCTRLH_BYTESEL_BYTE3 (3 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 3 selected */
#define WDOG_STCTRLH_DISTESTWDOG (1 << 14) /* Bit 14: Disable WDOG’s functional test mode */
#define WDOG_STCTRLH_DISTESTWDOG (1 << 14) /* Bit 14: Disable WDOG's functional test mode */
/* Bit 15: Reserved */
/* Watchdog Status and Control Register Low (16-bit) */

2
arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
View File

@ -613,7 +613,7 @@ void lpc17_40_dmastop(DMA_HANDLE handle)
/* Disable this channel and mask any further interrupts from the channel.
* this channel. The channel is disabled by clearning the channel
* enable bit. Any outstanding data in the FIFO’s is lost.
* enable bit. Any outstanding data in the FIFO's is lost.
*/
regaddr = LPC17_40_DMACH_CONFIG((uint32_t)dmach->chn);

4
arch/arm/src/lpc31xx/lpc31_analogdie.h
View File

@ -295,9 +295,9 @@
#define CODEC_DEC_DCFILTO (1 << 18) /* Bit 18: Enable DC blocking filter after decimation filters */
#define CODEC_DEC_DBLIN (1 << 17) /* Bit 17: Enable soft start-up after a reset */
#define CODEC_DEC_DELAY_DBLIN (1 << 16) /* Bit 16: Enable delay timer after a reset */
#define CODEC_DEC_GAINL_SHIFT (8) /* Bits 8-15: Gain settings, LEFT channel (2’s compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINL_SHIFT (8) /* Bits 8-15: Gain settings, LEFT channel (2's compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINL_MASK (0xff << CODEC_DEC_GAINL_SHIFT)
#define CODEC_DEC_GAINR_SHIFT (0) /* Bits 0-7: Gain settings RIGHT channel (2’s compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINR_SHIFT (0) /* Bits 0-7: Gain settings RIGHT channel (2's compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINR_MASK (0xff << CODEC_DEC_GAINR_SHIFT)
/* Interpolator control */

2
arch/arm/src/lpc31xx/lpc31_bcrndx.c
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_cgu.h
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
*/
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_CGU_H

2
arch/arm/src/lpc31xx/lpc31_cgudrvr.h
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_clkdomain.c
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_clkfreq.c
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@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_esrndx.c
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_fdcndx.c
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@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

6
arch/arm/src/lpc31xx/lpc31_fdivinit.c
View File

@ -62,7 +62,7 @@
* Say an input frequency of 13 MHz is given while a frequency of 12
* MHz is required. In this case we want a frequency
*
* f▓ = 12/13 в f
* f' = 12/13 x f
*
* So n = 12 and m = 13. This then gives
*
@ -77,8 +77,8 @@
* 4 bits. If madd/msub bit width has been set to say 8 bits, it is allowed
* to shift 4 bits, giving:
*
* msub▓ = -(12<<4)= -12 в 24 = -12 в 16 = -192
* madd▓ = 1<<4 = 24 = 16
* msub' = -(12<<4)= -12 x 24 = -12 x 16 = -192
* madd' = 1<<4 = 24 = 16
*
****************************************************************************/

2
arch/arm/src/lpc31xx/lpc31_pllconfig.c
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@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_setfreqin.c
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@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_softreset.c
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@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

4
arch/arm/src/lpc43xx/hardware/lpc43_i2s.h
View File

@ -113,9 +113,9 @@
#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
/* Bits 15-31: Reserved */
/* Transmit FIFO: 8 × 32-bit transmit FIFO */
/* Transmit FIFO: 8 x 32-bit transmit FIFO */
/* Receive FIFO: 8 × 32-bit receive FIFO */
/* Receive FIFO: 8 x 32-bit receive FIFO */
/* Status Feedback Register */

10
arch/arm/src/sam34/hardware/sam_rtc.h
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@ -120,11 +120,11 @@
# define RTC_MR_THIGH_31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
# define RTC_MR_THIGH_16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
# define RTC_MR_THIGH_4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
# define RTC_MR_THIGH_976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
# define RTC_MR_THIGH_488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
# define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
# define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
# define RTC_MR_THIGH_976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
# define RTC_MR_THIGH_488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
# define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
# define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */
# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT)

4
arch/arm/src/sama5/hardware/sam_xdmac.h
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@ -51,7 +51,7 @@
#define SAM_XDMAC_GSWR_OFFSET 0x0038 /* Global Channel Software Request Register */
#define SAM_XDMAC_GSWS_OFFSET 0x003c /* Global Channel Software Request Status Register */
#define SAM_XDMAC_GSWF_OFFSET 0x0040 /* Global Channel Software Flush Request Register */
/* 0x0044–0x004c Reserved */
/* 0x0044-0x004c Reserved */
/* Offsets to the base of the DMA channel registers */
@ -92,7 +92,7 @@
#define SAM_XDMACH_CSUS_OFFSET 0x0030 /* Channel Source Microblock Stride */
#define SAM_XDMACH_CDUS_OFFSET 0x0034 /* Channel Destination Microblock Stride */
/* 0x0038-0x003c Reserved */
/* 0x0fec–0x0ffc Reserved */
/* 0x0fec-0x0ffc Reserved */
/* XDMAC Register Addresses *************************************************/

2
arch/arm/src/samd2l2/hardware/samd20_memorymap.h
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@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H

2
arch/arm/src/samd2l2/hardware/samd20_pinmap.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H

2
arch/arm/src/samd2l2/hardware/samd21_memorymap.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H

2
arch/arm/src/samd2l2/hardware/samd21_pinmap.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H

2
arch/arm/src/samd2l2/hardware/samd_evsys.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H

4
arch/arm/src/samd2l2/hardware/samd_fuses.h
View File

@ -41,9 +41,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H

4
arch/arm/src/samd2l2/hardware/samd_gclk.h
View File

@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H

8
arch/arm/src/samd2l2/hardware/samd_i2c_master.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H
@ -203,9 +203,9 @@
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */

2
arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H

4
arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
View File

@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H

4
arch/arm/src/samd2l2/hardware/samd_pm.h
View File

@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H

4
arch/arm/src/samd2l2/hardware/samd_port.h
View File

@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H

2
arch/arm/src/samd2l2/hardware/samd_sercom.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H

2
arch/arm/src/samd2l2/hardware/samd_spi.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H

68
arch/arm/src/samd2l2/hardware/samd_sysctrl.h
View File

@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H
@ -154,22 +154,22 @@
#define SYSCTRL_XOSC_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define SYSCTRL_XOSC_STARTUP_MASK (15 << SYSCTRL_XOSC_STARTUP_SHIFT)
# define SYSCTRL_XOSC_STARTUP(n) ((n) << SYSCTRL_XOSC_STARTUP_SHIFT)
# define SYSCTRL_XOSC_STARTUP_31US (0 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31µs */
# define SYSCTRL_XOSC_STARTUP_61US (1 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 61µs */
# define SYSCTRL_XOSC_STARTUP_122US (2 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC_STARTUP_244US (3 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 244µs */
# define SYSCTRL_XOSC_STARTUP_488US (4 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 488µs */
# define SYSCTRL_XOSC_STARTUP_977US (5 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 977µs */
# define SYSCTRL_XOSC_STARTUP_2MS (6 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1953µs */
# define SYSCTRL_XOSC_STARTUP_4MS (7 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 3906µs */
# define SYSCTRL_XOSC_STARTUP_8MS (8 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 7813µs */
# define SYSCTRL_XOSC_STARTUP_16MS (9 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 15625µs */
# define SYSCTRL_XOSC_STARTUP_31MS (10 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31250µs */
# define SYSCTRL_XOSC_STARTUP_63MS (11 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 62500µs */
# define SYSCTRL_XOSC_STARTUP_125MS (12 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 125000µs */
# define SYSCTRL_XOSC_STARTUP_250MS (13 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 250000µs */
# define SYSCTRL_XOSC_STARTUP_500MS (14 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 500000µs */
# define SYSCTRL_XOSC_STARTUP_1S (15 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1000000µs */
# define SYSCTRL_XOSC_STARTUP_31US (0 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31µs */
# define SYSCTRL_XOSC_STARTUP_61US (1 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 61µs */
# define SYSCTRL_XOSC_STARTUP_122US (2 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC_STARTUP_244US (3 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 244µs */
# define SYSCTRL_XOSC_STARTUP_488US (4 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 488µs */
# define SYSCTRL_XOSC_STARTUP_977US (5 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 977µs */
# define SYSCTRL_XOSC_STARTUP_2MS (6 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1953µs */
# define SYSCTRL_XOSC_STARTUP_4MS (7 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 3906µs */
# define SYSCTRL_XOSC_STARTUP_8MS (8 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 7813µs */
# define SYSCTRL_XOSC_STARTUP_16MS (9 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 15625µs */
# define SYSCTRL_XOSC_STARTUP_31MS (10 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31250µs */
# define SYSCTRL_XOSC_STARTUP_63MS (11 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 62500µs */
# define SYSCTRL_XOSC_STARTUP_125MS (12 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 125000µs */
# define SYSCTRL_XOSC_STARTUP_250MS (13 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 250000µs */
# define SYSCTRL_XOSC_STARTUP_500MS (14 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 500000µs */
# define SYSCTRL_XOSC_STARTUP_1S (15 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1000000µs */
/* 32kHz external crystal oscillator control register */
@ -183,14 +183,14 @@
#define SYSCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define SYSCTRL_XOSC32K_STARTUP_MASK (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT)
# define SYSCTRL_XOSC32K_STARTUP(n) ((n) << SYSCTRL_XOSC32K_STARTUP_SHIFT)
# define SYSCTRL_XOSC32K_STARTUP_122US (0 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC32K_STARTUP_1MS (1 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1068µs */
# define SYSCTRL_XOSC32K_STARTUP_63MS (2 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 62592µs */
# define SYSCTRL_XOSC32K_STARTUP_125MS (3 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 125092µs */
# define SYSCTRL_XOSC32K_STARTUP_500MS (4 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 500092µs */
# define SYSCTRL_XOSC32K_STARTUP_1S (5 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1000092µs */
# define SYSCTRL_XOSC32K_STARTUP_2S (6 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 2000092µs */
# define SYSCTRL_XOSC32K_STARTUP_4S (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 4000092µs */
# define SYSCTRL_XOSC32K_STARTUP_122US (0 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC32K_STARTUP_1MS (1 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1068µs */
# define SYSCTRL_XOSC32K_STARTUP_63MS (2 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 62592µs */
# define SYSCTRL_XOSC32K_STARTUP_125MS (3 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 125092µs */
# define SYSCTRL_XOSC32K_STARTUP_500MS (4 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 500092µs */
# define SYSCTRL_XOSC32K_STARTUP_1S (5 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1000092µs */
# define SYSCTRL_XOSC32K_STARTUP_2S (6 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 2000092µs */
# define SYSCTRL_XOSC32K_STARTUP_4S (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 4000092µs */
#define SYSCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
@ -208,14 +208,14 @@
#define SYSCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define SYSCTRL_OSC32K_STARTUP_MASK (7 << SYSCTRL_OSC32K_STARTUP_SHIFT)
# define SYSCTRL_OSC32K_STARTUP(n) ((n) << SYSCTRL_OSC32K_STARTUP_SHIFT)
# define SYSCTRL_OSC32K_STARTUP_92US (0 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define SYSCTRL_OSC32K_STARTUP_122US (1 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_OSC32K_STARTUP_183US (2 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define SYSCTRL_OSC32K_STARTUP_305US (3 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define SYSCTRL_OSC32K_STARTUP_549US (4 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define SYSCTRL_OSC32K_STARTUP_1MS (5 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define SYSCTRL_OSC32K_STARTUP_2MS (6 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define SYSCTRL_OSC32K_STARTUP_4MS (7 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
# define SYSCTRL_OSC32K_STARTUP_92US (0 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define SYSCTRL_OSC32K_STARTUP_122US (1 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_OSC32K_STARTUP_183US (2 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define SYSCTRL_OSC32K_STARTUP_305US (3 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define SYSCTRL_OSC32K_STARTUP_549US (4 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define SYSCTRL_OSC32K_STARTUP_1MS (5 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define SYSCTRL_OSC32K_STARTUP_2MS (6 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define SYSCTRL_OSC32K_STARTUP_4MS (7 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
#define SYSCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define SYSCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */

4
arch/arm/src/samd2l2/hardware/samd_usart.h
View File

@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H

4
arch/arm/src/samd2l2/hardware/samd_wdt.h
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H
@ -72,7 +72,7 @@
/* Configuration register */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0-3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */

6
arch/arm/src/samd2l2/hardware/saml_i2c_master.h
View File

@ -164,9 +164,9 @@
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */

16
arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
View File

@ -115,14 +115,14 @@
#define OSC32KCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define OSC32KCTRL_OSC32K_STARTUP_MASK (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT)
# define OSC32KCTRL_OSC32K_STARTUP(n) ((n) << OSC32KCTRL_OSC32K_STARTUP_SHIFT)
# define OSC32KCTRL_OSC32K_STARTUP_92US (0 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 92ľs */
# define OSC32KCTRL_OSC32K_STARTUP_122US (1 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 122ľs */
# define OSC32KCTRL_OSC32K_STARTUP_183US (2 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 183ľs */
# define OSC32KCTRL_OSC32K_STARTUP_305US (3 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 305ľs */
# define OSC32KCTRL_OSC32K_STARTUP_549US (4 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 549ľs */
# define OSC32KCTRL_OSC32K_STARTUP_1MS (5 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 1038ľs */
# define OSC32KCTRL_OSC32K_STARTUP_2MS (6 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 2014ľs */
# define OSC32KCTRL_OSC32K_STARTUP_4MS (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 3967ľs */
# define OSC32KCTRL_OSC32K_STARTUP_92US (0 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define OSC32KCTRL_OSC32K_STARTUP_122US (1 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define OSC32KCTRL_OSC32K_STARTUP_183US (2 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define OSC32KCTRL_OSC32K_STARTUP_305US (3 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define OSC32KCTRL_OSC32K_STARTUP_549US (4 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define OSC32KCTRL_OSC32K_STARTUP_1MS (5 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define OSC32KCTRL_OSC32K_STARTUP_2MS (6 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define OSC32KCTRL_OSC32K_STARTUP_4MS (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
#define OSC32KCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define OSC32KCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */

64
arch/arm/src/samd2l2/hardware/saml_oscctrl.h
View File

@ -117,22 +117,22 @@
#define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP(n) ((n) << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
/* 16MHz internal oscillator control register */
@ -159,22 +159,22 @@
#define OSCCTRL_OSC16MCTRL_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define OSCCTRL_OSC16MCTRL_STARTUP_MASK (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT)
# define OSCCTRL_OSC16MCTRL_STARTUP(n) ((n) << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT)
# define OSCCTRL_OSC16MCTRL_STARTUP_31US (0 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_61US (1 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_122US (2 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_244US (3 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_488US (4 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_977US (5 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_2MS (6 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_4MS (7 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_8MS (8 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_16MS (9 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_31MS (10 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_63MS (11 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_125MS (12 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_250MS (13 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_500MS (14 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_1S (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1000000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_31US (0 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_61US (1 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_122US (2 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_244US (3 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_488US (4 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_977US (5 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_2MS (6 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_4MS (7 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_8MS (8 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_16MS (9 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_31MS (10 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_63MS (11 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_125MS (12 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_250MS (13 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_500MS (14 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_1S (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1000000µs */
/* DFLL48M control register */

2
arch/arm/src/samd2l2/hardware/saml_wdt.h
View File

@ -72,7 +72,7 @@
/* Configuration register */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0-3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */

2
arch/arm/src/samd2l2/sam_lowputc.c
View File

@ -20,7 +20,7 @@
/* References:
* 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* 2. Atmel sample code. This code has an ASF license with is compatible
* with the NuttX BSD license, but includes the provision that this
* code not be used in non-Atmel products. That sample code was used

2
arch/arm/src/samd2l2/sam_port.c
View File

@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
/****************************************************************************

2
arch/arm/src/samd2l2/sam_sercom.c
View File

@ -20,7 +20,7 @@
/* References:
* 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
/****************************************************************************

4
arch/arm/src/samd2l2/samd_clockconfig.c
View File

@ -20,9 +20,9 @@
/* References:
* 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* 2. "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
* 3. Atmel sample code for the SAMD20. This code has an ASF license
* with is compatible with the NuttX BSD license, but includes the
* provision that this code not be used in non-Atmel products. That

6
arch/arm/src/samd5e5/hardware/sam_i2c_master.h
View File

@ -184,9 +184,9 @@
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
/* Control B register */

32
arch/arm/src/samd5e5/hardware/sam_oscctrl.h
View File

@ -153,22 +153,22 @@
#define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (20) /* Bits 20-23: Start-up time */
#define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP(n) ((n) << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
#define OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT (24) /* Bits 24-27: Clock Failure Detector Prescaler */
#define OSCCTRL_XOSCCTRL_CFDPRESC_MASK (15 << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT)

2
arch/arm/src/samd5e5/hardware/sam_wdt.h
View File

@ -65,7 +65,7 @@
/* Configuration register */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0-3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */

4
arch/arm/src/samv7/hardware/sam_xdmac.h
View File

@ -51,7 +51,7 @@
#define SAM_XDMAC_GSWR_OFFSET 0x0038 /* Global Channel Software Request Register */
#define SAM_XDMAC_GSWS_OFFSET 0x003c /* Global Channel Software Request Status Register */
#define SAM_XDMAC_GSWF_OFFSET 0x0040 /* Global Channel Software Flush Request Register */
/* 0x0044–0x004c Reserved */
/* 0x0044-0x004c Reserved */
/* Offsets to the base of the DMA channel registers */
@ -100,7 +100,7 @@
#define SAM_XDMACH_CSUS_OFFSET 0x0030 /* Channel Source Microblock Stride */
#define SAM_XDMACH_CDUS_OFFSET 0x0034 /* Channel Destination Microblock Stride */
/* 0x0038-0x003c Reserved */
/* 0x0fec–0x0ffc Reserved */
/* 0x0fec-0x0ffc Reserved */
/* XDMAC Register Addresses *************************************************/

2
arch/arm/src/stm32/stm32f30xxx_rcc.c
View File

@ -186,7 +186,7 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32_USB
/* USB clock divider. This bit must be valid before enabling the USB
* clock in the RCC_APB1ENR register. This bit can’t be reset if the USB
* clock in the RCC_APB1ENR register. This bit can't be reset if the USB
* clock is enabled.
*/

2
arch/hc/include/hcs12/irq.h
View File

@ -39,7 +39,7 @@
/* CCR bit definitions */
#define HCS12_CCR_C (1 << 0) /* Bit 0: Carry/Borrow status bit */
#define HCS12_CCR_V (1 << 1) /* Bit 1: Two’s complement overflow status bit */
#define HCS12_CCR_V (1 << 1) /* Bit 1: Two's complement overflow status bit */
#define HCS12_CCR_Z (1 << 2) /* Bit 2: Zero status bit */
#define HCS12_CCR_N (1 << 3) /* Bit 3: Negative status bit */
#define HCS12_CCR_I (1 << 4) /* Bit 4: Maskable interrupt control bit */

48
arch/hc/src/m9s12/chip.h
View File

@ -34,8 +34,8 @@
/* Memory Map.
*
* At reset:
* 0x0000–0x03ff: register space
* 0x0000–0x1fff: 7K RAM (1K RAM hidden behind register space)
* 0x0000-0x03ff: register space
* 0x0000-0x1fff: 7K RAM (1K RAM hidden behind register space)
*/
#define HCS12_REG_BASE 0x0000 /* 0x0000-0x03ff: Mapped Register base address */
@ -47,30 +47,30 @@
/* Device Register Map Overview (all relative to HCS12_REG_BASE) */
#define HCS12_CORE1_BASE 0x0000 /* 0x0000–0x0017: Ports A, B, E, Modes, Inits (MMC, INT, MEBI) */
/* 0x0018–0x0019: Reserved */
#define HCS12_CORE1_BASE 0x0000 /* 0x0000-0x0017: Ports A, B, E, Modes, Inits (MMC, INT, MEBI) */
/* 0x0018-0x0019: Reserved */
#define HCS12_DEVID_BASE 0x001a /* 0x001a-0x001b: Device ID register (PARTID) */
#define HCS12_CORE2_BASE 0x001c /* 0x001c–0x001f: MEMSIZ, IRQ, HPRIO (INT, MMC) */
#define HCS12_CORE2_BASE 0x001c /* 0x001c-0x001f: MEMSIZ, IRQ, HPRIO (INT, MMC) */
#define HCS12_CORE3_BASE 0x0020 /* 0x0020-0x002f: DBG */
#define HCS12_CORE4_BASE 0x0030 /* 0x0030–0x0033: PPAGE, Port K (MEBI, MMC) */
#define HCS12_CRG_BASE 0x0034 /* 0x0034–0x003f: Clock and Reset Generator (PLL, RTI, COP) */
#define HCS12_TIM_BASE 0x0040 /* 0x0040–0x006f: Standard Timer 16-bit 4 channels (TIM) */
/* 0x0070–0x007f: Reserved */
#define HCS12_ATD_BASE 0x0080 /* 0x0080–0x009f: Analog-to-Digital Converter 10-bit, 8-channel (ATD) */
/* 0x00a0–0x00c7: Reserved */
#define HCS12_SCI0_BASE 0x00c8 /* 0x00c8–0x00cf: Serial Communications Interface 0 (SCI0) */
#define HCS12_SCI1_BASE 0x00d0 /* 0x00d0–0x00d7: Serial Communications Interface 1 (SCI1) */o
#define HCS12_SPI_BASE 0x00d8 /* 0x00d8–0x00df: Serial Peripheral Interface (SPI) */
#define HCS12_IIC_BASE 0x00e0 /* 0x00e0–0x00e7: Inter IC Bus (IIC) */
/* 0x00e8–0x00ff: Reserved */
#define HCS12_FLASH_BASE 0x0100 /* 0x0100–0x010f: FLASH Control Register */
/* 0x0110–0x011f: Reserved */
#define HCS12_EPHY_BASE 0x0120 /* 0x0120–0x0123: Ethernet Physical Interface (EPHY) */
/* 0x0124–0x013f: Reserved */
#define HCS12_EMAC_BASE 0x0140 /* 0x0140–0x016f: Ethernet Media Access Controller (EMAC) */
/* 0x0170–0x023f: Reserved */
#define HCS12_PIM_BASE 0x0240 /* 0x0240–0x026f: Port Integration Module (PIM) */
/* 0x0270–0x03ff: Reserved */
#define HCS12_CORE4_BASE 0x0030 /* 0x0030-0x0033: PPAGE, Port K (MEBI, MMC) */
#define HCS12_CRG_BASE 0x0034 /* 0x0034-0x003f: Clock and Reset Generator (PLL, RTI, COP) */
#define HCS12_TIM_BASE 0x0040 /* 0x0040-0x006f: Standard Timer 16-bit 4 channels (TIM) */
/* 0x0070-0x007f: Reserved */
#define HCS12_ATD_BASE 0x0080 /* 0x0080-0x009f: Analog-to-Digital Converter 10-bit, 8-channel (ATD) */
/* 0x00a0-0x00c7: Reserved */
#define HCS12_SCI0_BASE 0x00c8 /* 0x00c8-0x00cf: Serial Communications Interface 0 (SCI0) */
#define HCS12_SCI1_BASE 0x00d0 /* 0x00d0-0x00d7: Serial Communications Interface 1 (SCI1) */o
#define HCS12_SPI_BASE 0x00d8 /* 0x00d8-0x00df: Serial Peripheral Interface (SPI) */
#define HCS12_IIC_BASE 0x00e0 /* 0x00e0-0x00e7: Inter IC Bus (IIC) */
/* 0x00e8-0x00ff: Reserved */
#define HCS12_FLASH_BASE 0x0100 /* 0x0100-0x010f: FLASH Control Register */
/* 0x0110-0x011f: Reserved */
#define HCS12_EPHY_BASE 0x0120 /* 0x0120-0x0123: Ethernet Physical Interface (EPHY) */
/* 0x0124-0x013f: Reserved */
#define HCS12_EMAC_BASE 0x0140 /* 0x0140-0x016f: Ethernet Media Access Controller (EMAC) */
/* 0x0170-0x023f: Reserved */
#define HCS12_PIM_BASE 0x0240 /* 0x0240-0x026f: Port Integration Module (PIM) */
/* 0x0270-0x03ff: Reserved */
/****************************************************************************
* Public Types

10
arch/mips/include/mips32/cp0.h
View File

@ -41,7 +41,7 @@
# define MIPS32_CP0_ENTRYLO11 $3,0 /* LS TLB entry for odd-numbered pages */
# define MIPS32_CP0_CONTEXT2 $4,0 /* Page table address */
# define MIPS32_CP0_PAGEMASK1 $5,0 /* Variable page sizes in TLB entries */
# define MIPS32_CP0_WIRED1 $6,0 /* umber of fixed (“wired”) TLB entries */
# define MIPS32_CP0_WIRED1 $6,0 /* Number of fixed ('wired') TLB entries */
# define MIPS32_CP0_BADVADDR $8,0 /* Address of most recent exception */
# define MIPS32_CP0_COUNT $9,0 /* Processor cycle count */
# define MIPS32_CP0_ENTRYHI1 $10,0 /* High-order portion of the TLB entry */
@ -140,7 +140,7 @@
# define CP0_PAGEMASK_256MB (0xffff << CP0_PAGEMASK_SHIFT)
/* Register Number: 6 Sel: 0 Name: Wired
* Function: Controls the number of fixed (“wired”) TLB entries
* Function: Controls the number of fixed ('wired') TLB entries
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*
* This is a 32-bit register containing the TLB wired boundary.
@ -232,7 +232,7 @@
#define CP0_STATUS_TS (1 << 21) /* Bit 21: TLB detected match on multiple entries */
#define CP0_STATUS_BEV (1 << 22) /* Bit 22: Location of exception vectors 1->Bootstrap */
#define CP0_STATUS_PX (1 << 23) /* Bit 23: Enables 64-bit operations (Not MIPS32) */
#define CP0_STATUS_MX (1 << 24) /* Bit 24: Enables MDMX™ (Not MIPS32) */
#define CP0_STATUS_MX (1 << 24) /* Bit 24: Enables MDMX™ (Not MIPS32) */
#define CP0_STATUS_RE (1 << 25) /* Bit 25: Enable reverse-endian memory in user mode */
#define CP0_STATUS_FR (1 << 26) /* Bit 26: Controls the floating point register mode (Not MIPS32) */
#define CP0_STATUS_RP (1 << 27) /* Bit 27: Enables reduced power mode */
@ -432,12 +432,12 @@
*/
#define CP0_CONFIG3_TL (1 << 0) /* Bit 0: Trace Logic implemented */
#define CP0_CONFIG3_SM (1 << 1) /* Bit 1: SmartMIPS™ ASE implemented */
#define CP0_CONFIG3_SM (1 << 1) /* Bit 1: SmartMIPS™ ASE implemented */
#define CP0_CONFIG3_CDMM (1 << 3) /* Bit 3: Common Device Memory Map */
#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Small page bit */
#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */
#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */
#define CP0_CONFIG3_ITL (1 << 8) /* Bit 8: Flowtrace® Hardware bit */
#define CP0_CONFIG3_ITL (1 << 8) /* Bit 8: Flowtrace® Hardware bit */
#define CP0_CONFIG3_DSPP (1 << 10) /* Bit 10: MIPS DSP ASE Presence bit */
#define CP0_CONFIG3_DSP2 (1 << 11) /* Bit 11: MIPS DSP ASE Revision 2 Presence bit */
#define CP0_CONFIG3_RXI (1 << 12) /* Bit 12: RIE and XIE Implemented in PageGrain bit */

2
arch/mips/include/pic32mx/cp0.h
View File

@ -115,7 +115,7 @@
* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
* CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32)
* CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32)
*/
#undef CP0_STATUS_UX

2
arch/mips/src/pic32mx/pic32mx_devcfg.h
View File

@ -51,7 +51,7 @@
/* Device configuration word 3 */
#define DEVCFG3_USERID_SHIFT (0) /* Bits 0-15: User-defined, readable via ICSP™ and JTAG */
#define DEVCFG3_USERID_SHIFT (0) /* Bits 0-15: User-defined, readable via ICSP™ and JTAG */
#define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT)
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)

2
arch/x86/include/i486/irq.h
View File

@ -76,7 +76,7 @@
#define IRQ0 32 /* System timer (cannot be changed) */
#define IRQ1 33 /* Keyboard controller (cannot be changed) */
#define IRQ2 34 /* Cascaded signals from IRQs 8–15 */
#define IRQ2 34 /* Cascaded signals from IRQs 8-15 */
#define IRQ3 35 /* Serial port controller for COM2/4 */
#define IRQ4 36 /* serial port controller for COM1/3 */
#define IRQ5 37 /* LPT port 2 or sound card */

2
arch/z80/include/z180/chip.h
View File

@ -387,7 +387,7 @@
* External Memory - 1
* Voltage Range - 5.0V
* Communications Controller - CSIO, UART
* Other Features - 1MB MMU, 2xDMA’s, 2xUARTs
* Other Features - 1MB MMU, 2xDMAs, 2xUARTs
* Speed (MHz) - 20, 10, 33
* Core / CPU Used - Z180
* Pin Count - 64, 68, 80

4
arch/z80/include/z180/irq.h
View File

@ -74,10 +74,10 @@
/* INT0
*
* INT0 (only) has 3 different software programmable interrupt response
* modes—Mode 0, Mode 1 and Mode 2.
* modes: Mode 0, Mode 1 and Mode 2.
*
* - INT0 Mode 0. During the interrupt acknowledge cycle, an instruction
* is fetched from the data bus (DO–D7) at the rising edge of T3.
* is fetched from the data bus (DO-D7) at the rising edge of T3.
*
* - INT0 Mode 1. The PC is stacked and instruction execution restarts at
* logical address 0x0038.

2
boards/arm/a1x/pcduino-a10/README.txt
View File

@ -56,7 +56,7 @@ README
(See http://www.allwinnertech.com/en/product/a10.html):
CPU
- ARM Cortex™-A8
- ARM Cortex™-A8
- 32KB I-Cache
- 32KB D-Cache
- 256KB L2 Cache

2
boards/arm/imx6/sabre-6quad/README.txt
View File

@ -213,7 +213,7 @@ Debug:
- JTAG connector (20-pin)
- 1x Serial-to-USB connector (for JTAG)
OS Support:
- Linux® and Android™ from NXP/Freescale
- Linux® and Android™ from NXP/Freescale
- Others supported via third party (QNX, Windows Embedded)
Tools Support:
- Manufacturing tool from NXP/Freescale

2
boards/arm/kinetis/twr-k60n512/README.txt
View File

@ -35,7 +35,7 @@ Kinetis TWR-K60N512 Features:
o Touch TWRPI Socket adds support for various capacitive touch boards
(e.g. keypads, rotary dials, sliders, etc.)
o Tower connectivity for access to USB, Ethernet, RS232/RS485, CAN, SPI,
I²C, Flexbus, etc.
I²C, Flexbus, etc.
o Plus: Potentiometer, 4 LEDs, 2 pushbuttons, infrared port
Kinetis TWR-K60N512 Pin Configuration

2
boards/arm/lpc31xx/ea3131/src/lpc31_clkinit.c
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

8
boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
@ -100,12 +100,12 @@
* undefined operation. Once power is applied to VDD and VDDQ
* (simultaneously) and the clock is stable (stable clock is defined as
* a signal cycling within timing constraints specified for the clock
* pin), the SDRAM requires a 100µs delay prior to issuing any command
* pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP.
*
* "Starting at some point during this 100µs period and continuing at least
* "Starting at some point during this 100µs period and continuing at least
* through the end of this period, COMMAND INHIBIT or NOP commands should
* be applied. Once the 100µs delay has been satisfied with at least one
* be applied. Once the 100µs delay has been satisfied with at least one
* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
* should be applied. All banks must then be precharged, thereby placing
* the device in the all banks idle state.

10
boards/arm/lpc31xx/ea3131/tools/lpchdr.h
View File

@ -46,13 +46,13 @@ struct lpc31_header_s
* valid image header. This field should always
* be set to 0x41676d69. */
uint32_t execution_crc32; /* 0x08 CRC32 value of execution part of the image. If
* the ‘image_type’ is set to ‘0xA’, this field
* the 'image_type' is set to '0xA', this field
* is ignored by boot ROM. */
uint32_t reserved0[4]; /* 0x0c-0x18: Should be zero. */
uint32_t imagetype; /* 0x1c Specifies whether CRC check should be done
* on the image or not:
* 0xA – No CRC check required.
* 0xB – Do CRC32 check on both header and
* 0xA - No CRC check required.
* 0xB - Do CRC32 check on both header and
* execution part of the image. */
uint32_t imagelength; /* 0x20 Total image length including header rounded
* up to the nearest 512 byte boundary. In C
@ -68,8 +68,8 @@ struct lpc31_header_s
uint32_t sbzbootparameter; /* 0x2c hould be zero. */
uint32_t cust_reserved[15]; /* 0x30-0x68: Reserved for customer use (60 bytes) */
uint32_t header_crc32; /* 0x6c CRC32 value of the header (bytes 0x00 to 0x6C
* of the image). If the ‘image_type’ is set
* to ‘0xA’, this field is ignored by boot ROM. */
* of the image). If the 'image_type' is set
* to '0xA', this field is ignored by boot ROM. */
uint32_t reserved1[4]; /* 0x70-0x7c: Should be zero. */
/* 0x80 Start of program code (128Kb max). The final
* image has to be padded to the nearest 512

2
boards/arm/lpc31xx/ea3152/src/lpc31_clkinit.c
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

8
boards/arm/lpc31xx/ea3152/src/lpc31_mem.c
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
@ -100,12 +100,12 @@
* undefined operation. Once power is applied to VDD and VDDQ
* (simultaneously) and the clock is stable (stable clock is defined as
* a signal cycling within timing constraints specified for the clock
* pin), the SDRAM requires a 100µs delay prior to issuing any command
* pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP.
*
* "Starting at some point during this 100µs period and continuing at least
* "Starting at some point during this 100µs period and continuing at least
* through the end of this period, COMMAND INHIBIT or NOP commands should
* be applied. Once the 100µs delay has been satisfied with at least one
* be applied. Once the 100µs delay has been satisfied with at least one
* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
* should be applied. All banks must then be precharged, thereby placing
* the device in the all banks idle state.

10
boards/arm/lpc31xx/ea3152/tools/lpchdr.h
View File

@ -48,15 +48,15 @@ struct lpc31_header_s
* should always be set to 0x41676d69.
*/
uint32_t execution_crc32; /* 0x08 CRC32 value of execution part of
* the image. If the ‘image_type’ is set
* to ‘0xA’, this field is ignored by boot
* the image. If the 'image_type' is set
* to '0xA', this field is ignored by boot
* ROM.
*/
uint32_t reserved0[4]; /* 0x0c-0x18: Should be zero. */
uint32_t imagetype; /* 0x1c Specifies whether CRC check should be
* done on the image or not:
* 0xA – No CRC check required.
* 0xB – Do CRC32 check on both header and
* 0xA - No CRC check required.
* 0xB - Do CRC32 check on both header and
* execution part of the image.
*/
uint32_t imagelength; /* 0x20 Total image length including header
@ -82,7 +82,7 @@ struct lpc31_header_s
*/
uint32_t header_crc32; /* 0x6c CRC32 value of the header
* (bytes 0x00 to 0x6C of the image).
* If the ‘image_type’ is set to ‘0xA’,
* If the 'image_type' is set to '0xA',
* this field is ignored by boot ROM.
*/
uint32_t reserved1[4]; /* 0x70-0x7c: Should be zero. */

2
boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_clkinit.c
View File

@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

10
boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h
View File

@ -46,13 +46,13 @@ struct lpc31_header_s
* valid image header. This field should always
* be set to 0x41676d69. */
uint32_t execution_crc32; /* 0x08 CRC32 value of execution part of the image. If
* the ‘image_type’ is set to ‘0xA’, this field
* the 'image_type' is set to '0xA', this field
* is ignored by boot ROM. */
uint32_t reserved0[4]; /* 0x0c-0x18: Should be zero. */
uint32_t imagetype; /* 0x1c Specifies whether CRC check should be done
* on the image or not:
* 0xA – No CRC check required.
* 0xB – Do CRC32 check on both header and
* 0xA - No CRC check required.
* 0xB - Do CRC32 check on both header and
* execution part of the image. */
uint32_t imagelength; /* 0x20 Total image length including header rounded
* up to the nearest 512 byte boundary. In C
@ -68,8 +68,8 @@ struct lpc31_header_s
uint32_t sbzbootparameter; /* 0x2c hould be zero. */
uint32_t cust_reserved[15]; /* 0x30-0x68: Reserved for customer use (60 bytes) */
uint32_t header_crc32; /* 0x6c CRC32 value of the header (bytes 0x00 to 0x6C
* of the image). If the ‘image_type’ is set
* to ‘0xA’, this field is ignored by boot ROM. */
* of the image). If the 'image_type' is set
* to '0xA', this field is ignored by boot ROM. */
uint32_t reserved1[4]; /* 0x70-0x7c: Should be zero. */
/* 0x80 Start of program code (128Kb max). The final
* image has to be padded to the nearest 512

4
boards/arm/sama5/sama5d2-xult/include/board_384mhz.h
View File

@ -102,7 +102,7 @@
*
* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
* full-speed operations. These clocks must be generated by a PLL with a
* correct accuracy of ± 0.25% thanks to USBDIV field.
* correct accuracy of ± 0.25% thanks to USBDIV field.
*
* "Thus the USB Host peripheral receives three clocks from the Power
* Management Controller (PMC): the Peripheral Clock (MCK domain), the
@ -142,7 +142,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d2-xult/include/board_396mhz.h
View File

@ -98,7 +98,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d2-xult/include/board_528mhz.h
View File

@ -97,7 +97,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d2-xult/include/board_sdram.h
View File

@ -107,7 +107,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* HSMCI clocking

4
boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h
View File

@ -103,7 +103,7 @@
*
* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
* full-speed operations. These clocks must be generated by a PLL with a
* correct accuracy of ± 0.25% thanks to USBDIV field.
* correct accuracy of ± 0.25% thanks to USBDIV field.
*
* "Thus the USB Host peripheral receives three clocks from the Power
* Management Controller (PMC): the Peripheral Clock (MCK domain), the
@ -143,7 +143,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h
View File

@ -100,7 +100,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h
View File

@ -99,7 +99,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d3-xplained/include/board_sdram.h
View File

@ -111,7 +111,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* HSMCI clocking

2
boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c
View File

@ -166,7 +166,7 @@ void weak_function sam_netinitialize(void)
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential
* pair signals designated from GRX± and GTx± plus control signals for link
* pair signals designated from GRX± and GTx± plus control signals for link
* activity indicators. These signals can be used to connect to a
* 10/100/1000 BaseT RJ45 connector integrated on the main board.
*

2
boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c
View File

@ -137,7 +137,7 @@ static inline void sam_sdram_delay(unsigned int loops)
* Per the SAMA5D3-Xplained User guide:
* "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte).
* The board includes 2 Gbits of on-board soldered DDR2 (double data rate)
* SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron®
* SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron®
* for a total of 512 MBytes of DDR2 memory.
* The memory bus is 32 bits wide and operates with a frequency of up
* to 166 MHz."

4
boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h
View File

@ -104,7 +104,7 @@
*
* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
* full-speed operations. These clocks must be generated by a PLL with a
* correct accuracy of ± 0.25% thanks to USBDIV field.
* correct accuracy of ± 0.25% thanks to USBDIV field.
*
* "Thus the USB Host peripheral receives three clocks from the Power
* Management Controller (PMC): the Peripheral Clock (MCK domain), the
@ -144,7 +144,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h
View File

@ -100,7 +100,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h
View File

@ -99,7 +99,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d3x-ek/include/board_sdram.h
View File

@ -110,7 +110,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* HSMCI clocking

2
boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c
View File

@ -166,7 +166,7 @@ void weak_function sam_netinitialize(void)
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential
* pair signals designated from GRX± and GTx± plus control signals for link
* pair signals designated from GRX± and GTx± plus control signals for link
* activity indicators. These signals can be used to connect to a
* 10/100/1000 BaseT RJ45 connector integrated on the main board.
*

4
boards/arm/sama5/sama5d4-ek/include/board_384mhz.h
View File

@ -102,7 +102,7 @@
*
* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
* full-speed operations. These clocks must be generated by a PLL with a
* correct accuracy of ± 0.25% thanks to USBDIV field.
* correct accuracy of ± 0.25% thanks to USBDIV field.
*
* "Thus the USB Host peripheral receives three clocks from the Power
* Management Controller (PMC): the Peripheral Clock (MCK domain), the
@ -142,7 +142,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d4-ek/include/board_396mhz.h
View File

@ -98,7 +98,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d4-ek/include/board_528mhz.h
View File

@ -97,7 +97,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */

2
boards/arm/sama5/sama5d4-ek/include/board_sdram.h
View File

@ -106,7 +106,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* HSMCI clocking

2
boards/arm/sama5/sama5d4-ek/src/sam_sdram.c
View File

@ -274,7 +274,7 @@ static void sam_config_slaveddr(void)
* "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte).
* The board includes 2 Gbits of on-board solderedDDR2 (double data rate)
* SDRAM. The footprints can also host two DDR2 (MT47H128M16RT) from
* Micron® for a total of 512 MBytes of DDR2 memory. The memory bus is 32
* Micron® for a total of 512 MBytes of DDR2 memory. The memory bus is 32
* bits wide and operates with a frequency of up to 166 MHz."
*
* From the Atmel Code Example:

6
boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h
View File

@ -536,9 +536,9 @@
*
* - 7 inch LCD at 800x480 18-bit RGB resolution and white backlight
* - Projected Capacitive Multi-Touch Controller based on the Atmel
* MXT768E maXTouch™ IC
* - 4 Capacitive “Navigation” Keys available via an Atmel AT42QT1070
* QTouch™ Button Sensor IC
* MXT768E maXTouch™ IC
* - 4 Capacitive "Navigation" Keys available via an Atmel AT42QT1070
* QTouch™ Button Sensor IC
* - 200 bytes of non-volatile serial EEPROM
*
* Both the MXT768E and the AT42QT1070 are I2C devices with interrupting

8
boards/arm/samd2l2/samd20-xplained/README.txt
View File

@ -108,10 +108,10 @@ Modules
10 microSD_DETECT 10 PB05 GPIO 10 PB15 GPIO
----------------- ---------------------- ---------------------- ------------------------------------
11 TWI SDA 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0] EXT1, EXT2, EXT3 and EDBG
I²C SDA I²C SDA
I²C SDA I²C SDA
----------------- ---------------------- ---------------------- ------------------------------------
12 TWI SCL 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1] EXT2, EXT3 and EDBG
I²C SCL I²C SCL
I²C SCL I²C SCL
----------------- ---------------------- ---------------------- ------------------------------------
13 USART RX 13 PB09 SERCOM4 PAD[1] 13 PB13 SERCOM4 PAD[1] The SERCOM4 module is shared between
USART RX USART RX EXT1, 2 and 3 USART's, but uses
@ -221,10 +221,10 @@ Modules
10 DISPLAY_RESET 10 PB05 GPIO 10 PB15 GPIO
----------------- ---------------------- ---------------------- ------------------------------------
11 N/C 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0] EXT1, EXT2, EXT3 and EDBG
I²C SDA I²C SDA
I²C SDA I²C SDA
----------------- ---------------------- ---------------------- ------------------------------------
12 N/C 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1] EXT2, EXT3 and EDBG
I²C SCL I²C SCL
I²C SCL I²C SCL
----------------- ---------------------- ---------------------- ------------------------------------
13 N/C 13 PB09 SERCOM4 PAD[1] 13 PB13 SERCOM4 PAD[1] The SERCOM4 module is shared between
USART RX USART RX EXT1, 2 and 3 USART's, but uses

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