arch/risc-v: remove g_cpux_idlestack

As all the board allocate idle stack from _ebss. The idle stack
layout is fix and can be computed directly by using _ebss. There
is no need to use g_cpux_idlestack array anymore, remove it.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>

arch/risc-v/src/bl602/bl602_start.c

@@ -148,10 +148,6 @@ void bfl_main(void)
 
   asm volatile("csrw mtvec, %0" ::"r"((uintptr_t)exception_common + 2));
 
-  /* Setup base stack */
-
-  riscv_set_basestack((uintptr_t)_ebss, SMP_STACK_SIZE);
-
   /* Configure the UART so we can get debug output */
 
   bl602_lowsetup();

arch/risc-v/src/bl808/bl808_start.c

@@ -267,10 +267,6 @@ void bl808_start(int mhartid)
 
       bl808_clear_bss();
 
-      /* Setup base stack */
-
-      riscv_set_basestack(BL808_IDLESTACK_BASE, SMP_STACK_SIZE);
-
       /* Copy the RAM Disk */
 
       bl808_copy_ramdisk();

arch/risc-v/src/c906/c906_start.c

@@ -79,10 +79,6 @@ void __c906_start(uint32_t mhartid)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack(C906_IDLESTACK_BASE, SMP_STACK_SIZE);
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the

arch/risc-v/src/common/espressif/esp_start.c

@@ -453,10 +453,6 @@ void __esp_start(void)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack((uintptr_t)_ebss, SMP_STACK_SIZE);
-
   /* Setup the syscall table needed by the ROM code */
 
   esp_setup_syscall_table();

arch/risc-v/src/common/riscv_common_memorymap.h

@@ -67,7 +67,8 @@ EXTERN uintptr_t g_idle_topstack;
 
 /* Address of per-cpu idle stack base */
 
-EXTERN const uint8_t *g_cpux_idlestack[CONFIG_SMP_NCPUS];
+#define g_cpux_idlestack(cpuid) \
+   (g_idle_topstack - SMP_STACK_SIZE * ((cpuid) + 1))
 
 /* Address of the saved user stack pointer */
 

arch/risc-v/src/common/riscv_cpuidlestack.c

@@ -50,8 +50,6 @@
 uintptr_t g_idle_topstack = (uintptr_t)_ebss +
                                        SMP_STACK_SIZE * CONFIG_SMP_NCPUS;
 
-const uint8_t *g_cpux_idlestack[CONFIG_SMP_NCPUS];
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -109,7 +107,7 @@ int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size)
 
   /* Get the top of the stack */
 
-  stack_alloc = (uintptr_t)g_cpux_idlestack[cpu];
+  stack_alloc = (uintptr_t)g_cpux_idlestack(cpu);
   DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc));
 
   tcb->adj_stack_size  = SMP_STACK_SIZE;

arch/risc-v/src/common/riscv_initialstate.c

@@ -97,7 +97,7 @@ void up_initial_state(struct tcb_s *tcb)
 
   if (tcb->pid == IDLE_PROCESS_ID)
     {
-      tcb->stack_alloc_ptr = (void *)g_cpux_idlestack[riscv_mhartid()];
+      tcb->stack_alloc_ptr = (void *)g_cpux_idlestack(riscv_mhartid());
       tcb->stack_base_ptr  = tcb->stack_alloc_ptr;
       tcb->adj_stack_size  = SMP_STACK_SIZE;
 

arch/risc-v/src/common/riscv_internal.h

@@ -331,18 +331,6 @@ int riscv_check_pmp_access(uintptr_t attr, uintptr_t base, uintptr_t size);
 int riscv_configured_pmp_regions(void);
 int riscv_next_free_pmp_region(void);
 
-/* RISC-V Memorymap Config **************************************************/
-
-static inline void riscv_set_basestack(uintptr_t base, uintptr_t size)
-{
-  unsigned int i;
-
-  for (i = 0; i < CONFIG_SMP_NCPUS; i++)
-    {
-      g_cpux_idlestack[i] = (const uint8_t *)(base + size * i);
-    }
-}
-
 /* RISC-V SBI wrappers ******************************************************/
 
 #ifdef CONFIG_ARCH_USE_S_MODE

arch/risc-v/src/esp32c3-legacy/esp32c3_start.c

@@ -288,10 +288,6 @@ void __esp32c3_start(void)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack((uintptr_t)_ebss, SMP_STACK_SIZE);
-
   /* Setup the syscall table needed by the ROM code */
 
   setup_syscall_table();

arch/risc-v/src/fe310/fe310_start.c

@@ -69,10 +69,6 @@ void __fe310_start(void)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack(FE310_IDLESTACK_BASE, SMP_STACK_SIZE);
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the

arch/risc-v/src/hpm6000/hpm_start.c

@@ -64,10 +64,6 @@ void __hpm_start(void)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack(HPM_IDLESTACK_BASE, CONFIG_IDLETHREAD_STACKSIZE);
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the

arch/risc-v/src/hpm6750/hpm6750_start.c

@@ -64,10 +64,6 @@ void __hpm6750_start(void)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack(HPM6750_IDLESTACK_BASE, SMP_STACK_SIZE);
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the

arch/risc-v/src/jh7110/jh7110_start.c

@@ -133,10 +133,6 @@ void jh7110_start(int mhartid)
     {
       jh7110_clear_bss();
 
-      /* Setup base stack */
-
-      riscv_set_basestack(JH7110_IDLESTACK_BASE, SMP_STACK_SIZE);
-
       /* Initialize the per CPU areas */
 
       riscv_percpu_add_hart(mhartid);

arch/risc-v/src/k210/k210_start.c

@@ -79,10 +79,6 @@ void __k210_start(uint32_t mhartid)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack(K210_IDLESTACK_BASE, SMP_STACK_SIZE);
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the

arch/risc-v/src/k230/k230_start.c

@@ -115,8 +115,6 @@ void k230_start(int mhartid, const char *dtb)
     {
       k230_clear_bss();
 
-      riscv_set_basestack(K230_IDLESTACK_BASE, SMP_STACK_SIZE);
-
 #ifdef CONFIG_RISCV_PERCPU_SCRATCH
       riscv_percpu_add_hart(mhartid);
 #else

arch/risc-v/src/litex/litex_start.c

@@ -81,10 +81,6 @@ void __litex_start(int hart_index, const void * fdt, int arg)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack(LITEX_IDLESTACK_BASE, SMP_STACK_SIZE);
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the

arch/risc-v/src/mpfs/mpfs_start.c

@@ -86,10 +86,6 @@ void __mpfs_start(uint64_t mhartid)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack(MPFS_IDLESTACK_BASE, MPFS_IDLESTACK_SIZE);
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the

arch/risc-v/src/qemu-rv/qemu_rv_start.c

@@ -140,8 +140,6 @@ void qemu_rv_start(int mhartid, const char *dtb)
 
   qemu_rv_clear_bss();
 
-  riscv_set_basestack(QEMU_RV_IDLESTACK_BASE, SMP_STACK_SIZE);
-
 #ifdef CONFIG_RISCV_PERCPU_SCRATCH
   riscv_percpu_add_hart(mhartid);
 #endif

arch/risc-v/src/rv32m1/rv32m1_start.c

@@ -101,10 +101,6 @@ void __rv32m1_start(void)
       *dest++ = 0;
     }
 
-  /* Setup base stack */
-
-  riscv_set_basestack(RV32M1_IDLESTACK_BASE, RV32M1_IDLESTACK_TOP);
-
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the