Add peripheral configuration logic for the SAM3X/3A; Change all references to SAM3/4 SPI to SPI0 for compatibity with the SAM3X/3A which has SPI0 and SPI1; Add directory which will eventually holdl an Arduino Due port

2013-06-26 18:46:44 -06:00 · 2013-06-26 18:46:44 -06:00 · bc7ac20616
commit bc7ac20616
parent d4b7efb34e
42 changed files with 825 additions and 138 deletions
--- a/8
+++ b/8
@ -5067,4 +5067,12 @@
 	* arch/arm/src/sam34/sam3x_gpio.h:  Add SAM3X/3A gpio encoding
 	  macros.  These differ from the SAM3U only in because of the
 	  6 PIOs:  PIOA-PIOF (2013-6-26).
+	* configs/arduino-due:  This is an empty directory now with only
+	  a README file in it but this directory will eventually hold a port
+	  for the Arduino Due (2013-6-26).
+	* arch/arm/src/sam34/Kconfig:  Add SAM3X/3A peripherals to the SAM3/4
+	  configuration logic (2013-6-26).
+	* arch/arm/src and include/ and configs/sam*/:  Large rename of all
+	  references to SPI with SPI0.  This is because all other SAMs have
+	  only SPI but the 3X/3A have SPI0 and SPI1 (2013-6-26).

--- a/arch/arm/include/sam34/chip.h
+++ b/arch/arm/include/sam34/chip.h
@ -95,7 +95,7 @@
 * HSMCI        8 bit    4 bit    8 bit    4 bit    4 bit    4 bit
 */

-#if defined(CONFIG_ARCH_CHIP_AT91SAM3X8E)
+#elif defined(CONFIG_ARCH_CHIP_AT91SAM3X8E)

 /* Internal memory */

--- a/arch/arm/include/sam34/sam3u_irq.h
+++ b/arch/arm/include/sam34/sam3u_irq.h
@ -70,7 +70,7 @@
 #define SAM_PID_HSMCI         (17)  /* High Speed Multimedia Card Interface */
 #define SAM_PID_TWI0          (18)  /* Two-Wire Interface 0 */
 #define SAM_PID_TWI1          (19)  /* Two-Wire Interface 1 */
-#define SAM_PID_SPI           (20)  /* Serial Peripheral Interface */
+#define SAM_PID_SPI0          (20)  /* Serial Peripheral Interface */
 #define SAM_PID_SSC           (21)  /* Synchronous Serial Controller */
 #define SAM_PID_TC0           (22)  /* Timer Counter 0 */
 #define SAM_PID_TC1           (23)  /* Timer Counter 1 */
@ -104,7 +104,7 @@
 #define SAM_IRQ_HSMCI         (SAM_IRQ_EXTINT+SAM_PID_HSMCI)  /* High Speed Multimedia Card Interface */
 #define SAM_IRQ_TWI0          (SAM_IRQ_EXTINT+SAM_PID_TWI0)   /* Two-Wire Interface 0 */
 #define SAM_IRQ_TWI1          (SAM_IRQ_EXTINT+SAM_PID_TWI1)   /* Two-Wire Interface 1 */
-#define SAM_IRQ_SPI           (SAM_IRQ_EXTINT+SAM_PID_SPI)    /* Serial Peripheral Interface */
+#define SAM_IRQ_SPI0          (SAM_IRQ_EXTINT+SAM_PID_SPI0)   /* Serial Peripheral Interface */
 #define SAM_IRQ_SSC           (SAM_IRQ_EXTINT+SAM_PID_SSC)    /* Synchronous Serial Controller */
 #define SAM_IRQ_TC0           (SAM_IRQ_EXTINT+SAM_PID_TC0)    /* Timer Counter 0 */
 #define SAM_IRQ_TC1           (SAM_IRQ_EXTINT+SAM_PID_TC1)    /* Timer Counter 1 */
--- a/arch/arm/include/sam34/sam4l_irq.h
+++ b/arch/arm/include/sam34/sam4l_irq.h
@ -57,7 +57,7 @@
 #define SAM_PID_USART1_RHR     (1)   /* DIR=RX REGISTER: USART1 RHR */
 #define SAM_PID_USART2_RHR     (2)   /* DIR=RX REGISTER: USART2 RHR */
 #define SAM_PID_USART3_RHR     (3)   /* DIR=RX REGISTER: USART3 RHR */
-#define SAM_PID_SPI_RDR        (4)   /* DIR=RX REGISTER: SPI RDR */
+#define SAM_PID_SPI0_RDR       (4)   /* DIR=RX REGISTER: SPI RDR */
 #define SAM_PID_TWIM0_RHR      (5)   /* DIR=RX REGISTER: TWIM0 RHR */
 #define SAM_PID_TWIM1_RHR      (6)   /* DIR=RX REGISTER: TWIM1 RHR */
 #define SAM_PID_TWIM2_RHR      (7)   /* DIR=RX REGISTER: TWIM2 RHR */
@ -75,7 +75,7 @@
 #define SAM_PID_USART1_THR     (19)  /* DIR=TX REGISTER: USART1 THR */
 #define SAM_PID_USART2_THR     (20)  /* DIR=TX REGISTER: USART2 THR */
 #define SAM_PID_USART3_THR     (21)  /* DIR=TX REGISTER: USART3 THR */
-#define SAM_PID_SPI_TDR        (22)  /* DIR=TX REGISTER: SPI TDR */
+#define SAM_PID_SPI0_TDR       (22)  /* DIR=TX REGISTER: SPI TDR */
 #define SAM_PID_TWIM0_THR      (23)  /* DIR=TX REGISTER: TWIM0 THR */
 #define SAM_PID_TWIM1_THR      (24)  /* DIR=TX REGISTER: TWIM1 THR */
 #define SAM_PID_TWIM2_THR      (25)  /* DIR=TX REGISTER: TWIM2 THR */
@ -149,7 +149,7 @@
 #define SAM_IRQ_EIC7           (SAM_IRQ_EXTINT+51)   /* 51 External Interrupt Controller 7 */
 #define SAM_IRQ_EIC8           (SAM_IRQ_EXTINT+52)   /* 52 External Interrupt Controller 8 */
 #define SAM_IRQ_IISC           (SAM_IRQ_EXTINT+53)   /* 53 Inter-IC Sound (I2S) Controller */
-#define SAM_IRQ_SPI            (SAM_IRQ_EXTINT+54)   /* 54 Serial Peripheral Interface */
+#define SAM_IRQ_SPI0           (SAM_IRQ_EXTINT+54)   /* 54 Serial Peripheral Interface */
 #define SAM_IRQ_TC00           (SAM_IRQ_EXTINT+55)   /* 55 Timer/Counter 0 */
 #define SAM_IRQ_TC01           (SAM_IRQ_EXTINT+56)   /* 56 Timer/Counter 1 */
 #define SAM_IRQ_TC02           (SAM_IRQ_EXTINT+57)   /* 57 Timer/Counter 2 */
--- a/arch/arm/include/sam34/sam4s_irq.h
+++ b/arch/arm/include/sam34/sam4s_irq.h
@ -71,7 +71,7 @@
 #define SAM_PID_HSMCI        (18)  /* High Speed Multimedia Card Interface */
 #define SAM_PID_TWI0         (19)  /* Two-Wire Interface 0 */
 #define SAM_PID_TWI1         (20)  /* Two-Wire Interface 1 */
-#define SAM_PID_SPI          (21)  /* Serial Peripheral Interface */
+#define SAM_PID_SPI0         (21)  /* Serial Peripheral Interface */
 #define SAM_PID_SSC          (22)  /* Synchronous Serial Controller */
 #define SAM_PID_TC0          (23)  /* Timer Counter 0 */
 #define SAM_PID_TC1          (24)  /* Timer Counter 1 */
@ -110,7 +110,7 @@
 #define SAM_IRQ_HSMCI        (SAM_IRQ_EXTINT+SAM_PID_HSMCI)       /* PID 18: High Speed Multimedia Card Interface */
 #define SAM_IRQ_TWI0         (SAM_IRQ_EXTINT+SAM_PID_TWI0)        /* PID 19: Two-Wire Interface 0 */
 #define SAM_IRQ_TWI1         (SAM_IRQ_EXTINT+SAM_PID_TWI1)        /* PID 20: Two-Wire Interface 1 */
-#define SAM_IRQ_SPI          (SAM_IRQ_EXTINT+SAM_PID_SPI)         /* PIC 21: Serial Peripheral Interface */
+#define SAM_IRQ_SPI0         (SAM_IRQ_EXTINT+SAM_PID_SPI0)        /* PIC 21: Serial Peripheral Interface */
 #define SAM_IRQ_SSC          (SAM_IRQ_EXTINT+SAM_PID_SSC)         /* PID 22: Synchronous Serial Controller */
 #define SAM_IRQ_TC0          (SAM_IRQ_EXTINT+SAM_PID_TC0)         /* PID 23: Timer Counter 0 */
 #define SAM_IRQ_TC1          (SAM_IRQ_EXTINT+SAM_PID_TC1)         /* PID 24: Timer Counter 1 */
--- a/arch/arm/src/sam34/Kconfig
+++ b/arch/arm/src/sam34/Kconfig
@ -222,14 +222,19 @@ config SAM34_IISC
 	default n
 	depends on ARCH_CHIP_SAM4L

-config SAM34_SPI
-	bool "Serial Peripheral Interface (SPI)"
+config SAM34_SPI0
+	bool "Serial Peripheral Interface 0 (SPI0)"
 	default n

+config SAM34_SPI1
+	bool "Serial Peripheral Interface 1 (SPI1)"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+
 config SAM34_SSC
 	bool "Synchronous Serial Controller (SSC)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S

 config SAM34_TC0
 	bool "Timer/Counter 0 (TC0)"
@ -242,27 +247,42 @@ config SAM34_TC1
 config SAM34_TC2
 	bool "Timer/Counter 2 (TC2)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S

 config SAM34_TC3
 	bool "Timer/Counter 3 (TC3)"
 	default n
-	depends on ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S

 config SAM34_TC4
 	bool "Timer/Counter 4 (TC4)"
 	default n
-	depends on ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S

 config SAM34_TC5
 	bool "Timer/Counter 5 (TC5)"
 	default n
-	depends on ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S
+
+config SAM34_TC6
+	bool "Timer/Counter 6 (TC6)"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+
+config SAM34_TC7
+	bool "Timer/Counter 7 (TC6)"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+
+config SAM34_TC8
+	bool "Timer/Counter 6 (TC8)"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A

 config SAM34_PWM
 	bool "Pulse Width Modulation (PWM) Controller"
 	default n
-	depends on ARCH_CHIP_SAM3U|| ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S

 config SAM34_TWIM0
 	bool "Two-wire Master Interface 0 (TWIM0)"
@ -293,7 +313,7 @@ config SAM34_TWIM3
 config SAM34_UART0
 	bool "UART 0"
 	default y
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S
 	select ARCH_HAVE_UART0

 config SAM34_UART1
@ -322,13 +342,13 @@ config SAM34_USART2
 	bool "USART 2"
 	default n
 	select ARCH_HAVE_USART2
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L

 config SAM34_USART3
 	bool "USART 3"
 	default n
 	select ARCH_HAVE_USART3
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L

 config SAM34_ADC12B
 	bool "12-bit ADC Controller"
@ -342,7 +362,7 @@ config SAM34_ADC
 config SAM34_DACC
 	bool "Digital To Analog Converter (DAC)"
 	default n
-	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S

 config SAM34_ACC
 	bool "Analog Comparator (AC)"
@ -362,7 +382,22 @@ config SAM34_ABDACB
 config SAM34_TRNG
 	bool "True Random Number Generator (TRNG)"
 	default n
-	depends on ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
+
+config SAM34_EMAC
+	bool "Ethernet MAC (EMAC)"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+
+config SAM34_CAN0
+	bool "CAN0"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+
+config SAM34_CAN1
+	bool "CAN1"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A

 config SAM34_PARC
 	bool "Parallel Capture (PARC)"
@ -387,7 +422,12 @@ config SAM34_HRAMC1
 config SAM34_SMC
 	bool "Static Memory Controller (SMC)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S
+
+config SAM34_SDRAMC
+	bool "SDRAM Controller (SDRAMC)"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A

 config SAM34_NAND
 	bool "NAND support"
@ -408,7 +448,7 @@ config SAM34_PDCA
 config SAM34_DMA
 	bool "DMA controller"
 	default n
-	depends on ARCH_CHIP_SAM3U
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
 	select ARCH_DMA

 config SAM34_CRCCU
@ -421,6 +461,11 @@ config SAM34_UDPHS
 	default n
 	depends on ARCH_CHIP_SAM3U

+config SAM34_UOTGHS
+	bool "USB OTG High Speed"
+	default n
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X
+
 config SAM34_UDP
 	bool "USB Device Full Speed"
 	default n
@ -454,12 +499,12 @@ config SAM34_AST
 config SAM34_RTC
 	bool "Real Time Clock (RTC)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S

 config SAM34_RTT
 	bool "Real Time Timer (RTT)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S

 config SAM34_WDT
 	bool "Watchdog Timer (WDT)"
@ -473,7 +518,7 @@ config SAM34_EIC
 config SAM34_HSMCI
 	bool "High Speed Multimedia Card Interface (HSMCI)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S

 endmenu

@ -615,6 +660,21 @@ config GPIOC_IRQ
 	bool "GPIOC interrupts"
 	default n

+config GPIOD_IRQ
+	bool "GPIOD interrupts"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+
+config GPIOE_IRQ
+	bool "GPIOE interrupts"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+
+config GPIOF_IRQ
+	bool "GPIOF interrupts"
+	default n
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+
 endif

 if SAM34_WDT
--- a/arch/arm/src/sam34/Make.defs
+++ b/arch/arm/src/sam34/Make.defs
@ -104,6 +104,6 @@ ifeq ($(CONFIG_SAM34_HSMCI),y)
 CHIP_CSRCS += sam_hsmci.c
 endif

-ifeq ($(CONFIG_SAM34_SPI),y)
+ifeq ($(CONFIG_SAM34_SPI0),y)
 CHIP_CSRCS += sam_spi.c
 endif
--- a/arch/arm/src/sam34/chip/sam3u_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam3u_memorymap.h
@ -64,7 +64,7 @@
 #define SAM_PERIPHERALS_BASE   0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
 #  define SAM_MCI_BASE         0x40000000 /* 0x40000000-0x400003ff:   High Speed Multimedia Card Interface */
 #  define SAM_SSC_BASE         0x40004000 /* 0x40004000-0x40007fff:   Synchronous Serial Controller */
-#  define SAM_SPI_BASE         0x40008000 /* 0x40008000-0x4000bfff:   Serial Peripheral Interface */
+#  define SAM_SPI0_BASE        0x40008000 /* 0x40008000-0x4000bfff:   Serial Peripheral Interface */
                                          /* 0x4000c000-0x4007ffff:   Reserved */
 #  define SAM_TC_BASE          0x40080000 /* 0x40080000-0x40083fff:   Timer Counters */
 #    define SAM_TCN_BASE(n)    (0x40080000+((n)<<6))
--- a/arch/arm/src/sam34/chip/sam3u_pmc.h
+++ b/arch/arm/src/sam34/chip/sam3u_pmc.h
@ -169,6 +169,7 @@
 #  define SAM_PMC_PCER1                  (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET)
 #  define SAM_PMC_PCDR1                  (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET)
 #  define SAM_PMC_PCSR1                  (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET)
+#endif

 #if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
 #  define SAM_PMC_PCR                    (SAM_PMC_BASE+SAM_PMC_PCR_OFFSET)
--- a/arch/arm/src/sam34/chip/sam3u_vectors.h
+++ b/arch/arm/src/sam34/chip/sam3u_vectors.h
@ -74,7 +74,7 @@
  VECTOR(sam_hsmci, SAM_IRQ_HSMCI)    /* Vector 16+17: High Speed Multimedia Card Interface */
  VECTOR(sam_twi0, SAM_IRQ_TWI0)      /* Vector 16+18: Two-Wire Interface 0 */
  VECTOR(sam_twi1, SAM_IRQ_TWI1)      /* Vector 16+19: Two-Wire Interface 1 */
-  VECTOR(sam_spi, SAM_IRQ_SPI)        /* Vector 16+20: Serial Peripheral Interface */
+  VECTOR(sam_spi0, SAM_IRQ_SPI0)      /* Vector 16+20: Serial Peripheral Interface */
  VECTOR(sam_ssc, SAM_IRQ_SSC)        /* Vector 16+21: Synchronous Serial Controller */
  VECTOR(sam_tc0, SAM_IRQ_TC0)        /* Vector 16+22: Timer Counter 0 */
  VECTOR(sam_tc1, SAM_IRQ_TC1)        /* Vector 16+23: Timer Counter 1 */
--- a/arch/arm/src/sam34/chip/sam4l_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4l_memorymap.h
@ -78,7 +78,7 @@
 /* Peripheral Bridge A */
                                        /* 0x40000000-0x40003fff: Reserved */
 #define SAM_I2SC_BASE        0x40004000 /* 0x40004000-0x40007fff: I2S Controller */
-#define SAM_SPI_BASE         0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
+#define SAM_SPI0_BASE        0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
                                        /* 0x4000c000-0x4000ffff: Reserved */
 #define SAM_TC0_BASE         0x40100000 /* 0x40100000-0x4013ffff: Timer Counter 0 */
 #define SAM_TC1_BASE         0x40140000 /* 0x40180000-0x4017ffff: Timer Counter 1 */
--- a/arch/arm/src/sam34/chip/sam4l_vectors.h
+++ b/arch/arm/src/sam34/chip/sam4l_vectors.h
@ -108,7 +108,7 @@
  VECTOR(sam_eic7, SAM_IRQ_EIC7)                 /* Vector 16+51:  External Interrupt Controller 7 */
  VECTOR(sam_eic8, SAM_IRQ_EIC8)                 /* Vector 16+52:  External Interrupt Controller 8 */
  VECTOR(sam_iisc, SAM_IRQ_IISC)                 /* Vector 16+53:  Inter-IC Sound (I2S) Controller */
-  VECTOR(sam_spi, SAM_IRQ_SPI)                   /* Vector 16+54:  Serial Peripheral Interface */
+  VECTOR(sam_spi0, SAM_IRQ_SPI0)                 /* Vector 16+54:  Serial Peripheral Interface */
  VECTOR(sam_tc00, SAM_IRQ_TC00)                 /* Vector 16+55:  Timer/Counter 0 */
  VECTOR(sam_tc01, SAM_IRQ_TC01)                 /* Vector 16+56:  Timer/Counter 1 */
  VECTOR(sam_tc02, SAM_IRQ_TC02)                 /* Vector 16+57:  Timer/Counter 2 */
--- a/arch/arm/src/sam34/chip/sam4s_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4s_memorymap.h
@ -71,7 +71,7 @@

 #define SAM_HSMCI_BASE         0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
 #define SAM_SSC_BASE           0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */
-#define SAM_SPI_BASE           0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
+#define SAM_SPI0_BASE          0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
                                          /* 0x4000c000-0x4000ffff: Reserved */
 #define SAM_TC_BASE            0x40010000 /* 0x40010000-0x40017fff: Timer Counters */
 #  define SAM_TC0_BASE         0x40080000 /* 0x40010000-0x4001003f:   Timer Counter 0 */
--- a/arch/arm/src/sam34/chip/sam4s_vectors.h
+++ b/arch/arm/src/sam34/chip/sam4s_vectors.h
@ -75,7 +75,7 @@
  VECTOR(sam_hsmci, SAM_IRQ_HSMCI)    /* Vector 16+18: High Speed Multimedia Card Interface */
  VECTOR(sam_twi0, SAM_IRQ_TWI0)      /* Vector 16+19: Two-Wire Interface 0 */
  VECTOR(sam_twi1, SAM_IRQ_TWI1)      /* Vector 16+20: Two-Wire Interface 1 */
-  VECTOR(sam_spi, SAM_PID_SPI)        /* Vector 16+21: Serial Peripheral Interface */
+  VECTOR(sam_spi0, SAM_IRQ_SPI0)      /* Vector 16+21: Serial Peripheral Interface */
  VECTOR(sam_ssc, SAM_IRQ_SSC)        /* Vector 16+22: Synchronous Serial Controller */
  VECTOR(sam_tc0, SAM_IRQ_TC0)        /* Vector 16+23: Timer Counter 0 */
  VECTOR(sam_tc1, SAM_IRQ_TC1)        /* Vector 16+24: Timer Counter 1 */
--- a/arch/arm/src/sam34/chip/sam_spi.h
+++ b/arch/arm/src/sam34/chip/sam_spi.h
@ -80,24 +80,44 @@

 /* SPI register adresses ****************************************************************/

-#define SAM_SPI_CR                (SAM_SPI_BASE+SAM_SPI_CR_OFFSET)   /* Control Register */
-#define SAM_SPI_MR                (SAM_SPI_BASE+SAM_SPI_MR_OFFSET)   /* Mode Register */
-#define SAM_SPI_RDR               (SAM_SPI_BASE+SAM_SPI_RDR_OFFSET)  /* Receive Data Register */
-#define SAM_SPI_TDR               (SAM_SPI_BASE+SAM_SPI_TDR_OFFSET)  /* Transmit Data Register */
-#define SAM_SPI_SR                (SAM_SPI_BASE+SAM_SPI_SR_OFFSET)   /* Status Register */
-#define SAM_SPI_IER               (SAM_SPI_BASE+SAM_SPI_IER_OFFSET)  /* Interrupt Enable Register */
-#define SAM_SPI_IDR               (SAM_SPI_BASE+SAM_SPI_IDR_OFFSET)  /* Interrupt Disable Register */
-#define SAM_SPI_IMR               (SAM_SPI_BASE+SAM_SPI_IMR_OFFSET)  /* Interrupt Mask Register */
-#define SAM_SPI_CSR0              (SAM_SPI_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
-#define SAM_SPI_CSR1              (SAM_SPI_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
-#define SAM_SPI_CSR2              (SAM_SPI_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
-#define SAM_SPI_CSR3              (SAM_SPI_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
-#define SAM_SPI_WPCR              (SAM_SPI_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */
-#define SAM_SPI_WPSR              (SAM_SPI_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */
+#define SAM_SPI0_CR               (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET)   /* Control Register */
+#define SAM_SPI0_MR               (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET)   /* Mode Register */
+#define SAM_SPI0_RDR              (SAM_SPI0_BASE+SAM_SPI_RDR_OFFSET)  /* Receive Data Register */
+#define SAM_SPI0_TDR              (SAM_SPI0_BASE+SAM_SPI_TDR_OFFSET)  /* Transmit Data Register */
+#define SAM_SPI0_SR               (SAM_SPI0_BASE+SAM_SPI_SR_OFFSET)   /* Status Register */
+#define SAM_SPI0_IER              (SAM_SPI0_BASE+SAM_SPI_IER_OFFSET)  /* Interrupt Enable Register */
+#define SAM_SPI0_IDR              (SAM_SPI0_BASE+SAM_SPI_IDR_OFFSET)  /* Interrupt Disable Register */
+#define SAM_SPI0_IMR              (SAM_SPI0_BASE+SAM_SPI_IMR_OFFSET)  /* Interrupt Mask Register */
+#define SAM_SPI0_CSR0             (SAM_SPI0_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
+#define SAM_SPI0_CSR1             (SAM_SPI0_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
+#define SAM_SPI0_CSR2             (SAM_SPI0_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
+#define SAM_SPI0_CSR3             (SAM_SPI0_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
+#define SAM_SPI0_WPCR             (SAM_SPI0_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */
+#define SAM_SPI0_WPSR             (SAM_SPI0_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */

 #ifdef CONFIG_ARCH_CHIP_SAM4L
-#  define SAM_SPI_FEATURES        (SAM_SPI_BASE+SAM_SPI_FEATURES_OFFSET)
-#  define SAM_SPI_VERSION         (SAM_SPI_BASE+SAM_SPI_VERSION_OFFSET)
+#  define SAM_SPI0_FEATURES       (SAM_SPI0_BASE+SAM_SPI_FEATURES_OFFSET)
+#  define SAM_SPI0_VERSION        (SAM_SPI0_BASE+SAM_SPI_VERSION_OFFSET)
+#endif
+
+#define SAM_SPI1_CR               (SAM_SPI1_BASE+SAM_SPI_CR_OFFSET)   /* Control Register */
+#define SAM_SPI1_MR               (SAM_SPI1_BASE+SAM_SPI_MR_OFFSET)   /* Mode Register */
+#define SAM_SPI1_RDR              (SAM_SPI1_BASE+SAM_SPI_RDR_OFFSET)  /* Receive Data Register */
+#define SAM_SPI1_TDR              (SAM_SPI1_BASE+SAM_SPI_TDR_OFFSET)  /* Transmit Data Register */
+#define SAM_SPI1_SR               (SAM_SPI1_BASE+SAM_SPI_SR_OFFSET)   /* Status Register */
+#define SAM_SPI1_IER              (SAM_SPI1_BASE+SAM_SPI_IER_OFFSET)  /* Interrupt Enable Register */
+#define SAM_SPI1_IDR              (SAM_SPI1_BASE+SAM_SPI_IDR_OFFSET)  /* Interrupt Disable Register */
+#define SAM_SPI1_IMR              (SAM_SPI1_BASE+SAM_SPI_IMR_OFFSET)  /* Interrupt Mask Register */
+#define SAM_SPI1_CSR0             (SAM_SPI1_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
+#define SAM_SPI1_CSR1             (SAM_SPI1_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
+#define SAM_SPI1_CSR2             (SAM_SPI1_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
+#define SAM_SPI1_CSR3             (SAM_SPI1_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
+#define SAM_SPI1_WPCR             (SAM_SPI1_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */
+#define SAM_SPI1_WPSR             (SAM_SPI1_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */
+
+#ifdef CONFIG_ARCH_CHIP_SAM4L
+#  define SAM_SPI1_FEATURES       (SAM_SPI1_BASE+SAM_SPI_FEATURES_OFFSET)
+#  define SAM_SPI1_VERSION        (SAM_SPI1_BASE+SAM_SPI_VERSION_OFFSET)
 #endif

 /* SPI register bit definitions *********************************************************/
--- a/arch/arm/src/sam34/sam3u_periphclks.h
+++ b/arch/arm/src/sam34/sam3u_periphclks.h
@ -73,7 +73,7 @@
 #define sam_hsmci_enableclk()      sam_enableperipheral(SAM_PID_HSMCI)
 #define sam_twi0_enableclk()       sam_enableperipheral(SAM_PID_TWI0)
 #define sam_twi1_enableclk()       sam_enableperipheral(SAM_PID_TWI1)
-#define sam_spi_enableclk()        sam_enableperipheral(SAM_PID_SPI)
+#define sam_spi0_enableclk()       sam_enableperipheral(SAM_PID_SPI0)
 #define sam_ssc_enableclk()        sam_enableperipheral(SAM_PID_SSC)
 #define sam_tc0_enableclk()        sam_enableperipheral(SAM_PID_TC0)
 #define sam_tc1_enableclk()        sam_enableperipheral(SAM_PID_TC1)
@ -103,7 +103,7 @@
 #define sam_hsmci_disableclk()     sam_disableperipheral(SAM_PID_HSMCI)
 #define sam_twi0_disableclk()      sam_disableperipheral(SAM_PID_TWI0)
 #define sam_twi1_disableclk()      sam_disableperipheral(SAM_PID_TWI1)
-#define sam_spi_disableclk()       sam_disableperipheral(SAM_PID_SPI)
+#define sam_spi0_disableclk()      sam_disableperipheral(SAM_PID_SPI0)
 #define sam_ssc_disableclk()       sam_disableperipheral(SAM_PID_SSC)
 #define sam_tc0_disableclk()       sam_disableperipheral(SAM_PID_TC0)
 #define sam_tc1_disableclk()       sam_disableperipheral(SAM_PID_TC1)
--- a/arch/arm/src/sam34/sam4l_periphclks.c
+++ b/arch/arm/src/sam34/sam4l_periphclks.c
@ -186,7 +186,7 @@ static inline void sam_init_pbamask(void)
 #ifdef CONFIG_SAM34_IISC
  mask    |= PM_PBAMASK_IISC;         /* IISC */
 #endif
-#ifdef CONFIG_SAM34_SPI
+#ifdef CONFIG_SAM34_SPI0
  mask    |= PM_PBAMASK_SPI;          /* SPI */
 #endif
 #ifdef CONFIG_SAM34_TC0
--- a/arch/arm/src/sam34/sam4l_periphclks.h
+++ b/arch/arm/src/sam34/sam4l_periphclks.h
@ -72,7 +72,7 @@

 #define sam_aesa_enableclk()         sam_hsb_enableperipheral(PM_HSBMASK_AESA)
 #define sam_iisc_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_IISC)
-#define sam_spi_enableclk()          sam_pba_enableperipheral(PM_PBAMASK_SPI)
+#define sam_spi0_enableclk()         sam_pba_enableperipheral(PM_PBAMASK_SPI)

 #define sam_tc0_enableclk() \
  do { \
@ -170,7 +170,7 @@

 #define sam_aesa_disableclk()         sam_hsb_disableperipheral(PM_HSBMASK_AESA)
 #define sam_iisc_disableclk()         sam_pba_disableperipheral(PM_PBAMASK_IISC)
-#define sam_spi_disableclk()          sam_pba_disableperipheral(PM_PBAMASK_SPI)
+#define sam_spi0_disableclk()         sam_pba_disableperipheral(PM_PBAMASK_SPI)
 #define sam_tc0_disableclk()          sam_pba_disableperipheral(PM_PBAMASK_TC0)
 #define sam_tc1_disableclk()          sam_pba_disableperipheral(PM_PBAMASK_TC1)
 #define sam_twim0_disableclk()        sam_pba_disableperipheral(PM_PBAMASK_TWIM0)
--- a/arch/arm/src/sam34/sam_gpio.h
+++ b/arch/arm/src/sam34/sam_gpio.h
@ -49,7 +49,7 @@

 #if defined(CONFIG_ARCH_CHIP_SAM3U)
 #  include "sam3u_gpio.h"
-#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
+#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
 #  include "sam3x_gpio.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
 #  include "sam4l_gpio.h"
--- a/arch/arm/src/sam34/sam_spi.c
+++ b/arch/arm/src/sam34/sam_spi.c
@ -63,7 +63,7 @@
 #include "chip/sam_spi.h"
 #include "chip/sam_pinmap.h"

-#ifdef CONFIG_SAM34_SPI
+#ifdef CONFIG_SAM34_SPI0

 /****************************************************************************
 * Definitions
@ -203,7 +203,7 @@ static bool g_spinitialized = false;

 static const uint32_t g_csraddr[4] =
 {
-  SAM_SPI_CSR0, SAM_SPI_CSR1, SAM_SPI_CSR2, SAM_SPI_CSR3
+  SAM_SPI0_CSR0, SAM_SPI0_CSR1, SAM_SPI0_CSR2, SAM_SPI0_CSR3
 };

 /****************************************************************************
@ -233,13 +233,13 @@ static void spi_dumpregs(FAR const char *msg)
 {
  spivdbg("%s:\n", msg);
  spivdbg("    MR:%08x   SR:%08x  IMR:%08x\n",
-          getreg32(SAM_SPI_MR), getreg32(SAM_SPI_SR),
-          getreg32(SAM_SPI_IMR));
+          getreg32(SAM_SPI0_MR), getreg32(SAM_SPI0_SR),
+          getreg32(SAM_SPI0_IMR));
  spivdbg("  CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n",
-          getreg32(SAM_SPI_CSR0), getreg32(SAM_SPI_CSR1),
-          getreg32(SAM_SPI_CSR2), getreg32(SAM_SPI_CSR3));
+          getreg32(SAM_SPI0_CSR0), getreg32(SAM_SPI0_CSR1),
+          getreg32(SAM_SPI0_CSR2), getreg32(SAM_SPI0_CSR3));
  spivdbg("  WPCR:%08x WPSR:%08x\n",
-          getreg32(SAM_SPI_WPCR), getreg32(SAM_SPI_WPSR));
+          getreg32(SAM_SPI0_WPCR), getreg32(SAM_SPI0_WPSR));
 }
 #endif

@ -261,15 +261,15 @@ static inline void spi_flush(void)
 {
  /* Make sure the no TX activity is in progress... waiting if necessary */

-  while ((getreg32(SAM_SPI_SR) & SPI_INT_TXEMPTY) == 0);
+  while ((getreg32(SAM_SPI0_SR) & SPI_INT_TXEMPTY) == 0);

  /* Then make sure that there is no pending RX data .. reading as
   * discarding as necessary.
   */

-  while ((getreg32(SAM_SPI_SR) & SPI_INT_RDRF) != 0)
+  while ((getreg32(SAM_SPI0_SR) & SPI_INT_RDRF) != 0)
    {
-       (void)getreg32(SAM_SPI_RDR);
+       (void)getreg32(SAM_SPI0_RDR);
    }
 }

@ -385,10 +385,10 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
       * in order to select a slave.
       */

-      regval  = getreg32(SAM_SPI_MR);
+      regval  = getreg32(SAM_SPI0_MR);
      regval &= ~SPI_MR_PCS_MASK;
      regval |= (spi_cs2pcs(priv) << SPI_MR_PCS_SHIFT);
-      putreg32(regval, SAM_SPI_MR);
+      putreg32(regval, SAM_SPI0_MR);
    }

  /* Perform any board-specific chip select operations. PIO chip select
@ -784,24 +784,24 @@ static void  spi_exchange(FAR struct spi_dev_s *dev,
       * to the serializer.
       */

-      while ((getreg32(SAM_SPI_SR) & SPI_INT_TDRE) == 0);
+      while ((getreg32(SAM_SPI0_SR) & SPI_INT_TDRE) == 0);

      /* Write the data to transmitted to the Transmit Data Register (TDR) */

-      putreg32(data, SAM_SPI_TDR);
+      putreg32(data, SAM_SPI0_TDR);

      /* Wait for the read data to be available in the RDR.
       * TODO:  Data transfer rates would be improved using the RX FIFO
       *        (and also DMA)
       */

-      while ((getreg32(SAM_SPI_SR) & SPI_INT_RDRF) == 0);
+      while ((getreg32(SAM_SPI0_SR) & SPI_INT_RDRF) == 0);

      /* Read the received data from the SPI Data Register..
       * TODO: The following only works if nbits <= 8.
       */

-      data = getreg32(SAM_SPI_RDR);
+      data = getreg32(SAM_SPI0_RDR);
      if (rxptr)
        {
          *rxptr++ = (uint8_t)data;
@ -931,7 +931,7 @@ FAR struct spi_dev_s *up_spiinitialize(int cs)
      /* Enable clocking to the SPI block */

      flags = irqsave();
-      sam_spi_enableclk();
+      sam_spi0_enableclk();

      /* Configure multiplexed pins as connected on the board.  Chip select
       * pins must be configured by board-specific logic.
@ -943,27 +943,27 @@ FAR struct spi_dev_s *up_spiinitialize(int cs)

      /* Disable SPI clocking */

-      putreg32(SPI_CR_SPIDIS, SAM_SPI_CR);
+      putreg32(SPI_CR_SPIDIS, SAM_SPI0_CR);

      /* Execute a software reset of the SPI (twice) */

-      putreg32(SPI_CR_SWRST, SAM_SPI_CR);
-      putreg32(SPI_CR_SWRST, SAM_SPI_CR);
+      putreg32(SPI_CR_SWRST, SAM_SPI0_CR);
+      putreg32(SPI_CR_SWRST, SAM_SPI0_CR);
      irqrestore(flags);

      /* Configure the SPI mode register */

-      putreg32(SPI_MR_MSTR | SPI_MR_MODFDIS, SAM_SPI_MR);
+      putreg32(SPI_MR_MSTR | SPI_MR_MODFDIS, SAM_SPI0_MR);

      /* And enable the SPI */

-      putreg32(SPI_CR_SPIEN, SAM_SPI_CR);
+      putreg32(SPI_CR_SPIEN, SAM_SPI0_CR);
      up_mdelay(20);

      /* Flush any pending transfers */

-      (void)getreg32(SAM_SPI_SR);
-      (void)getreg32(SAM_SPI_RDR);
+      (void)getreg32(SAM_SPI0_SR);
+      (void)getreg32(SAM_SPI0_RDR);

 #ifndef CONFIG_SPI_OWNBUS
      /* Initialize the SPI semaphore that enforces mutually exclusive
@ -978,4 +978,4 @@ FAR struct spi_dev_s *up_spiinitialize(int cs)

  return &priv->spidev;
 }
-#endif /* CONFIG_SAM34_SPI */
+#endif /* CONFIG_SAM34_SPI0 */
--- a/arch/arm/src/sam34/sam_spi.h
+++ b/arch/arm/src/sam34/sam_spi.h
@ -111,7 +111,7 @@ extern "C"
 *
 ****************************************************************************/

-#ifdef CONFIG_SAM34_SPI
+#ifdef CONFIG_SAM34_SPI0
 struct spi_dev_s;
 enum spi_dev_e;

@ -187,7 +187,7 @@ uint8_t sam_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
 #ifdef CONFIG_SPI_CMDDATA
 int sam_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
 #endif
-#endif /* CONFIG_SAM34_SPI */
+#endif /* CONFIG_SAM34_SPI0 */

 #undef EXTERN
 #if defined(__cplusplus)
--- a/configs/arduino-due/README.txt
+++ b/configs/arduino-due/README.txt
@ -0,0 +1,535 @@
+README
+^^^^^^
+
+  This README discusses issues unique to NuttX configurations for the
+  Arduion DUE board featuring the Atmel ATSAM3X8E MSU.
+
+
+Contents
+^^^^^^^^
+
+  - PIO Pin Usage
+  - Development Environment
+  - GNU Toolchain Options
+  - IDEs
+  - NuttX EABI "buildroot" Toolchain
+  - NuttX OABI "buildroot" Toolchain
+  - NXFLAT Toolchain
+  - Buttons and LEDs
+  - Serial Consoles
+  - SAM4S Xplained-specific Configuration Options
+  - Configurations
+
+PIO Pin Usage
+^^^^^^^^^^^^^
+
+  To be provided
+
+Development Environment
+^^^^^^^^^^^^^^^^^^^^^^^
+
+  Either Linux or Cygwin on Windows can be used for the development environment.
+  The source has been built only using the GNU toolchain (see below).  Other
+  toolchains will likely cause problems. Testing was performed using the Cygwin
+  environment.
+
+GNU Toolchain Options
+^^^^^^^^^^^^^^^^^^^^^
+
+  The NuttX make system has been modified to support the following different
+  toolchain options.
+
+  1. The CodeSourcery GNU toolchain,
+  2. The devkitARM GNU toolchain, ok
+  4. The NuttX buildroot Toolchain (see below).
+
+  All testing has been conducted using the NuttX buildroot toolchain.  However,
+  the make system is setup to default to use the devkitARM toolchain.  To use
+  the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to
+  add one of the following configuration options to your .config (or defconfig)
+  file:
+
+    CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y  : CodeSourcery under Windows
+    CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y  : CodeSourcery under Linux
+    CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y        : Atollic toolchain for Windos
+    CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y      : devkitARM under Windows
+    CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y      : NuttX buildroot under Linux or Cygwin (default)
+    CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y      : Generic GCC ARM EABI toolchain for Linux
+    CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y      : Generic GCC ARM EABI toolchain for Windows
+
+  If you are not using CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT, then you may also
+  have to modify the PATH in the setenv.h file if your make cannot find the
+  tools.
+
+  NOTE about Windows native toolchains
+  ------------------------------------
+
+  The CodeSourcery (for Windows), Atollic, and devkitARM toolchains are
+  Windows native toolchains.  The CodeSourcery (for Linux), NuttX buildroot,
+  and, perhaps, the generic GCC toolchains are Cygwin and/or Linux native
+  toolchains. There are several limitations to using a Windows based
+  toolchain in a Cygwin environment.  The three biggest are:
+
+  1. The Windows toolchain cannot follow Cygwin paths.  Path conversions are
+     performed automatically in the Cygwin makefiles using the 'cygpath' utility
+     but you might easily find some new path problems.  If so, check out 'cygpath -w'
+
+  2. Windows toolchains cannot follow Cygwin symbolic links.  Many symbolic links
+     are used in Nuttx (e.g., include/arch).  The make system works around these
+     problems for the Windows tools by copying directories instead of linking them.
+     But this can also cause some confusion for you:  For example, you may edit
+     a file in a "linked" directory and find that your changes had no effect.
+     That is because you are building the copy of the file in the "fake" symbolic
+     directory.  If you use a Windows toolchain, you should get in the habit of
+     making like this:
+
+       make clean_context all
+
+     An alias in your .bashrc file might make that less painful.
+
+  3. Dependencies are not made when using Windows versions of the GCC.  This is
+     because the dependencies are generated using Windows pathes which do not
+     work with the Cygwin make.
+
+       MKDEP                = $(TOPDIR)/tools/mknulldeps.sh
+
+  NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
+  level of -Os (See Make.defs).  It will work with -O0, -O1, or -O2, but not with
+  -Os.
+
+  NOTE 2: The devkitARM toolchain includes a version of MSYS make.  Make sure that
+  the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
+  path or will get the wrong version of make.
+
+IDEs
+^^^^
+
+  NuttX is built using command-line make.  It can be used with an IDE, but some
+  effort will be required to create the project (There is a simple RIDE project
+  in the RIDE subdirectory).
+
+  Makefile Build
+  --------------
+  Under Eclipse, it is pretty easy to set up an "empty makefile project" and
+  simply use the NuttX makefile to build the system.  That is almost for free
+  under Linux.  Under Windows, you will need to set up the "Cygwin GCC" empty
+  makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
+  there is a lot of help on the internet).
+
+  Native Build
+  ------------
+  Here are a few tips before you start that effort:
+
+  1) Select the toolchain that you will be using in your .config file
+  2) Start the NuttX build at least one time from the Cygwin command line
+     before trying to create your project.  This is necessary to create
+     certain auto-generated files and directories that will be needed.
+  3) Set up include pathes:  You will need include/, arch/arm/src/sam34,
+     arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
+  4) All assembly files need to have the definition option -D __ASSEMBLY__
+     on the command line.
+
+  Startup files will probably cause you some headaches.  The NuttX startup file
+  is arch/arm/src/sam34/sam_vectors.S.  You may need to build NuttX
+  one time from the Cygwin command line in order to obtain the pre-built
+  startup object needed by RIDE.
+
+NuttX EABI "buildroot" Toolchain
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+  A GNU GCC-based toolchain is assumed.  The files */setenv.sh should
+  be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
+  different from the default in your PATH variable).
+
+  If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
+  SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/).
+  This GNU toolchain builds and executes in the Linux or Cygwin environment.
+
+  1. You must have already configured Nuttx in <some-dir>/nuttx.
+
+     cd tools
+     ./configure.shsam4s-xplained/<sub-dir>
+
+  2. Download the latest buildroot package into <some-dir>
+
+  3. unpack the buildroot tarball.  The resulting directory may
+     have versioning information on it like buildroot-x.y.z.  If so,
+     rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
+
+  4. cd <some-dir>/buildroot
+
+  5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config
+
+  6. make oldconfig
+
+  7. make
+
+  8. Edit setenv.h, if necessary, so that the PATH variable includes
+     the path to the newly built binaries.
+
+  See the file configs/README.txt in the buildroot source tree.  That has more
+  details PLUS some special instructions that you will need to follow if you are
+  building a Cortex-M3 toolchain for Cygwin under Windows.
+
+  NOTE:  Unfortunately, the 4.6.3 EABI toolchain is not compatible with the
+  the NXFLAT tools.  See the top-level TODO file (under "Binary loaders") for
+  more information about this problem. If you plan to use NXFLAT, please do not
+  use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain.
+  See instructions below.
+
+NuttX OABI "buildroot" Toolchain
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+  The older, OABI buildroot toolchain is also available.  To use the OABI
+  toolchain:
+
+  1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3
+     configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI
+     configuration such as cortexm3-defconfig-4.3.3
+
+  2. Modify the Make.defs file to use the OABI conventions:
+
+    +CROSSDEV = arm-nuttx-elf-
+    +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+    +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections
+    -CROSSDEV = arm-nuttx-eabi-
+    -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+    -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+
+NXFLAT Toolchain
+^^^^^^^^^^^^^^^^
+
+  If you are *not* using the NuttX buildroot toolchain and you want to use
+  the NXFLAT tools, then you will still have to build a portion of the buildroot
+  tools -- just the NXFLAT tools.  The buildroot with the NXFLAT tools can
+  be downloaded from the NuttX SourceForge download site
+  (https://sourceforge.net/projects/nuttx/files/).
+
+  This GNU toolchain builds and executes in the Linux or Cygwin environment.
+
+  1. You must have already configured Nuttx in <some-dir>/nuttx.
+
+     cd tools
+     ./configure.sh lpcxpresso-lpc1768/<sub-dir>
+
+  2. Download the latest buildroot package into <some-dir>
+
+  3. unpack the buildroot tarball.  The resulting directory may
+     have versioning information on it like buildroot-x.y.z.  If so,
+     rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
+
+  4. cd <some-dir>/buildroot
+
+  5. cp configs/cortexm3-defconfig-nxflat .config
+
+  6. make oldconfig
+
+  7. make
+
+  8. Edit setenv.h, if necessary, so that the PATH variable includes
+     the path to the newly builtNXFLAT binaries.
+
+Buttons and LEDs
+^^^^^^^^^^^^^^^^
+
+  To be provided
+
+Serial Consoles
+^^^^^^^^^^^^^^^
+
+  To be provided
+
+Arduino DUE-specific Configuration Options
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+  CONFIG_ARCH - Identifies the arch/ subdirectory.  This should
+  be set to:
+
+    CONFIG_ARCH=arm
+
+  CONFIG_ARCH_family - For use in C code:
+
+    CONFIG_ARCH_ARM=y
+
+  CONFIG_ARCH_architecture - For use in C code:
+
+    CONFIG_ARCH_CORTEXM3=y
+
+  CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+    CONFIG_ARCH_CHIP="sam34"
+
+  CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+  chip:
+
+    CONFIG_ARCH_CHIP_SAM34
+    CONFIG_ARCH_CHIP_SAM3X
+    CONFIG_ARCH_CHIP_ATSAM3X8E
+
+  CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
+  hence, the board that supports the particular chip or SoC.
+
+    CONFIG_ARCH_BOARD=arduino-due (for the Arduino Due development board)
+
+  CONFIG_ARCH_BOARD_name - For use in C code
+
+    CONFIG_ARCH_BOARD_ARDUINO_DUE=y
+
+  CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+  of delay loops
+
+  CONFIG_ENDIAN_BIG - define if big endian (default is little
+  endian)
+
+  CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+    CONFIG_DRAM_SIZE=0x00008000 (32Kb)
+
+  CONFIG_DRAM_START - The start address of installed DRAM
+
+    CONFIG_DRAM_START=0x20000000
+
+  CONFIG_ARCH_IRQPRIO - The SAM3UF103Z supports interrupt prioritization
+
+    CONFIG_ARCH_IRQPRIO=y
+
+  CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+  have LEDs
+
+  CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+  stack. If defined, this symbol is the size of the interrupt
+  stack in bytes.  If not defined, the user task stacks will be
+  used during interrupt handling.
+
+  CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+  CONFIG_ARCH_LEDS -  Use LEDs to show state. Unique to board architecture.
+
+  CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+  cause a 100 second delay during boot-up.  This 100 second delay
+  serves no purpose other than it allows you to calibratre
+  CONFIG_ARCH_LOOPSPERMSEC.  You simply use a stop watch to measure
+  the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
+  the delay actually is 100 seconds.
+
+  Individual subsystems can be enabled:
+
+    CONFIG_SAM34_RTC         - Real Time Clock
+    CONFIG_SAM34_RTT         - Real Time Timer
+    CONFIG_SAM34_WDT         - Watchdog Timer
+    CONFIG_SAM34_UART0       - UART 0
+    CONFIG_SAM34_SMC         - Static Memory Controller
+    CONFIG_SAM34_SDRAMC      - SDRAM Controller
+    CONFIG_SAM34_USART0      - USART 0
+    CONFIG_SAM34_USART1      - USART 1
+    CONFIG_SAM34_USART2      - USART 2
+    CONFIG_SAM34_USART3      - USART 3
+    CONFIG_SAM34_HSMCI       - High Speed Multimedia Card Interface
+    CONFIG_SAM34_TWI0        - Two-Wire Interface 0 (master/slave)
+    CONFIG_SAM34_TWI1        - Two-Wire Interface 1 (master/slave)
+    CONFIG_SAM34_SPI0        - Serial Peripheral Interface 0
+    CONFIG_SAM34_SPI1        - Serial Peripheral Interface 1
+    CONFIG_SAM34_SSC         - Synchronous Serial Controller
+    CONFIG_SAM34_TC0         - Timer Counter 0
+    CONFIG_SAM34_TC1         - Timer Counter 1
+    CONFIG_SAM34_TC2         - Timer Counter 2
+    CONFIG_SAM34_TC3         - Timer Counter 3
+    CONFIG_SAM34_TC4         - Timer Counter 4
+    CONFIG_SAM34_TC5         - Timer Counter 5
+    CONFIG_SAM34_TC6         - Timer Counter 6
+    CONFIG_SAM34_TC7         - Timer Counter 7
+    CONFIG_SAM34_TC8         - Timer Counter 8
+    CONFIG_SAM34_PWM         - Pulse Width Modulation
+    CONFIG_SAM34_ADC12B      - 12-bit Analog To Digital Converter
+    CONFIG_SAM34_DACC        - Digital To Analog Converter
+    CONFIG_SAM34_DMA         - DMA Controller
+    CONFIG_SAM34_UOTGHS      - USB OTG High Speed
+    CONFIG_SAM34_TRNG        - True Random Number Generator
+    CONFIG_SAM34_EMAC        - Ethernet MAC
+    CONFIG_SAM34_CAN0        - CAN Controller 0
+    CONFIG_SAM34_CAN1        - CAN Controller 1
+
+  Some subsystems can be configured to operate in different ways. The drivers
+  need to know how to configure the subsystem.
+
+    CONFIG_GPIOA_IRQ
+    CONFIG_GPIOB_IRQ
+    CONFIG_GPIOC_IRQ
+    CONFIG_GPIOD_IRQ
+    CONFIG_GPIOE_IRQ
+    CONFIG_GPIOF_IRQ
+    CONFIG_USART0_ISUART
+    CONFIG_USART1_ISUART
+    CONFIG_USART2_ISUART
+    CONFIG_USART3_ISUART
+
+  ST91SAM4S specific device driver settings
+
+    CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=0,1,2,3) or UART
+           m (m=4,5) for the console and ttys0 (default is the USART1).
+    CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+       This specific the size of the receive buffer
+    CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+       being sent.  This specific the size of the transmit buffer
+    CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART.  Must be
+    CONFIG_U[S]ARTn_BITS - The number of bits.  Must be either 7 or 8.
+    CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+    CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+Configurations
+^^^^^^^^^^^^^^
+
+  Each SAM4S Xplained configuration is maintained in a sub-directory and
+  can be selected as follow:
+
+    cd tools
+    ./configure.shsam4s-xplained/<subdir>
+    cd -
+    . ./setenv.sh
+
+  Before sourcing the setenv.sh file above, you should examine it and perform
+  edits as necessary so that BUILDROOT_BIN is the correct path to the directory
+  than holds your toolchain binaries.
+
+  And then build NuttX by simply typing the following.  At the conclusion of
+  the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
+
+    make
+
+  The <subdir> that is provided above as an argument to the tools/configure.sh
+  must be is one of the following.
+
+  NOTES:
+
+  1. These configurations use the mconf-based configuration tool.  To
+    change any of these configurations using that tool, you should:
+
+    a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+       and misc/tools/
+
+    b. Execute 'make menuconfig' in nuttx/ in order to start the
+       reconfiguration process.
+
+  2. Unless stated otherwise, all configurations generate console
+     output on UART1 which is available on J1 or J4 (see the
+     section "Serial Consoles" above).  USART1 or the virtual COM
+     port on UART0 are options. The virtual COM port could
+     be used, for example, by reconfiguring to use UART0 like:
+
+       System Type -> AT91SAM3/4 Peripheral Support
+         CONFIG_SAM_UART0=y
+         CONFIG_SAM_UART1=n
+
+       Device Drivers -> Serial Driver Support -> Serial Console
+         CONFIG_UART0_SERIAL_CONSOLE=y
+
+       Device Drivers -> Serial Driver Support -> UART0 Configuration
+         CONFIG_UART0_2STOP=0
+         CONFIG_UART0_BAUD=115200
+         CONFIG_UART0_BITS=8
+         CONFIG_UART0_PARITY=0
+         CONFIG_UART0_RXBUFSIZE=256
+         CONFIG_UART0_TXBUFSIZE=256
+
+  3. Unless otherwise stated, the configurations are setup for
+     Linux (or any other POSIX environment like Cygwin under Windows):
+
+     Build Setup:
+       CONFIG_HOST_LINUX=y   : Linux or other POSIX environment
+
+  4. These configurations use the older, OABI, buildroot toolchain.  But
+     that is easily reconfigured:
+
+     System Type -> Toolchain:
+       CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain
+       CONFIG_ARMV7M_OABI_TOOLCHAIN=y      : Older, OABI toolchain
+
+     If you want to use the Atmel GCC toolchain, here are the steps to
+     do so:
+
+     Build Setup:
+       CONFIG_HOST_WINDOWS=y   : Windows
+       CONFIG_HOST_CYGWIN=y    : Using Cygwin or other POSIX environment
+
+     System Type -> Toolchain:
+       CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : General GCC EABI toolchain under windows
+
+     This re-configuration should be done before making NuttX or else the
+     subsequent 'make' will fail.  If you have already attempted building
+     NuttX then you will have to 1) 'make distclean' to remove the old
+     configuration, 2) 'cd tools; ./configure.sh sam3u-ek/ksnh' to start
+     with a fresh configuration, and 3) perform the configuration changes
+     above.
+
+     Also, make sure that your PATH variable has the new path to your
+     Atmel tools.  Try 'which arm-none-eabi-gcc' to make sure that you
+     are selecting the right tool.  setenv.sh is available for you to
+     use to set or PATH variable.  The path in the that file may not,
+     however, be correct for your installation.
+
+     See also the "NOTE about Windows native toolchains" in the section call
+     "GNU Toolchain Options" above.
+
+Configuration sub-directories
+-----------------------------
+
+  ostest:
+    This configuration directory performs a simple OS test using
+    examples/ostest.  See NOTES above.
+
+  nsh:
+    This configuration directory will built the NuttShell.  See NOTES above.
+
+    NOTES:
+    1. The configuration configuration can be modified to include support
+       for the on-board SRAM (1MB).
+
+       System Type -> External Memory Configuration       
+         CONFIG_ARCH_EXTSRAM0=y              : Select SRAM on CS0
+         CONFIG_ARCH_EXTSRAM0SIZE=1048576    : Size=1MB
+
+       Now what are you going to do with the SRAM.  There are two choices:
+
+       a)  To enable the NuttX RAM test that may be used to verify the
+           external SRAM:
+
+           System Type -> External Memory Configuration       
+             CONFIG_ARCH_EXTSRAM0HEAP=n      : Don't add to heap
+
+           Application Configuration -> System NSH Add-Ons
+             CONFIG_SYSTEM_RAMTEST=y         : Enable the RAM test built-in
+
+         In this configuration, the SDRAM is not added to heap and so is
+         not excessible to the applications.  So the RAM test can be
+         freely executed against the SRAM memory beginning at address
+         0x6000:0000 (CS0).
+
+         nsh> ramtest -h
+         Usage: <noname> [-w|h|b] <hex-address> <decimal-size>
+
+         Where:
+           <hex-address> starting address of the test.
+           <decimal-size> number of memory locations (in bytes).
+           -w Sets the width of a memory location to 32-bits.
+           -h Sets the width of a memory location to 16-bits (default).
+           -b Sets the width of a memory location to 8-bits.
+
+         To test the entire external SRAM:
+
+         nsh> ramtest 60000000 1048576
+         RAMTest: Marching ones: 60000000 1048576
+         RAMTest: Marching zeroes: 60000000 1048576
+         RAMTest: Pattern test: 60000000 1048576 55555555 aaaaaaaa
+         RAMTest: Pattern test: 60000000 1048576 66666666 99999999
+         RAMTest: Pattern test: 60000000 1048576 33333333 cccccccc
+         RAMTest: Address-in-address test: 60000000 1048576
+
+        b) To add this RAM to the NuttX heap, you would need to change the
+           configuration as follows:
+
+           System Type -> External Memory Configuration       
+             CONFIG_ARCH_EXTSRAM0HEAP=y     : Add external RAM to heap
+
+           Memory Management
+             -CONFIG_MM_REGIONS=1           : Only the internal SRAM
+             +CONFIG_MM_REGIONS=2           : Also include external SRAM
--- a/configs/sam3u-ek/README.txt
+++ b/configs/sam3u-ek/README.txt
@ -354,7 +354,7 @@ SAM3U-EK-specific Configuration Options
    CONFIG_SAM34_HSMCI         - High Speed Multimedia Card Interface
    CONFIG_SAM34_TWI0          - Two-Wire Interface 0
    CONFIG_SAM34_TWI1          - Two-Wire Interface 1
-    CONFIG_SAM34_SPI           - Serial Peripheral Interface
+    CONFIG_SAM34_SPI0           - Serial Peripheral Interface
    CONFIG_SAM34_SSC           - Synchronous Serial Controller
    CONFIG_SAM34_TC0           - Timer Counter 0
    CONFIG_SAM34_TC1           - Timer Counter 1
@ -587,7 +587,7 @@ Configuration sub-directories
            CONFIG_ADS7843E_THRESHY=39

          System Type -> Peripherals:
-            CONFIG_SAM34_SPI=y                : Enable support for SPI
+            CONFIG_SAM34_SPI0=y                : Enable support for SPI

          System Type:
            CONFIG_GPIO_IRQ=y                 : GPIO interrupt support
--- a/configs/sam3u-ek/knsh/defconfig
+++ b/configs/sam3u-ek/knsh/defconfig
@ -135,7 +135,7 @@ CONFIG_ARCH_CHIP_SAM3U=y
 #
 # AT91SAM3/4 Peripheral Support
 #
-# CONFIG_SAM34_SPI is not set
+# CONFIG_SAM34_SPI0 is not set
 # CONFIG_SAM34_SSC is not set
 # CONFIG_SAM34_TC0 is not set
 # CONFIG_SAM34_TC1 is not set
--- a/configs/sam3u-ek/nsh/defconfig
+++ b/configs/sam3u-ek/nsh/defconfig
@ -98,7 +98,13 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 # AT91SAM3/4 Configuration Options
 #
 CONFIG_ARCH_CHIP_AT91SAM3U4E=y
-# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X8E is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X8C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X4E is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X4C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3A8C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3A4C is not set
+# CONFIG_ARCH_CHIP_ATSAM4LC2C is not set
 # CONFIG_ARCH_CHIP_ATSAM4LC2B is not set
 # CONFIG_ARCH_CHIP_ATSAM4LC2A is not set
 # CONFIG_ARCH_CHIP_ATSAM4LC4C is not set
@ -121,13 +127,15 @@ CONFIG_ARCH_CHIP_AT91SAM3U4E=y
 # CONFIG_ARCH_CHIP_ATSAM4S8C is not set
 # CONFIG_ARCH_CHIP_ATSAM4S8B is not set
 CONFIG_ARCH_CHIP_SAM3U=y
+# CONFIG_ARCH_CHIP_SAM3X is not set
+# CONFIG_ARCH_CHIP_SAM3A is not set
 # CONFIG_ARCH_CHIP_SAM4L is not set
 # CONFIG_ARCH_CHIP_SAM4S is not set

 #
 # AT91SAM3/4 Peripheral Support
 #
-# CONFIG_SAM34_SPI is not set
+# CONFIG_SAM34_SPI0 is not set
 # CONFIG_SAM34_SSC is not set
 # CONFIG_SAM34_TC0 is not set
 # CONFIG_SAM34_TC1 is not set
@ -148,6 +156,7 @@ CONFIG_SAM34_UART0=y
 # CONFIG_SAM34_NAND is not set
 # CONFIG_SAM34_DMA is not set
 # CONFIG_SAM34_UDPHS is not set
+# CONFIG_SAM34_UOTGHS is not set
 # CONFIG_SAM34_RTC is not set
 # CONFIG_SAM34_RTT is not set
 # CONFIG_SAM34_WDT is not set
@ -164,6 +173,14 @@ CONFIG_SAM34_UART0=y
 #
 # External Memory Configuration
 #
+CONFIG_ARCH_HAVE_EXTNAND=y
+CONFIG_ARCH_HAVE_EXTNOR=y
+CONFIG_ARCH_HAVE_EXTSRAM0=y
+CONFIG_ARCH_HAVE_EXTSRAM1=y
+# CONFIG_ARCH_EXTNAND is not set
+# CONFIG_ARCH_EXTNOR is not set
+# CONFIG_ARCH_EXTSRAM0 is not set
+# CONFIG_ARCH_EXTSRAM1 is not set

 #
 # Architecture Options
@ -242,7 +259,7 @@ CONFIG_DEV_CONSOLE=y
 # CONFIG_FDCLONE_DISABLE is not set
 # CONFIG_FDCLONE_STDIO is not set
 CONFIG_SDCLONE_DISABLE=y
-# CONFIG_SCHED_WAITPID is not set
+CONFIG_SCHED_WAITPID=y
 # CONFIG_SCHED_STARTHOOK is not set
 # CONFIG_SCHED_ATEXIT is not set
 # CONFIG_SCHED_ONEXIT is not set
@ -642,6 +659,11 @@ CONFIG_NSH_ARCHINIT=y
 # FLASH Erase-all Command
 #

+#
+# RAM test
+#
+# CONFIG_SYSTEM_RAMTEST is not set
+
 #
 # readline()
 #
--- a/configs/sam3u-ek/nx/defconfig
+++ b/configs/sam3u-ek/nx/defconfig
@ -127,7 +127,7 @@ CONFIG_ARCH_CHIP_SAM3U=y
 #
 # AT91SAM3/4 Peripheral Support
 #
-# CONFIG_SAM34_SPI is not set
+# CONFIG_SAM34_SPI0 is not set
 # CONFIG_SAM34_SSC is not set
 # CONFIG_SAM34_TC0 is not set
 # CONFIG_SAM34_TC1 is not set
--- a/configs/sam3u-ek/ostest/defconfig
+++ b/configs/sam3u-ek/ostest/defconfig
@ -127,7 +127,7 @@ CONFIG_ARCH_CHIP_SAM3U=y
 #
 # AT91SAM3/4 Peripheral Support
 #
-# CONFIG_SAM34_SPI is not set
+# CONFIG_SAM34_SPI0 is not set
 # CONFIG_SAM34_SSC is not set
 # CONFIG_SAM34_TC0 is not set
 # CONFIG_SAM34_TC1 is not set
--- a/configs/sam3u-ek/src/up_boot.c
+++ b/configs/sam3u-ek/src/up_boot.c
@ -74,7 +74,7 @@ void sam_boardinitialize(void)
   * sam_spiinitialize() has been brought into the link.
   */

-#ifdef CONFIG_SAM34_SPI
+#ifdef CONFIG_SAM34_SPI0
  if (sam_spiinitialize)
    {
      sam_spiinitialize();
--- a/configs/sam3u-ek/src/up_spi.c
+++ b/configs/sam3u-ek/src/up_spi.c
@ -53,7 +53,7 @@
 #include "sam_spi.h"
 #include "sam3u-ek.h"

-#ifdef CONFIG_SAM34_SPI
+#ifdef CONFIG_SAM34_SPI0

 /************************************************************************************
 * Definitions
@ -201,4 +201,4 @@ uint8_t sam_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
  return 0;
 }

-#endif /* CONFIG_SAM34_SPI */
+#endif /* CONFIG_SAM34_SPI0 */
--- a/configs/sam3u-ek/src/up_touchscreen.c
+++ b/configs/sam3u-ek/src/up_touchscreen.c
@ -62,8 +62,8 @@
 #  error "Touchscreen support requires CONFIG_INPUT"
 #endif

-#ifndef CONFIG_SAM34_SPI
-#  error "Touchscreen support requires CONFIG_SAM34_SPI"
+#ifndef CONFIG_SAM34_SPI0
+#  error "Touchscreen support requires CONFIG_SAM34_SPI0"
 #endif

 #ifndef CONFIG_GPIOA_IRQ
--- a/configs/sam4l-xplained/README.txt
+++ b/configs/sam4l-xplained/README.txt
@ -528,7 +528,7 @@ SAM4L Xplained Pro-specific Configuration Options
    PBA
    ---
    CONFIG_SAM34_IISC
-    CONFIG_SAM34_SPI
+    CONFIG_SAM34_SPI0
    CONFIG_SAM34_TC0
    CONFIG_SAM34_TC1
    CONFIG_SAM34_TWIM0
@ -739,7 +739,7 @@ Configuration sub-directories
         details.

       System Type -> Peripherals:
-         CONFIG_SAM34_SPI=y                : Enable the SAM4L SPI peripheral
+         CONFIG_SAM34_SPI0=y                : Enable the SAM4L SPI peripheral

       Device Drivers
         CONFIG_SPI=y                      : Enable SPI support
@ -793,7 +793,7 @@ Configuration sub-directories
       changes to the configuration:

       System Type -> Peripherals:
-         CONFIG_SAM34_SPI=y                 : Enable the SAM4L SPI peripheral
+         CONFIG_SAM34_SPI0=y                 : Enable the SAM4L SPI peripheral

       Device Drivers -> SPI
         CONFIG_SPI=y                       : Enable SPI support
--- a/configs/sam4l-xplained/nsh/defconfig
+++ b/configs/sam4l-xplained/nsh/defconfig
@ -92,12 +92,19 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
 CONFIG_ARMV7M_OABI_TOOLCHAIN=y
+# CONFIG_GPIO_IRQ is not set

 #
 # AT91SAM3/4 Configuration Options
 #
 # CONFIG_ARCH_CHIP_AT91SAM3U4E is not set
-# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X8E is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X8C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X4E is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X4C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3A8C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3A4C is not set
+# CONFIG_ARCH_CHIP_ATSAM4LC2C is not set
 # CONFIG_ARCH_CHIP_ATSAM4LC2B is not set
 # CONFIG_ARCH_CHIP_ATSAM4LC2A is not set
 CONFIG_ARCH_CHIP_ATSAM4LC4C=y
@ -109,17 +116,19 @@ CONFIG_ARCH_CHIP_ATSAM4LC4C=y
 # CONFIG_ARCH_CHIP_ATSAM4LS4C is not set
 # CONFIG_ARCH_CHIP_ATSAM4LS4B is not set
 # CONFIG_ARCH_CHIP_ATSAM4LS4A is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD32C is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD32B is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD16C is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SD16B is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SA16C is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4SA16B is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S16C is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S16B is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S8C is not set
-# CONFIG_CONFIG_ARCH_CHIP_ATSAM4S8B is not set
+# CONFIG_ARCH_CHIP_ATSAM4SD32C is not set
+# CONFIG_ARCH_CHIP_ATSAM4SD32B is not set
+# CONFIG_ARCH_CHIP_ATSAM4SD16C is not set
+# CONFIG_ARCH_CHIP_ATSAM4SD16B is not set
+# CONFIG_ARCH_CHIP_ATSAM4SA16C is not set
+# CONFIG_ARCH_CHIP_ATSAM4SA16B is not set
+# CONFIG_ARCH_CHIP_ATSAM4S16C is not set
+# CONFIG_ARCH_CHIP_ATSAM4S16B is not set
+# CONFIG_ARCH_CHIP_ATSAM4S8C is not set
+# CONFIG_ARCH_CHIP_ATSAM4S8B is not set
 # CONFIG_ARCH_CHIP_SAM3U is not set
+# CONFIG_ARCH_CHIP_SAM3X is not set
+# CONFIG_ARCH_CHIP_SAM3A is not set
 CONFIG_ARCH_CHIP_SAM4L=y
 # CONFIG_ARCH_CHIP_SAM4S is not set

@ -131,7 +140,7 @@ CONFIG_SAM_PICOCACHE=y
 # CONFIG_SAM34_APBA is not set
 # CONFIG_SAM34_AESA is not set
 # CONFIG_SAM34_IISC is not set
-# CONFIG_SAM34_SPI is not set
+# CONFIG_SAM34_SPI0 is not set
 # CONFIG_SAM34_TC0 is not set
 # CONFIG_SAM34_TC1 is not set
 # CONFIG_SAM34_TWIM0 is not set
@ -145,9 +154,9 @@ CONFIG_SAM34_USART0=y
 # CONFIG_SAM34_USART1 is not set
 # CONFIG_SAM34_USART2 is not set
 # CONFIG_SAM34_USART3 is not set
-# CONFIG_SAM34_ADCIFE is not set
+# CONFIG_SAM34_ADC12B is not set
 # CONFIG_SAM34_DACC is not set
-# CONFIG_SAM34_ACIFC is not set
+# CONFIG_SAM34_ACC is not set
 # CONFIG_SAM34_GLOC is not set
 # CONFIG_SAM34_ABDACB is not set
 # CONFIG_SAM34_TRNG is not set
@ -165,7 +174,17 @@ CONFIG_SAM34_USART0=y
 # CONFIG_SAM34_AST is not set
 # CONFIG_SAM34_WDT is not set
 # CONFIG_SAM34_EIC is not set
+
+#
+# AT91SAM3/4 Clock Configuration
+#
 # CONFIG_SAM32_RESET_PERIPHCLKS is not set
+# CONFIG_SAM34_OSC0 is not set
+# CONFIG_SAM34_OSC32K is not set
+# CONFIG_SAM34_RC80M is not set
+# CONFIG_SAM34_RCFAST is not set
+# CONFIG_SAM34_RC1M is not set
+# CONFIG_SAM34_RC32K is not set

 #
 # AT91SAM3/4 USART Configuration
@ -175,9 +194,6 @@ CONFIG_USART0_ISUART=y
 #
 # AT91SAM3/4 GPIO Interrupt Configuration
 #
-# CONFIG_GPIOA_IRQ is not set
-# CONFIG_GPIOB_IRQ is not set
-# CONFIG_GPIOC_IRQ is not set

 #
 # External Memory Configuration
@ -241,6 +257,13 @@ CONFIG_NSH_MMCSDMINOR=0
 # Board-Specific Options
 #

+#
+# SAM4L Xplained Pro Modules
+#
+# CONFIG_SAM4L_XPLAINED_SLCD1MODULE is not set
+# CONFIG_SAM4L_XPLAINED_IOMODULE is not set
+# CONFIG_SAM4L_XPLAINED_OLED1MODULE is not set
+
 #
 # RTOS Features
 #
@ -260,7 +283,7 @@ CONFIG_DEV_CONSOLE=y
 # CONFIG_FDCLONE_DISABLE is not set
 # CONFIG_FDCLONE_STDIO is not set
 CONFIG_SDCLONE_DISABLE=y
-# CONFIG_SCHED_WAITPID is not set
+CONFIG_SCHED_WAITPID=y
 # CONFIG_SCHED_STARTHOOK is not set
 # CONFIG_SCHED_ATEXIT is not set
 # CONFIG_SCHED_ONEXIT is not set
@ -663,6 +686,11 @@ CONFIG_NSH_CONSOLE=y
 # FLASH Erase-all Command
 #

+#
+# RAM test
+#
+# CONFIG_SYSTEM_RAMTEST is not set
+
 #
 # readline()
 #
--- a/configs/sam4l-xplained/ostest/defconfig
+++ b/configs/sam4l-xplained/ostest/defconfig
@ -131,7 +131,7 @@ CONFIG_SAM_PICOCACHE=y
 # CONFIG_SAM34_APBA is not set
 # CONFIG_SAM34_AESA is not set
 # CONFIG_SAM34_IISC is not set
-# CONFIG_SAM34_SPI is not set
+# CONFIG_SAM34_SPI0 is not set
 # CONFIG_SAM34_TC0 is not set
 # CONFIG_SAM34_TC1 is not set
 # CONFIG_SAM34_TWIM0 is not set
--- a/configs/sam4l-xplained/src/Makefile
+++ b/configs/sam4l-xplained/src/Makefile
@ -46,7 +46,7 @@ ifeq ($(CONFIG_HAVE_CXX),y)
 CSRCS += sam_cxxinitialize.c
 endif

-ifeq ($(CONFIG_SAM34_SPI),y)
+ifeq ($(CONFIG_SAM34_SPI0),y)
 CSRCS += sam_spi.c
 endif

@ -70,13 +70,13 @@ CSRCS += sam_slcd.c
 endif
 endif

-ifeq ($(CONFIG_SAM34_SPI),y)
+ifeq ($(CONFIG_SAM34_SPI0),y)
 ifeq ($(CONFIG_SAM4L_XPLAINED_IOMODULE),y)
 CSRCS += sam_mmcsd.c
 endif
 endif

-ifeq ($(CONFIG_SAM34_SPI),y)
+ifeq ($(CONFIG_SAM34_SPI0),y)
 ifeq ($(CONFIG_SAM4L_XPLAINED_OLED1MODULE),y)
 ifeq ($(CONFIG_LCD_UG2832HSWEG04),y)
 CSRCS += sam_ug2832hsweg04.c
--- a/configs/sam4l-xplained/src/sam4l-xplained.h
+++ b/configs/sam4l-xplained/src/sam4l-xplained.h
@ -189,8 +189,8 @@

 #ifdef CONFIG_SAM4L_XPLAINED_IOMODULE

-#  ifndef CONFIG_SAM34_SPI
-#    error CONFIG_SAM34_SPI is required to use the I/O1 module
+#  ifndef CONFIG_SAM34_SPI0
+#    error CONFIG_SAM34_SPI0 is required to use the I/O1 module
 #  endif

 #  if defined(CONFIG_SAM4L_XPLAINED_IOMODULE_EXT1)
@ -248,8 +248,8 @@

 #ifdef CONFIG_SAM4L_XPLAINED_OLED1MODULE

-#  ifndef CONFIG_SAM34_SPI
-#    error CONFIG_SAM34_SPI is required to use the OLED1 module
+#  ifndef CONFIG_SAM34_SPI0
+#    error CONFIG_SAM34_SPI0 is required to use the OLED1 module
 #  endif

 #  ifndef CONFIG_SPI_CMDDATA
@ -337,11 +337,11 @@ void weak_function sam_spiinitialize(void);
 *
 * Description:
 *   Initialize the SPI-based SD card.  Requires CONFIG_SAM4L_XPLAINED_IOMODULE=y,
- *   CONFIG_DISABLE_MOUNTPOINT=n, CONFIG_MMCSD=y, and CONFIG_SAM34_SPI=y
+ *   CONFIG_DISABLE_MOUNTPOINT=n, CONFIG_MMCSD=y, and CONFIG_SAM34_SPI0=y
 *
 ************************************************************************************/

-#if defined(CONFIG_SAM34_SPI) && defined(CONFIG_SAM4L_XPLAINED_IOMODULE)
+#if defined(CONFIG_SAM34_SPI0) && defined(CONFIG_SAM4L_XPLAINED_IOMODULE)
 int sam_sdinitialize(int minor);
 #endif

--- a/configs/sam4l-xplained/src/sam_boot.c
+++ b/configs/sam4l-xplained/src/sam_boot.c
@ -71,7 +71,7 @@ void sam_boardinitialize(void)
   * sam_spiinitialize() has been brought into the link.
   */

-#ifdef CONFIG_SAM34_SPI
+#ifdef CONFIG_SAM34_SPI0
  if (sam_spiinitialize)
    {
      sam_spiinitialize();
--- a/configs/sam4l-xplained/src/sam_mmcsd.c
+++ b/configs/sam4l-xplained/src/sam_mmcsd.c
@ -59,8 +59,8 @@
 #  error Mountpoints are disabled (CONFIG_DISABLE_MOUNTPOINT=y)
 #endif

-#ifndef CONFIG_SAM34_SPI
-#  error SPI support is required (CONFIG_SAM34_SPI)
+#ifndef CONFIG_SAM34_SPI0
+#  error SPI support is required (CONFIG_SAM34_SPI0)
 #endif

 #ifndef CONFIG_MMCSD
@ -81,7 +81,7 @@
 *   - CONFIG_SAM4L_XPLAINED_IOMODULE=y,
 *   - CONFIG_DISABLE_MOUNTPOINT=n,
 *   - CONFIG_MMCSD=y, and
- *   - CONFIG_SAM34_SPI=y
+ *   - CONFIG_SAM34_SPI0=y
 *
 *****************************************************************************/

--- a/configs/sam4l-xplained/src/sam_nsh.c
+++ b/configs/sam4l-xplained/src/sam_nsh.c
@ -112,7 +112,7 @@ int nsh_archinitialize(void)
      }
  }
 #endif
-#if defined(CONFIG_SAM34_SPI) && defined(CONFIG_SAM4L_XPLAINED_IOMODULE)
+#if defined(CONFIG_SAM34_SPI0) && defined(CONFIG_SAM4L_XPLAINED_IOMODULE)
  /* Initialize the SPI-based MMC/SD slot */

  {
--- a/configs/sam4l-xplained/src/sam_spi.c
+++ b/configs/sam4l-xplained/src/sam_spi.c
@ -49,7 +49,7 @@
 #include "sam_spi.h"
 #include "sam4l-xplained.h"

-#ifdef CONFIG_SAM34_SPI
+#ifdef CONFIG_SAM34_SPI0

 /************************************************************************************
 * Definitions
@ -236,7 +236,7 @@ uint8_t sam_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
  return ret;
 }

-#endif /* CONFIG_SAM34_SPI */
+#endif /* CONFIG_SAM34_SPI0 */

 /****************************************************************************
 * Name: sam_spicmddata
--- a/configs/sam4l-xplained/src/sam_ug2832hsweg04.c
+++ b/configs/sam4l-xplained/src/sam_ug2832hsweg04.c
@ -103,8 +103,8 @@
 #  error "The OLED driver requires CONFIG_LCD_UG2832HSWEG04 in the configuration"
 #endif

-#ifndef CONFIG_SAM34_SPI
-#  error "The OLED driver requires CONFIG_SAM34_SPI in the configuration"
+#ifndef CONFIG_SAM34_SPI0
+#  error "The OLED driver requires CONFIG_SAM34_SPI0 in the configuration"
 #endif

 #ifndef CONFIG_SPI_CMDDATA
--- a/configs/sam4s-xplained/README.txt
+++ b/configs/sam4s-xplained/README.txt
@ -444,7 +444,7 @@ SAM4S Xplained-specific Configuration Options
    CONFIG_SAM34_HSMCI       - High Speed Multimedia Card Interface
    CONFIG_SAM34_TWI0        - Two-Wire Interface 0
    CONFIG_SAM34_TWI1        - Two-Wire Interface 1
-    CONFIG_SAM34_SPI         - Serial Peripheral Interface
+    CONFIG_SAM34_SPI0        - Serial Peripheral Interface
    CONFIG_SAM34_SSC         - Synchronous Serial Controller
    CONFIG_SAM34_TC0         - Timer Counter 0
    CONFIG_SAM34_TC1         - Timer Counter 1
--- a/configs/sam4s-xplained/nsh/defconfig
+++ b/configs/sam4s-xplained/nsh/defconfig
@ -98,7 +98,13 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 # AT91SAM3/4 Configuration Options
 #
 # CONFIG_ARCH_CHIP_AT91SAM3U4E is not set
-# CONFIG_ARCH_CHIP_SAM34_NDMACHANC2C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X8E is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X8C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X4E is not set
+# CONFIG_ARCH_CHIP_AT91SAM3X4C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3A8C is not set
+# CONFIG_ARCH_CHIP_AT91SAM3A4C is not set
+# CONFIG_ARCH_CHIP_ATSAM4LC2C is not set
 # CONFIG_ARCH_CHIP_ATSAM4LC2B is not set
 # CONFIG_ARCH_CHIP_ATSAM4LC2A is not set
 # CONFIG_ARCH_CHIP_ATSAM4LC4C is not set
@ -121,13 +127,15 @@ CONFIG_ARCH_CHIP_ATSAM4S16C=y
 # CONFIG_ARCH_CHIP_ATSAM4S8C is not set
 # CONFIG_ARCH_CHIP_ATSAM4S8B is not set
 # CONFIG_ARCH_CHIP_SAM3U is not set
+# CONFIG_ARCH_CHIP_SAM3X is not set
+# CONFIG_ARCH_CHIP_SAM3A is not set
 # CONFIG_ARCH_CHIP_SAM4L is not set
 CONFIG_ARCH_CHIP_SAM4S=y

 #
 # AT91SAM3/4 Peripheral Support
 #
-# CONFIG_SAM34_SPI is not set
+# CONFIG_SAM34_SPI0 is not set
 # CONFIG_SAM34_SSC is not set
 # CONFIG_SAM34_TC0 is not set
 # CONFIG_SAM34_TC1 is not set
@ -652,6 +660,11 @@ CONFIG_NSH_CONSOLE=y
 # FLASH Erase-all Command
 #

+#
+# RAM test
+#
+# CONFIG_SYSTEM_RAMTEST is not set
+
 #
 # readline()
 #