diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index f8ece4d76b..960f1f80a2 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -337,11 +337,6 @@ config SAMA5_HSMCI2 depends on SAMA5_HAVE_HSMCI2 select ARCH_HAVE_SDIO -config SAMA5_SAIC - bool "Secure Advanced Interrupt Controller (SAIC)" - default n - depends on SAMA5_HAVE_SAIC - config SAMA5_SBM bool "Secure Box Module (SBM)" default n diff --git a/arch/arm/src/sama5/chip/sam_aic.h b/arch/arm/src/sama5/chip/sam_aic.h index f9b07e58b3..4da2cabb18 100644 --- a/arch/arm/src/sama5/chip/sam_aic.h +++ b/arch/arm/src/sama5/chip/sam_aic.h @@ -66,9 +66,13 @@ #define SAM_AIC_IDCR_OFFSET 0x0044 /* Interrupt Disable Command Register */ #define SAM_AIC_ICCR_OFFSET 0x0048 /* Interrupt Clear Command Register */ #define SAM_AIC_ISCR_OFFSET 0x004c /* Interrupt Set Command Register */ -#define SAM_AIC_FFER_OFFSET 0x0050 /* Fast Forcing Enable Register */ -#define SAM_AIC_FFDR_OFFSET 0x0054 /* Fast Forcing Disable Register */ -#define SAM_AIC_FFSR_OFFSET 0x0058 /* Fast Forcing Status Register */ + +#ifdef ATSAMA5D3 +# define SAM_AIC_FFER_OFFSET 0x0050 /* Fast Forcing Enable Register */ +# define SAM_AIC_FFDR_OFFSET 0x0054 /* Fast Forcing Disable Register */ +# define SAM_AIC_FFSR_OFFSET 0x0058 /* Fast Forcing Status Register */ +#endif + #define SAM_AIC_DCR_OFFSET 0x006c /* Debug Control Register */ #define SAM_AIC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ #define SAM_AIC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ @@ -93,13 +97,41 @@ #define SAM_AIC_IDCR (SAM_AIC_VBASE+SAM_AIC_IDCR_OFFSET) #define SAM_AIC_ICCR (SAM_AIC_VBASE+SAM_AIC_ICCR_OFFSET) #define SAM_AIC_ISCR (SAM_AIC_VBASE+SAM_AIC_ISCR_OFFSET) -#define SAM_AIC_FFER (SAM_AIC_VBASE+SAM_AIC_FFER_OFFSET) -#define SAM_AIC_FFDR (SAM_AIC_VBASE+SAM_AIC_FFDR_OFFSET) -#define SAM_AIC_FFSR (SAM_AIC_VBASE+SAM_AIC_FFSR_OFFSET) + +#ifdef ATSAMA5D3 +# define SAM_AIC_FFER (SAM_AIC_VBASE+SAM_AIC_FFER_OFFSET) +# define SAM_AIC_FFDR (SAM_AIC_VBASE+SAM_AIC_FFDR_OFFSET) +# define SAM_AIC_FFSR (SAM_AIC_VBASE+SAM_AIC_FFSR_OFFSET) +#endif + #define SAM_AIC_DCR (SAM_AIC_VBASE+SAM_AIC_DCR_OFFSET) #define SAM_AIC_WPMR (SAM_AIC_VBASE+SAM_AIC_WPMR_OFFSET) #define SAM_AIC_WPSR (SAM_AIC_VBASE+SAM_AIC_WPSR_OFFSET) +#ifdef SAMA5_HAVE_SAIC +# define SAM_SAIC_SSR (SAM_SAIC_VBASE+SAM_AIC_SSR_OFFSET) +# define SAM_SAIC_SMR (SAM_SAIC_VBASE+SAM_AIC_SMR_OFFSET) +# define SAM_SAIC_SVR (SAM_SAIC_VBASE+SAM_AIC_SVR_OFFSET) +# define SAM_SAIC_IVR (SAM_SAIC_VBASE+SAM_AIC_IVR_OFFSET) +# define SAM_SAIC_FVR (SAM_SAIC_VBASE+SAM_AIC_FVR_OFFSET) +# define SAM_SAIC_ISR (SAM_SAIC_VBASE+SAM_AIC_ISR_OFFSET) +# define SAM_SAIC_IPR0 (SAM_SAIC_VBASE+SAM_AIC_IPR0_OFFSET) +# define SAM_SAIC_IPR1 (SAM_SAIC_VBASE+SAM_AIC_IPR1_OFFSET) +# define SAM_SAIC_IPR2 (SAM_SAIC_VBASE+SAM_AIC_IPR2_OFFSET) +# define SAM_SAIC_IPR3 (SAM_SAIC_VBASE+SAM_AIC_IPR3_OFFSET) +# define SAM_SAIC_IMR (SAM_SAIC_VBASE+SAM_AIC_IMR_OFFSET) +# define SAM_SAIC_CISR (SAM_SAIC_VBASE+SAM_AIC_CISR_OFFSET) +# define SAM_SAIC_EOICR (SAM_SAIC_VBASE+SAM_AIC_EOICR_OFFSET) +# define SAM_SAIC_SPU (SAM_SAIC_VBASE+SAM_AIC_SPU_OFFSET) +# define SAM_SAIC_IECR (SAM_SAIC_VBASE+SAM_AIC_IECR_OFFSET) +# define SAM_SAIC_IDCR (SAM_SAIC_VBASE+SAM_AIC_IDCR_OFFSET) +# define SAM_SAIC_ICCR (SAM_SAIC_VBASE+SAM_AIC_ICCR_OFFSET) +# define SAM_SAIC_ISCR (SAM_SAIC_VBASE+SAM_AIC_ISCR_OFFSET) +# define SAM_SAIC_DCR (SAM_SAIC_VBASE+SAM_AIC_DCR_OFFSET) +# define SAM_SAIC_WPMR (SAM_SAIC_VBASE+SAM_AIC_WPMR_OFFSET) +# define SAM_SAIC_WPSR (SAM_SAIC_VBASE+SAM_AIC_WPSR_OFFSET) +#endif + /* AIC Register Bit Definitions *****************************************************/ /* Source Select Register */ @@ -131,7 +163,10 @@ /* Interrupt Pending Register 0-3 */ -#define AIC_IPR(pid) (1 << (pid)) +#define AIC_IPR0(pid) (1 << (pid)) +#define AIC_IPR1(pid) (1 << ((pid) - 32) +#define AIC_IPR2(pid) (1 << ((pid) - 64) +#define AIC_IPR3(pid) (1 << ((pid) - 96) /* Interrupt Mask Register */ @@ -164,17 +199,19 @@ #define AIC_ISCR_INTSET (1 << 0) /* Bit 0: Interrupt Set */ +#ifdef ATSAMA5D3 /* Fast Forcing Enable Register */ -#define AIC_FFER_FFEN (1 << 0) /* Bit 0: Fast Forcing Enable */ +# define AIC_FFER_FFEN (1 << 0) /* Bit 0: Fast Forcing Enable */ /* Fast Forcing Disable Register */ -#define AIC_FFDR_FFDIS (1 << 0) /* Bit 0: Fast Forcing Disable */ +# define AIC_FFDR_FFDIS (1 << 0) /* Bit 0: Fast Forcing Disable */ /* Fast Forcing Status Register */ -#define AIC_FFSR_FFS (1 << 0) /* Bit 0: Fast Forcing Status */ +# define AIC_FFSR_FFS (1 << 0) /* Bit 0: Fast Forcing Status */ +#endif /* Debug Control Register */ diff --git a/arch/arm/src/sama5/chip/sam_aximx.h b/arch/arm/src/sama5/chip/sam_aximx.h index 214ff8ae6c..7f86cc15e9 100644 --- a/arch/arm/src/sama5/chip/sam_aximx.h +++ b/arch/arm/src/sama5/chip/sam_aximx.h @@ -41,6 +41,8 @@ ************************************************************************************/ #include + +#include #include "chip/sam_memorymap.h" /************************************************************************************ @@ -66,6 +68,9 @@ */ #define AXIMX_REMAP_REMAP0 (1 << 0) /* Remap State 0 */ -#define AXIMX_REMAP_REMAP1 (1 << 1) /* Remap State 1 */ + +#ifdef ATSAMA5D3 +# define AXIMX_REMAP_REMAP1 (1 << 1) /* Remap State 1 */ +#endif #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AXIMX_H */ diff --git a/arch/arm/src/sama5/chip/sam_wdt.h b/arch/arm/src/sama5/chip/sam_wdt.h index ceae9f4581..e1407a2721 100644 --- a/arch/arm/src/sama5/chip/sam_wdt.h +++ b/arch/arm/src/sama5/chip/sam_wdt.h @@ -77,7 +77,11 @@ # define WDT_MR_WDV(n) ((uint32_t)(n) << WDT_MR_WDV_SHIFT) #define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ #define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ + +#ifdef ATSAMA5D3 +# define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ +#endif + #define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ #define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value */ #define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT)