Add Tiva CAN driver
This commit is contained in:
Matthew Trescott
hartmannathan
parent
0df313974c
commit
bc80bbddc7
@ -125,6 +125,7 @@ config ARCH_CHIP_TM4C123GH6PM
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select TIVA_HAVE_GPIOF_IRQS
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select TIVA_HAVE_ADC0
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select TIVA_HAVE_ADC1
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select TIVA_HAVE_CAN1
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select TIVA_HAVE_QEI0
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select TIVA_HAVE_QEI1
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@ -350,6 +351,7 @@ config ARCH_CHIP_TM4C
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select ARCH_HAVE_FPU
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select TIVA_HAVE_ADC0
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select TIVA_HAVE_ADC1
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select TIVA_HAVE_CAN0
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select TIVA_HAVE_I2C1
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select TIVA_HAVE_I2C2
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select TIVA_HAVE_I2C3
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@ -423,6 +425,21 @@ config TIVA_HAVE_ADC1
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bool
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default n
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config TIVA_CAN
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bool
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default n
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select ARCH_HAVE_CAN_ERRORS
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select CAN_TXREADY
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select CAN_USE_RTR
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config TIVA_HAVE_CAN0
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bool
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default n
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config TIVA_HAVE_CAN1
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bool
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default n
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config TIVA_QEI
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bool
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default n
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@ -582,6 +599,40 @@ config TIVA_ADC1
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depends on TIVA_HAVE_ADC0
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select TIVA_ADC
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config TIVA_CAN0
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bool "CAN0"
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default n
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depends on TIVA_HAVE_CAN0
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select CAN
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select TIVA_CAN
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config TIVA_CAN0_PRIO
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int "CAN0 kthread priority"
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default 300
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depends on TIVA_CAN0
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---help---
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The Tiva CAN driver retrieves messages using a kthread rather
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than in the ISR or using a work queue. The ISR signals the
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kthread, but the kthread can be preempted if needed. This
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option sets the thread priority for CAN module 0.
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config TIVA_CAN1
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bool "CAN1"
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default n
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depends on TIVA_HAVE_CAN1
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select CAN
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select TIVA_CAN
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config TIVA_CAN1_PRIO
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int "CAN1 kthread priority"
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default 300
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depends on TIVA_CAN1
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---help---
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The Tiva CAN driver retrieves messages using a kthread rather
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than in the ISR or using a work queue. The ISR signals the
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kthread, but the kthread can be preempted if needed. This
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option sets the thread priority for CAN module 1.
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config TIVA_QEI0
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bool "QEI0"
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default n
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@ -1461,6 +1512,97 @@ config TIVA_ADC_REGDEBUG
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endmenu # Tiva ADC Configuration
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endif # TIVA_ADC
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menu "CAN Driver Configuration"
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depends on TIVA_CAN
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config TIVA_CAN_REGDEBUG
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bool "CAN register level debug"
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depends on DEBUG_CAN_INFO
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default n
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---help---
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Output detailed register-level CAN device debug information.
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Requires also CONFIG_DEBUG_CAN_INFO.
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config TIVA_CAN_TX_FIFO_DEPTH
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int "Size of the hardware TX FIFO"
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range 1 31
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default 8
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---help---
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This number determines the depth of the hardware transmit
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FIFO, which cannot be resized. Using a transmit FIFO allows
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the application to transmit messages at maximum speed and
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reduces jitter caused by excessive interrupts. However, it
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occupies extra mailboxes that might be used for more fine-
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grained filtering; hence there is a trade-off.
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Because the mailboxes on the Tiva chips cannot be used as
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a ring buffer for outbound messages, a larger TX FIFO
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directly increases the maximum number of messages that
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can be sent in a "burst" at maximum speed.
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However, the TX FIFO makes implementation of
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"pre-arbitration" more difficult. Although the classic
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character device CAN model does not support this anyway,
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transmission of a higher-priority message would require
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cancelling and reenqueuing of the low-priority messages
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already in the hardware.
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config TIVA_CAN_DEFAULT_FIFO_DEPTH
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int "Default CAN message RX FIFO depth"
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range 1 31
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default 6
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---help---
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This number determines the default depth for all RX
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hardware FIFOs in the CAN module. The size of a FIFO can be
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adjusted at any time (and made deeper than this number if
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needed) via the various CANIOC_TIVA ioctls. However, this
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option is limited to 31 because the driver must allocate
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at least one mailbox for outbound (TX) messages. The default
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RX filter FIFO is set to allow any messages, but is
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reconfigured as soon as an application uses the
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CANIOC_ADD_STDFILTER or CANIOC_ADD_EXTFILTER.
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config TIVA_CAN_FILTERS_MAX
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int "Maximum number of CAN RX filters"
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range 1 31
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default 4
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---help---
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This number applies to both CAN0 and CAN1, if the chip has
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both. (This is the number of filters for each module, not the
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total for both CAN modules.)
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The Tiva CAN modules have 32 message objects. Only one is
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used for TX, so it is possible to have up to 31 unique
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RX filters. However, increasing the FIFO depth of a filter
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uses up message objects and reduces this number. Additionally,
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since the driver has to keep track of the message objects
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assigned to each filter, increasing the number of available
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filters increases the memory footprint even if the filters
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are not used (internally, it is a statically-allocated array).
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config TIVA_CAN_ERR_HANDLER_PER
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int "Rate-limited error handling period (milliseconds)"
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range 10 1000
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default 100
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depends on CAN_ERRORS
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---help---
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When error messages (CAN_ERRORS) are enabled, the Tiva
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CAN driver will disable interrupts for individual errors
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when the application fails to call read() quickly enough
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to keep up. This can easily happen during testing if no
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transceiver is connected and the application is trying
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to print error messages to a serial console.
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When this happens, the driver defers error reporting to
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a periodic task in the high-priority work queue. The task
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checks for errors and reports them at the specified
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interval. It is unlikely that the bus would be disturbed
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badly enough to cause interrupt overload and yet be usable
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for real-time communication, so successful transmission or
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reception of a message will return the driver to the
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normal interrupt handling mode.
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endmenu
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if TIVA_ETHERNET
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menu "Stellaris Ethernet Configuration"
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@ -138,6 +138,10 @@ ifeq ($(CONFIG_TIVA_ADC),y)
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CHIP_CSRCS += tiva_adclib.c
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endif
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ifeq ($(CONFIG_TIVA_CAN),y)
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CHIP_CSRCS += tiva_can.c
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endif
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ifeq ($(CONFIG_TIVA_ETHERNET),y)
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ifeq ($(CONFIG_ARCH_CHIP_LM3S),y)
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CHIP_CSRCS += lm3s_ethernet.c
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2409
arch/arm/src/tiva/common/tiva_can.c
Normal file
2409
arch/arm/src/tiva/common/tiva_can.c
Normal file
File diff suppressed because it is too large
Load Diff
459
arch/arm/src/tiva/hardware/tiva_can.h
Normal file
459
arch/arm/src/tiva/hardware/tiva_can.h
Normal file
@ -0,0 +1,459 @@
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/****************************************************************************
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* arch/arm/src/tiva/hardware/tiva_can.h
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*
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* Copyright (C) 2006-2020 Texas Instruments Incorporated.
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* All rights reserved.
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* Author: Matthew Trescott <matthewtrescott@gmail.com>
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*
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* From the TivaWare Peripheral Driver Library, with minor changes for
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* clarity and style.
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*
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* The TivaWare sample code has a BSD compatible license that requires this
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* copyright notice:
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*
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* Copyright (c) 2005-2020 Texas Instruments Incorporated.
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* All rights reserved.
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* Software License Agreement
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This is part of revision 2.2.0295 of the Tiva Peripheral Driver Library.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_CAN_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_CAN_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* The following are defines describing the CAN controller modules
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****************************************************************************/
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#define TIVA_CAN_NUM_IFACES 2 /* Number of sets of CANIF registers */
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/* Note: driver code uses a 32-bit bitmask to represent the message objects */
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#define TIVA_CAN_NUM_MBOXES 32 /* Number of slots in the message SRAM */
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/****************************************************************************
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* The following are defines for the CAN register offsets.
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****************************************************************************/
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#define TIVA_CAN_OFFSET_CTL 0x00000000 /* CAN Control */
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#define TIVA_CAN_OFFSET_STS 0x00000004 /* CAN Status */
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#define TIVA_CAN_OFFSET_ERR 0x00000008 /* CAN Error Counter */
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#define TIVA_CAN_OFFSET_BIT 0x0000000C /* CAN Bit Timing */
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#define TIVA_CAN_OFFSET_INT 0x00000010 /* CAN Interrupt */
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#define TIVA_CAN_OFFSET_TST 0x00000014 /* CAN Test */
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#define TIVA_CAN_OFFSET_BRPE 0x00000018 /* CAN Baud Rate Prescaler *
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* Extension */
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#define TIVA_CAN_OFFSET_IFACE1_BASE 0x00000020 /* CAN Interface 1 base */
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#define TIVA_CAN_OFFSET_IF1CRQ 0x00000020 /* CAN IF1 Command Request */
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#define TIVA_CAN_OFFSET_IF1CMSK 0x00000024 /* CAN IF1 Command Mask */
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#define TIVA_CAN_OFFSET_IF1MSK1 0x00000028 /* CAN IF1 Mask 1 */
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#define TIVA_CAN_OFFSET_IF1MSK2 0x0000002C /* CAN IF1 Mask 2 */
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#define TIVA_CAN_OFFSET_IF1ARB1 0x00000030 /* CAN IF1 Arbitration 1 */
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#define TIVA_CAN_OFFSET_IF1ARB2 0x00000034 /* CAN IF1 Arbitration 2 */
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#define TIVA_CAN_OFFSET_IF1MCTL 0x00000038 /* CAN IF1 Message Control */
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#define TIVA_CAN_OFFSET_IF1DA1 0x0000003C /* CAN IF1 Data A1 */
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#define TIVA_CAN_OFFSET_IF1DA2 0x00000040 /* CAN IF1 Data A2 */
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#define TIVA_CAN_OFFSET_IF1DB1 0x00000044 /* CAN IF1 Data B1 */
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#define TIVA_CAN_OFFSET_IF1DB2 0x00000048 /* CAN IF1 Data B2 */
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#define TIVA_CAN_OFFSET_IFACE2_BASE 0x00000080 /* CAN Interface 2 base */
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#define TIVA_CAN_OFFSET_IF2CRQ 0x00000080 /* CAN IF2 Command Request */
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#define TIVA_CAN_OFFSET_IF2CMSK 0x00000084 /* CAN IF2 Command Mask */
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#define TIVA_CAN_OFFSET_IF2MSK1 0x00000088 /* CAN IF2 Mask 1 */
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#define TIVA_CAN_OFFSET_IF2MSK2 0x0000008C /* CAN IF2 Mask 2 */
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#define TIVA_CAN_OFFSET_IF2ARB1 0x00000090 /* CAN IF2 Arbitration 1 */
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#define TIVA_CAN_OFFSET_IF2ARB2 0x00000094 /* CAN IF2 Arbitration 2 */
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#define TIVA_CAN_OFFSET_IF2MCTL 0x00000098 /* CAN IF2 Message Control */
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#define TIVA_CAN_OFFSET_IF2DA1 0x0000009C /* CAN IF2 Data A1 */
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#define TIVA_CAN_OFFSET_IF2DA2 0x000000A0 /* CAN IF2 Data A2 */
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#define TIVA_CAN_OFFSET_IF2DB1 0x000000A4 /* CAN IF2 Data B1 */
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#define TIVA_CAN_OFFSET_IF2DB2 0x000000A8 /* CAN IF2 Data B2 */
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#define TIVA_CAN_OFFSET_TXRQ1 0x00000100 /* CAN Transmission Request 1 */
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#define TIVA_CAN_OFFSET_TXRQ2 0x00000104 /* CAN Transmission Request 2 */
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#define TIVA_CAN_OFFSET_NWDA1 0x00000120 /* CAN New Data 1 */
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#define TIVA_CAN_OFFSET_NWDA2 0x00000124 /* CAN New Data 2 */
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#define TIVA_CAN_OFFSET_MSG1INT 0x00000140 /* CAN Message 1 *
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* Interrupt Pending */
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#define TIVA_CAN_OFFSET_MSG2INT 0x00000144 /* CAN Message 2 *
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* Interrupt Pending */
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#define TIVA_CAN_OFFSET_MSG1VAL 0x00000160 /* CAN Message 1 Valid */
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#define TIVA_CAN_OFFSET_MSG2VAL 0x00000164 /* CAN Message 2 Valid */
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/****************************************************************************
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* The following are defines for CAN registers
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****************************************************************************/
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#define TIVA_CAN_BASE(n) (TIVA_CAN0_BASE + (n)*0x1000)
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#define TIVA_CAN_CTL(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_CTL) /* CAN Control */
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#define TIVA_CAN_STS(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_STS) /* CAN Status */
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#define TIVA_CAN_ERR(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_ERR) /* CAN Error Counter */
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#define TIVA_CAN_BIT(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_BIT) /* CAN Bit Timing */
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#define TIVA_CAN_INT(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_INT) /* CAN Interrupt */
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#define TIVA_CAN_TST(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_TST) /* CAN Test */
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#define TIVA_CAN_BRPE(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_BRPE) /* CAN Baud Rate Prescaler *
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* Extension */
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#define TIVA_CAN_IF1CRQ(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1CRQ) /* CAN IF1 Command Request */
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#define TIVA_CAN_IF1CMSK(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1CMSK) /* CAN IF1 Command Mask */
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#define TIVA_CAN_IF1MSK1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1MSK1) /* CAN IF1 Mask 1 */
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#define TIVA_CAN_IF1MSK2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1MSK2) /* CAN IF1 Mask 2 */
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#define TIVA_CAN_IF1ARB1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1ARB1) /* CAN IF1 Arbitration 1 */
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#define TIVA_CAN_IF1ARB2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1ARB2) /* CAN IF1 Arbitration 2 */
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#define TIVA_CAN_IF1MCTL(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1MCTL) /* CAN IF1 Message Control */
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#define TIVA_CAN_IF1DA1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1DA1) /* CAN IF1 Data A1 */
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#define TIVA_CAN_IF1DA2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1DA2) /* CAN IF1 Data A2 */
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#define TIVA_CAN_IF1DB1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1DB1) /* CAN IF1 Data B1 */
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#define TIVA_CAN_IF1DB2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF1DB2) /* CAN IF1 Data B2 */
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#define TIVA_CAN_IF2CRQ(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2CRQ) /* CAN IF2 Command Request */
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#define TIVA_CAN_IF2CMSK(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2CMSK) /* CAN IF2 Command Mask */
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#define TIVA_CAN_IF2MSK1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2MSK1) /* CAN IF2 Mask 1 */
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#define TIVA_CAN_IF2MSK2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2MSK2) /* CAN IF2 Mask 2 */
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#define TIVA_CAN_IF2ARB1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2ARB1) /* CAN IF2 Arbitration 1 */
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#define TIVA_CAN_IF2ARB2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2ARB2) /* CAN IF2 Arbitration 2 */
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#define TIVA_CAN_IF2MCTL(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2MCTL) /* CAN IF2 Message Control */
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#define TIVA_CAN_IF2DA1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2DA1) /* CAN IF2 Data A1 */
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#define TIVA_CAN_IF2DA2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2DA2) /* CAN IF2 Data A2 */
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#define TIVA_CAN_IF2DB1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2DB1) /* CAN IF2 Data B1 */
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#define TIVA_CAN_IF2DB2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IF2DB2) /* CAN IF2 Data B2 */
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#define TIVA_CAN_TXRQ1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_TXRQ1) /* CAN Transmission Request 1 */
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#define TIVA_CAN_TXRQ2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_TXRQ2) /* CAN Transmission Request 2 */
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#define TIVA_CAN_NWDA1(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_NWDA1) /* CAN New Data 1 */
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#define TIVA_CAN_NWDA2(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_NWDA2) /* CAN New Data 2 */
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#define TIVA_CAN_MSG1INT(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_MSG1INT) /* CAN Message *
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* Interrupt Pending 2 */
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#define TIVA_CAN_MSG2INT(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_MSG2INT) /* CAN Message *
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* Interrupt Pending 2 */
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#define TIVA_CAN_MSG1VAL(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_MSG1VAL) /* CAN Message 1 Valid */
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#define TIVA_CAN_MSG2VAL(n) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_MSG2VAL) /* CAN Message 2 Valid */
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/****************************************************************************
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* The following are defines for CAN interface (CANIFn) register offsets.
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* Note that in these defines, the CAN interfaces are indexed from zero.
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****************************************************************************/
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|
||||
#define TIVA_CANIF_OFFSET_CRQ 0x00000000
|
||||
#define TIVA_CANIF_OFFSET_CMSK 0x00000004
|
||||
#define TIVA_CANIF_OFFSET_MSK1 0x00000008
|
||||
#define TIVA_CANIF_OFFSET_MSK2 0x0000000C
|
||||
#define TIVA_CANIF_OFFSET_ARB1 0x00000010
|
||||
#define TIVA_CANIF_OFFSET_ARB2 0x00000014
|
||||
#define TIVA_CANIF_OFFSET_MCTL 0x00000018
|
||||
#define TIVA_CANIF_OFFSET_DA1 0x0000001C
|
||||
#define TIVA_CANIF_OFFSET_DA2 0x00000020
|
||||
#define TIVA_CANIF_OFFSET_DB1 0x00000024
|
||||
#define TIVA_CANIF_OFFSET_DB2 0x00000028
|
||||
|
||||
#define TIVA_CANIF_OFFSET_DATA(n) (TIVA_CANIF_OFFSET_DA1 + (n) * 0x4)
|
||||
|
||||
#define TIVA_CAN_OFFSET_IFACE(i) (TIVA_CAN_OFFSET_IFACE1_BASE + (i) * 0x60)
|
||||
#define TIVA_CAN_IFACE_BASE(n,i) (TIVA_CAN_BASE(n)+TIVA_CAN_OFFSET_IFACE(i))
|
||||
|
||||
#define TIVA_CANIF_CRQ(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_CRQ)
|
||||
#define TIVA_CANIF_CMSK(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_CMSK)
|
||||
#define TIVA_CANIF_MSK1(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_MSK1)
|
||||
#define TIVA_CANIF_MSK2(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_MSK2)
|
||||
#define TIVA_CANIF_ARB1(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_ARB1)
|
||||
#define TIVA_CANIF_ARB2(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_ARB2)
|
||||
#define TIVA_CANIF_MCTL(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_MCTL)
|
||||
#define TIVA_CANIF_DA1(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_DA1)
|
||||
#define TIVA_CANIF_DA2(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_DA2)
|
||||
#define TIVA_CANIF_DB1(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_DB1)
|
||||
#define TIVA_CANIF_DB2(n,i) (TIVA_CAN_IFACE_BASE((n),(i))+TIVA_CANIF_OFFSET_DB2)
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANCTL register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_CTL_TEST 0x00000080 /* Test Mode Enable */
|
||||
#define TIVA_CAN_CTL_CCE 0x00000040 /* Configuration Change Enable */
|
||||
#define TIVA_CAN_CTL_DAR 0x00000020 /* Disable Automatic-Retransmission */
|
||||
#define TIVA_CAN_CTL_EIE 0x00000008 /* Error Interrupt Enable */
|
||||
#define TIVA_CAN_CTL_SIE 0x00000004 /* Status Interrupt Enable */
|
||||
#define TIVA_CAN_CTL_IE 0x00000002 /* CAN Interrupt Enable */
|
||||
#define TIVA_CAN_CTL_INIT 0x00000001 /* Initialization */
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANSTS register
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_STS_BOFF 0x00000080 /* Bus-Off Status */
|
||||
#define TIVA_CAN_STS_EWARN 0x00000040 /* Warning Status */
|
||||
#define TIVA_CAN_STS_EPASS 0x00000020 /* Error Passive */
|
||||
#define TIVA_CAN_STS_RXOK 0x00000010 /* Received a Message Successfully */
|
||||
#define TIVA_CAN_STS_TXOK 0x00000008 /* Transmitted a Message */
|
||||
/* Successfully */
|
||||
#define TIVA_CAN_STS_LEC_MASK 0x00000007 /* Last Error Code */
|
||||
#define TIVA_CAN_STS_LEC_NONE 0x00000000 /* No Error */
|
||||
#define TIVA_CAN_STS_LEC_STUFF 0x00000001 /* Stuff Error */
|
||||
#define TIVA_CAN_STS_LEC_FORM 0x00000002 /* Format Error */
|
||||
#define TIVA_CAN_STS_LEC_ACK 0x00000003 /* ACK Error */
|
||||
#define TIVA_CAN_STS_LEC_BIT1 0x00000004 /* Bit 1 Error */
|
||||
#define TIVA_CAN_STS_LEC_BIT0 0x00000005 /* Bit 0 Error */
|
||||
#define TIVA_CAN_STS_LEC_CRC 0x00000006 /* CRC Error */
|
||||
#define TIVA_CAN_STS_LEC_NOEVENT 0x00000007 /* No Event */
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANERR register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_ERR_RP 0x00008000 /* Received Error Passive */
|
||||
#define TIVA_CAN_ERR_REC_MASK 0x00007F00 /* Receive Error Counter */
|
||||
#define TIVA_CAN_ERR_TEC_MASK 0x000000FF /* Transmit Error Counter */
|
||||
#define TIVA_CAN_ERR_REC_SHIFT 8
|
||||
#define TIVA_CAN_ERR_TEC_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANBIT register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_BIT_TSEG2_MASK 0x00007000 /* Time Segment after Sample Point */
|
||||
#define TIVA_CAN_BIT_TSEG1_MASK 0x00000F00 /* Time Segment Before Sample Point */
|
||||
#define TIVA_CAN_BIT_SJW_MASK 0x000000C0 /* (Re)Synchronization Jump Width */
|
||||
#define TIVA_CAN_BIT_BRP_MASK 0x0000003F /* Baud Rate Prescaler */
|
||||
#define TIVA_CAN_BIT_TSEG2_SHIFT 12
|
||||
#define TIVA_CAN_BIT_TSEG1_SHIFT 8
|
||||
#define TIVA_CAN_BIT_SJW_SHIFT 6
|
||||
#define TIVA_CAN_BIT_BRP_SHIFT 0
|
||||
#define TIVA_CAN_BIT_BRP_LENGTH 6 /* This is also the number of bits to shift the BRPE by */
|
||||
|
||||
#define TIVA_CAN_PRESCALER_MIN 1
|
||||
#define TIVA_CAN_PRESCALER_MAX 1024
|
||||
#define TIVA_CAN_TSEG1_MIN 1
|
||||
#define TIVA_CAN_TSEG1_MAX 16
|
||||
#define TIVA_CAN_TSEG2_MIN 1
|
||||
#define TIVA_CAN_TSEG2_MAX 8
|
||||
#define TIVA_CAN_SJW_MIN 1
|
||||
#define TIVA_CAN_SJW_MAX 4
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANINT register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_INT_INTID_MASK 0x0000FFFF /* Interrupt Identifier */
|
||||
#define TIVA_CAN_INT_INTID_NONE 0x00000000 /* No interrupt pending */
|
||||
#define TIVA_CAN_INT_INTID_STATUS 0x00008000 /* Status Interrupt */
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANTST register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_TST_RX 0x00000080 /* Receive Observation */
|
||||
#define TIVA_CAN_TST_TX_MASK 0x00000060 /* Transmit Control */
|
||||
#define TIVA_CAN_TST_TX_CANCTL 0x00000000 /* CAN Module Control */
|
||||
#define TIVA_CAN_TST_TX_SAMPLE 0x00000020 /* Sample Point */
|
||||
#define TIVA_CAN_TST_TX_DOMINANT 0x00000040 /* Driven Low */
|
||||
#define TIVA_CAN_TST_TX_RECESSIVE 0x00000060 /* Driven High */
|
||||
#define TIVA_CAN_TST_LBACK 0x00000010 /* Loopback Mode */
|
||||
#define TIVA_CAN_TST_SILENT 0x00000008 /* Silent Mode */
|
||||
#define TIVA_CAN_TST_BASIC 0x00000004 /* Basic Mode */
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANBRPE register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_BRPE_BRPE_MASK 0x0000000F /* Baud Rate Prescaler Extension */
|
||||
#define TIVA_CAN_BRPE_BRPE_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANIF1CRQ register.
|
||||
****************************************************************************/
|
||||
#define TIVA_CANIF_CRQ_BUSY 0x00008000 /* Busy Flag */
|
||||
#define TIVA_CANIF_CRQ_MNUM_MASK 0x0000003F /* Message Number */
|
||||
#define TIVA_CANIF_CRQ_MNUM_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANIF1CMSK register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CANIF_CMSK_WRNRD 0x00000080 /* Write, Not Read */
|
||||
#define TIVA_CANIF_CMSK_MASK 0x00000040 /* Access Mask Bits */
|
||||
#define TIVA_CANIF_CMSK_ARB 0x00000020 /* Access Arbitration Bits */
|
||||
#define TIVA_CANIF_CMSK_CONTROL 0x00000010 /* Access Control Bits */
|
||||
#define TIVA_CANIF_CMSK_CLRINTPND 0x00000008 /* Clear Interrupt Pending Bit */
|
||||
#define TIVA_CANIF_CMSK_NEWDAT 0x00000004 /* Access New Data */
|
||||
#define TIVA_CANIF_CMSK_TXRQST 0x00000004 /* Access Transmission Request */
|
||||
#define TIVA_CANIF_CMSK_DATAA 0x00000002 /* Access Data Byte 0 to 3 */
|
||||
#define TIVA_CANIF_CMSK_DATAB 0x00000001 /* Access Data Byte 4 to 7 */
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANIF1MSK1 register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CANIF_MSK1_IDMSK_EXT_MASK 0x0000FFFF /* Identifier mask for lower 16 bits of extended ID */
|
||||
#define TIVA_CANIF_MSK1_IDMSK_EXT_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANIF1MSK2 register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CANIF_MSK2_MXTD 0x00008000 /* Mask Extended Identifier */
|
||||
#define TIVA_CANIF_MSK2_MDIR 0x00004000 /* Mask Message Direction */
|
||||
#define TIVA_CANIF_MSK2_IDMSK_EXT_MASK 0x00001FFF /* Identifier Mask for upper 13 bits of extended ID */
|
||||
#define TIVA_CANIF_MSK2_IDMSK_EXT_SHIFT 0 /* Shift LEFT by this number to place a value in this field */
|
||||
#define TIVA_CANIF_MSK2_IDMSK_EXT_PRESHIFT 16 /* Shift RIGHT by this number to get the chunk this register wants */
|
||||
|
||||
#define TIVA_CANIF_MSK2_IDMSK_STD_MASK 0x00001FFC /* MSK2 contains all 11 bits of a standard ID, but not aligned with 0 */
|
||||
#define TIVA_CANIF_MSK2_IDMSK_STD_SHIFT 2 /* Shift LEFT by this number to place a value in this field */
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANIF1ARB1 register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CANIF_ARB1_ID_EXT_MASK 0x0000FFFF /* Identifier for lower 16 bits of extended ID */
|
||||
#define TIVA_CANIF_ARB1_ID_EXT_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANIF1ARB2 register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CANIF_ARB2_MSGVAL 0x00008000 /* Message Valid */
|
||||
#define TIVA_CANIF_ARB2_XTD 0x00004000 /* Extended Identifier */
|
||||
#define TIVA_CANIF_ARB2_DIR 0x00002000 /* Message Direction */
|
||||
#define TIVA_CANIF_ARB2_ID_EXT_MASK 0x00001FFF /* Message Identifier */
|
||||
#define TIVA_CANIF_ARB2_ID_EXT_SHIFT 0 /* Shift LEFT by this number to place a value in this filed */
|
||||
#define TIVA_CANIF_ARB2_ID_EXT_PRESHIFT 16 /* Shift RIGHT by this number to get the chunk this register wants */
|
||||
|
||||
#define TIVA_CANIF_ARB2_ID_STD_MASK 0x00001FFC /* ARB2 contains all 11 bits of a standard ID, but not aligned with 0 */
|
||||
#define TIVA_CANIF_ARB2_ID_STD_SHIFT 2 /* Shift LEFT by this number to place a value in this field */
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANIF1MCTL register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CANIF_MCTL_NEWDAT 0x00008000 /* New Data */
|
||||
#define TIVA_CANIF_MCTL_MSGLST 0x00004000 /* Message Lost */
|
||||
#define TIVA_CANIF_MCTL_INTPND 0x00002000 /* Interrupt Pending */
|
||||
#define TIVA_CANIF_MCTL_UMASK 0x00001000 /* Use Acceptance Mask */
|
||||
#define TIVA_CANIF_MCTL_TXIE 0x00000800 /* Transmit Interrupt Enable */
|
||||
#define TIVA_CANIF_MCTL_RXIE 0x00000400 /* Receive Interrupt Enable */
|
||||
#define TIVA_CANIF_MCTL_RMTEN 0x00000200 /* Remote Enable */
|
||||
#define TIVA_CANIF_MCTL_TXRQST 0x00000100 /* Transmit Request */
|
||||
#define TIVA_CANIF_MCTL_EOB 0x00000080 /* End of Buffer */
|
||||
#define TIVA_CANIF_MCTL_DLC_MASK 0x0000000F /* Data Length Code */
|
||||
#define TIVA_CANIF_MCTL_DLC_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANIF1D(A,B)(1,2)
|
||||
* registers. H and L refer to high and low bytes in network byte order.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CANIF_DATA_HBYTE_MASK 0x000000FF
|
||||
#define TIVA_CANIF_DATA_HBYTE_SHIFT 0
|
||||
#define TIVA_CANIF_DATA_LBYTE_MASK 0x0000FF00
|
||||
#define TIVA_CANIF_DATA_LBYTE_SHIFT 8
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANTXRQ1 register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_TXRQ1_TXRQST_MASK 0x0000FFFF /* Transmission Request Bits */
|
||||
#define TIVA_CAN_TXRQ1_TXRQST_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANTXRQ2 register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_TXRQ2_TXRQST_MASK 0x0000FFFF /* Transmission Request Bits */
|
||||
#define TIVA_CAN_TXRQ2_TXRQST_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANNWDA1 register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_NWDA1_NEWDAT_MASK 0x0000FFFF /* New Data Bits */
|
||||
#define TIVA_CAN_NWDA1_NEWDAT_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANNWDA2 register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_NWDA2_NEWDAT_MASK 0x0000FFFF /* New Data Bits */
|
||||
#define TIVA_CAN_NWDA2_NEWDAT_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANMSG1INT register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_MSG1INT_INTPND_MASK 0x0000FFFF /* Interrupt Pending Bits */
|
||||
#define TIVA_CAN_MSG1INT_INTPND_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANMSG2INT register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_MSG2INT_INTPND_MASK 0x0000FFFF /* Interrupt Pending Bits */
|
||||
#define TIVA_CAN_MSG2INT_INTPND_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANMSG1VAL register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_MSG1VAL_MSGVAL_MASK 0x0000FFFF /* Message Valid Bits */
|
||||
#define TIVA_CAN_MSG1VAL_MSGVAL_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* The following are defines for the bit fields in the CANMSG2VAL register.
|
||||
****************************************************************************/
|
||||
|
||||
#define TIVA_CAN_MSG2VAL_MSGVAL_MASK 0x0000FFFF /* Message Valid Bits */
|
||||
#define TIVA_CAN_MSG2VAL_MSGVAL_SHIFT 0
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_CAN_H */
|
||||
89
arch/arm/src/tiva/tiva_can.h
Normal file
89
arch/arm/src/tiva/tiva_can.h
Normal file
@ -0,0 +1,89 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/tiva/tiva_can.h
|
||||
* Classic (character-device) lower-half driver for the Tiva CAN modules.
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_TIVA_CAN_H
|
||||
#define __ARCH_ARM_SRC_TIVA_TIVA_CAN_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/can/can.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_CAN) && (defined(CONFIG_TIVA_CAN0) || defined(CONFIG_TIVA_CAN1))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tiva_can_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected CAN module
|
||||
*
|
||||
* Input Parameters:
|
||||
* Device path, a string of the form "/dev/can0" or "/dev/can1"
|
||||
* Module number, for chips with multiple modules (typically 0 or 1)
|
||||
*
|
||||
* Returned Value:
|
||||
* Pointer to can_dev_s (CAN device structure), or NULL on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int tiva_can_initialize(FAR char *devpath, int modnum);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_CAN && (CONFIG_TIVA_CAN0 || CONFIG_TIVA_CAN1) */
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_CAN_H */
|
||||
@ -43,4 +43,36 @@ config TM4C123G_LAUNCHPAD_AT24_NXFFS
|
||||
|
||||
endchoice # AT24 serial EPPROM configuration
|
||||
|
||||
choice
|
||||
prompt "CAN0 RX pin selection"
|
||||
default TM4C123G_LAUNCHPAD_CAN0RX_PE4
|
||||
depends on TIVA_CAN0
|
||||
|
||||
config TM4C123G_LAUNCHPAD_CAN0RX_PF0
|
||||
bool "Use pin 0 on GPIO port F"
|
||||
|
||||
config TM4C123G_LAUNCHPAD_CAN0RX_PB4
|
||||
bool "Use pin 4 on GPIO port B"
|
||||
|
||||
config TM4C123G_LAUNCHPAD_CAN0RX_PE4
|
||||
bool "Use pin 4 on GPIO port E"
|
||||
|
||||
endchoice # CAN0 RX pin selection
|
||||
|
||||
choice
|
||||
prompt "CAN0 TX pin selection"
|
||||
default TM4C123G_LAUNCHPAD_CAN0TX_PE5
|
||||
depends on TIVA_CAN0
|
||||
|
||||
config TM4C123G_LAUNCHPAD_CAN0TX_PF3
|
||||
bool "Use pin 3 on GPIO port F"
|
||||
|
||||
config TM4C123G_LAUNCHPAD_CAN0TX_PB5
|
||||
bool "Use pin 5 on GPIO port B"
|
||||
|
||||
config TM4C123G_LAUNCHPAD_CAN0TX_PE5
|
||||
bool "Use pin 5 on GPIO port E"
|
||||
|
||||
endchoice # CAN0 TX pin selection
|
||||
|
||||
endif
|
||||
|
||||
@ -180,4 +180,26 @@
|
||||
#define GPIO_UART1_RX GPIO_UART1_RX_1
|
||||
#define GPIO_UART1_TX GPIO_UART1_TX_1
|
||||
|
||||
/* CAN0 pin mux selection - defaults to port E in Kconfig */
|
||||
#ifdef CONFIG_TIVA_CAN0
|
||||
# ifdef CONFIG_TM4C123G_LAUNCHPAD_CAN0RX_PF0
|
||||
# define GPIO_CAN0_RX GPIO_CAN0_RX_1
|
||||
# endif
|
||||
# ifdef CONFIG_TM4C123G_LAUNCHPAD_CAN0RX_PB4
|
||||
# define GPIO_CAN0_RX GPIO_CAN0_RX_2
|
||||
# endif
|
||||
# ifdef CONFIG_TM4C123G_LAUNCHPAD_CAN0RX_PE4
|
||||
# define GPIO_CAN0_RX GPIO_CAN0_RX_3
|
||||
# endif
|
||||
# ifdef CONFIG_TM4C123G_LAUNCHPAD_CAN0TX_PF3
|
||||
# define GPIO_CAN0_TX GPIO_CAN0_TX_1
|
||||
# endif
|
||||
# ifdef CONFIG_TM4C123G_LAUNCHPAD_CAN0TX_PB5
|
||||
# define GPIO_CAN0_TX GPIO_CAN0_TX_2
|
||||
# endif
|
||||
# ifdef CONFIG_TM4C123G_LAUNCHPAD_CAN0TX_PE5
|
||||
# define GPIO_CAN0_TX GPIO_CAN0_TX_3
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* __BOARDS_ARM_TMC4C123G_LAUNCHPAD_INCLUDE_BOARD_H */
|
||||
|
||||
@ -38,6 +38,10 @@ ifeq ($(CONFIG_TIVA_ADC),y)
|
||||
CSRCS += tm4c_adc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_TIVA_CAN),y)
|
||||
CSRCS += tm4c_can.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_CAN_MCP2515),y)
|
||||
CSRCS += tm4c_mcp2515.c
|
||||
endif
|
||||
|
||||
@ -233,6 +233,18 @@ int tm4c_bringup(void);
|
||||
int tm4c_adc_setup(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tm4c_can_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize CAN modules and register the CAN driver.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_TIVA_CAN
|
||||
int tm4c_can_setup(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tm4c_at24_automount
|
||||
*
|
||||
|
||||
@ -58,6 +58,16 @@ int tm4c_bringup(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TIVA_CAN
|
||||
/* Initialize CAN module and register the CAN driver(s) */
|
||||
|
||||
ret = tm4c_can_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: tm4c_can_setup failed %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_AT24
|
||||
/* Initialize the AT24 driver */
|
||||
|
||||
|
||||
153
boards/arm/tiva/tm4c123g-launchpad/src/tm4c_can.c
Normal file
153
boards/arm/tiva/tm4c123g-launchpad/src/tm4c_can.c
Normal file
@ -0,0 +1,153 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/tiva/tm4c123g-launchpad/src/tm4c_can.c
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2020 Matthew Trescott
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Based heavily on stm32_can.c from the boards directory.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/can/can.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_internal.h"
|
||||
|
||||
#include "tiva_can.h"
|
||||
#include "tm4c123g-launchpad.h"
|
||||
|
||||
#include "tiva_enableclks.h"
|
||||
#include "tiva_gpio.h"
|
||||
#include "hardware/tiva_pinmap.h"
|
||||
|
||||
#ifdef CONFIG_CAN
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tm4c_can_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize CAN and register the CAN device
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int tm4c_can_setup(void)
|
||||
{
|
||||
#ifdef CONFIG_TIVA_CAN
|
||||
int ret;
|
||||
|
||||
# ifdef CONFIG_TIVA_CAN0
|
||||
tiva_can0_enableclk();
|
||||
|
||||
ret = tiva_configgpio(GPIO_CAN0_RX);
|
||||
|
||||
if (ret < 0)
|
||||
{
|
||||
goto configgpio_error;
|
||||
}
|
||||
|
||||
ret = tiva_configgpio(GPIO_CAN0_TX);
|
||||
|
||||
if (ret < 0)
|
||||
{
|
||||
goto configgpio_error;
|
||||
}
|
||||
|
||||
/* Call tiva_can_initialize() to get an instance of CAN interface 0
|
||||
* and register it.
|
||||
*/
|
||||
|
||||
ret = tiva_can_initialize("/dev/can0", 0);
|
||||
if (ret < 0)
|
||||
{
|
||||
canerr("ERROR: Failed to get/register CAN interface 0\n");
|
||||
return ret;
|
||||
}
|
||||
# endif /* CONFIG_TIVA_CAN0 */
|
||||
|
||||
# ifdef CONFIG_TIVA_CAN1
|
||||
tiva_can1_enableclk();
|
||||
|
||||
ret = tiva_configgpio(GPIO_CAN1_RX);
|
||||
|
||||
if (ret < 0)
|
||||
{
|
||||
goto configgpio_error;
|
||||
}
|
||||
|
||||
ret = tiva_configgpio(GPIO_CAN1_TX);
|
||||
|
||||
if (ret < 0)
|
||||
{
|
||||
goto configgpio_error;
|
||||
}
|
||||
|
||||
/* Call tiva_can_initialize() to get an instance of CAN interface 1
|
||||
* and register it.
|
||||
*/
|
||||
|
||||
ret = tiva_can_initialize("/dev/can1", 1);
|
||||
if (ret < 0)
|
||||
{
|
||||
canerr("ERROR: Failed to get/register CAN interface 1\n");
|
||||
return ret;
|
||||
}
|
||||
# endif /* CONFIG_TIVA_CAN1 */
|
||||
|
||||
return OK;
|
||||
|
||||
configgpio_error:
|
||||
canerr("ERROR: failed to configure CAN GPIO pin.\n");
|
||||
return ret;
|
||||
#else
|
||||
return -ENODEV;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CAN */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user