From bcfabcbe5309d2ec0fa7f8dc2b31484c67247f6a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 12 Aug 2019 12:10:54 -0600 Subject: [PATCH] This commit brings the initial files for a port to the NXP S32K1xx family. This is very much a work in progress and is little more that a partial configuration/build environment and some S32K1xx register definition header files Squashed commit of the following: arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h: Add MCM register definition file. arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h: Add memory map definition file. arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h: Add CMU register definition file. arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h: Add PCC register definition file. arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h: Add SCG register definition file. arch/arm/src/s32k1xx: Add initial Make.defs files. Basic configuration logic for the S32K1 family. --- arch/arm/Kconfig | 11 + arch/arm/include/s32k1xx/chip.h | 61 ++++ arch/arm/include/s32k1xx/irq.h | 57 +++ arch/arm/include/s32k1xx/s32k11x_irq.h | 76 ++++ arch/arm/include/s32k1xx/s32k14x_irq.h | 82 +++++ arch/arm/src/s32k1xx/Kconfig | 122 +++++++ arch/arm/src/s32k1xx/Make.defs | 67 ++++ arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h | 114 ++++++ arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h | 271 ++++++++++++++ .../src/s32k1xx/hardware/s32k1xx_memorymap.h | 125 +++++++ arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h | 172 +++++++++ arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h | 344 ++++++++++++++++++ arch/arm/src/s32k1xx/s32K11x/Make.defs | 72 ++++ arch/arm/src/s32k1xx/s32K14x/Make.defs | 90 +++++ 14 files changed, 1664 insertions(+) create mode 100644 arch/arm/include/s32k1xx/chip.h create mode 100644 arch/arm/include/s32k1xx/irq.h create mode 100644 arch/arm/include/s32k1xx/s32k11x_irq.h create mode 100644 arch/arm/include/s32k1xx/s32k14x_irq.h create mode 100644 arch/arm/src/s32k1xx/Kconfig create mode 100644 arch/arm/src/s32k1xx/Make.defs create mode 100644 arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h create mode 100644 arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h create mode 100644 arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h create mode 100644 arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h create mode 100644 arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h create mode 100644 arch/arm/src/s32k1xx/s32K11x/Make.defs create mode 100644 arch/arm/src/s32k1xx/s32K14x/Make.defs diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b94d9a43ec..68baff4a46 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -212,6 +212,13 @@ config ARCH_CHIP_NUC1XX ---help--- Nuvoton NUC100/120 architectures (ARM Cortex-M0). +config ARCH_CHIP_S32K1XX + bool "NXP S32K1XX" + select ARCH_HAVE_MPU + select ARM_HAVE_MPU_UNIFIED + ---help--- + NPX LPC54XX architectures (ARM Cortex-M0+ and Cortex-M4F). + config ARCH_CHIP_SAMA5 bool "Atmel SAMA5" select ARCH_CORTEXA5 @@ -670,6 +677,7 @@ config ARCH_CHIP default "moxart" if ARCH_CHIP_MOXART default "nrf52" if ARCH_CHIP_NRF52 default "nuc1xx" if ARCH_CHIP_NUC1XX + default "s32k1xx" if ARCH_CHIP_S32K1XX default "sama5" if ARCH_CHIP_SAMA5 default "samd2l2" if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X @@ -888,6 +896,9 @@ endif if ARCH_CHIP_LPC54XX source arch/arm/src/lpc54xx/Kconfig endif +if ARCH_CHIP_S32K1XX +source arch/arm/src/s32k1xx/Kconfig +endif if ARCH_CHIP_MAX326XX source arch/arm/src/max326xx/Kconfig endif diff --git a/arch/arm/include/s32k1xx/chip.h b/arch/arm/include/s32k1xx/chip.h new file mode 100644 index 0000000000..a851425b15 --- /dev/null +++ b/arch/arm/include/s32k1xx/chip.h @@ -0,0 +1,61 @@ +/************************************************************************************ + * arch/arm/include/x32k1xx/chip.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_S32K1XX_CHIP_H +#define __ARCH_ARM_INCLUDE_S32K1XX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_S32K1XX_CHIP_H */ diff --git a/arch/arm/include/s32k1xx/irq.h b/arch/arm/include/s32k1xx/irq.h new file mode 100644 index 0000000000..6c8311476d --- /dev/null +++ b/arch/arm/include/s32k1xx/irq.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm/include/s32k1xx/irq.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_S32K1XX_IRQ_H +#define __ARCH_ARM_INCLUDE_S32K1XX_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_S32K11X) +# include + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_S32K1XX_S32K11XX_IRQ_H +#define __ARCH_ARM_INCLUDE_S32K1XX_S32K11XX_IRQ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define S32K_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define S32K_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define S32K_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vector 4-10: Reserved */ +#define S32K_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define S32K_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define S32K_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). These definitions are chip-specific */ + +#define S32K_IRQ_INTERRUPT (16) +#warning Missing logic + +#endif /* __ARCH_ARM_INCLUDE_S32K1XX_S32K11XX_IRQ_H */ diff --git a/arch/arm/include/s32k1xx/s32k14x_irq.h b/arch/arm/include/s32k1xx/s32k14x_irq.h new file mode 100644 index 0000000000..2df7cca8ad --- /dev/null +++ b/arch/arm/include/s32k1xx/s32k14x_irq.h @@ -0,0 +1,82 @@ +/************************************************************************************ + * arch/arm/include/s32k1xx/s32k14x_irq.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_S32K1XX_S32K14XX_IRQ_H +#define __ARCH_ARM_INCLUDE_S32K1XX_S32K14XX_IRQ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define S32K_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define S32K_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define S32K_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define S32K_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define S32K_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define S32K_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define S32K_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define S32K_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define S32K_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define S32K_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). These definitions are chip-specific */ + +#define S32K_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#warning Missing logic + +#endif /* __ARCH_ARM_INCLUDE_S32K1XX_S32K14XX_IRQ_H */ + diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig new file mode 100644 index 0000000000..b4a53a5ecf --- /dev/null +++ b/arch/arm/src/s32k1xx/Kconfig @@ -0,0 +1,122 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_S32K1XX + +# Chip Selection + +choice + prompt "S32K1XX Chip Selection" + default ARCH_CHIP_S32K146 + +config ARCH_CHIP_S32K116 + bool "S32K116" + select ARCH_CHIP_S32K11X + ---help--- + Cortex-M0+, 128Kb FLASH, 17Kb RAM incl. 2Kb FlexRAM + +config ARCH_CHIP_S32K118 + bool "S32K118" + select ARCH_CHIP_S32K11X + ---help--- + Cortex-M0+, 256Kb FLASH, 25Kb RAM incl. 2Kb FlexRAM + +config ARCH_CHIP_S32K142 + bool "S32K142" + select ARCH_CHIP_S32K14X + ---help--- + Cortex-M4F, 256Kb FLASH, 32Kb RAM incl. 4Kb FlexRAM + +config ARCH_CHIP_S32K144 + bool "S32K144" + select ARCH_CHIP_S32K14X + ---help--- + Cortex-M4F, 512Kb FLASH, 64Kb RAM incl. 4Kb FlexRAM + +config ARCH_CHIP_S32K146 + bool "S32K146" + select ARCH_CHIP_S32K14X + ---help--- + Cortex-M4F, 1Mb FLASH, 128Kb RAM incl. 4Kb FlexRAM + +config ARCH_CHIP_S32K148 + bool "S32K148" + select ARCH_CHIP_S32K14X + select S32K1XX_HAVE_ETHMAC + select S32K1XX_HAVE_SAI + ---help--- + Cortex-M4F, 2Mb FLASH, 256Kb RAM incl. 4Kb FlexRAM + +endchoice # S32K1XX Chip Selection + +# Chip Family + +config ARCH_CHIP_S32K11X + bool + select ARCH_CORTEXM0 + select S32K1XX_HAVE_FIRC_CMU + +config ARCH_CHIP_S32K14X + bool + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select ARCH_HAVE_FETCHADD + select S32K1XX_HAVE_EWM + select S32K1XX_HAVE_HSRUN + +# Chip Capabilities + +config S32K1XX_HAVE_ETHMAC + bool + default n + +config S32K1XX_HAVE_EWM + bool + default n + +config S32K1XX_HAVE_FIRC_CMU + bool + default n + +config S32K1XX_HAVE_HSRUN + bool + default n + +config S32K1XX_HAVE_SAI + bool + default n + +# Peripheral Selection + +menu "S32K1XX Peripheral Selection" + +config S32K1XX_LPUART0 + bool "LPUART0" + default n + select LPUART0_SERIALDRIVER + +config S32K1XX_LPUART1 + bool "LPUART1" + default n + select LPUART1_SERIALDRIVER + +config S32K1XX_LPUART2 + bool "LPUART2" + default n + select LPUART2_SERIALDRIVER + +config S32K1XX_LPSPI0 + bool "LPSPI0" + default n + select SPI + +config S32K1XX_LPSPI1 + bool "LPSPI1" + default n + select SPI + +endmenu # iMX Peripheral Selection + +endif # ARCH_CHIP_S32K1XX diff --git a/arch/arm/src/s32k1xx/Make.defs b/arch/arm/src/s32k1xx/Make.defs new file mode 100644 index 0000000000..63855bcd99 --- /dev/null +++ b/arch/arm/src/s32k1xx/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# arch/arm/src/s32k1xx/Make.defs +# +# Copyright (C) 2019 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Common ARM source files + +HEAD_ASRC = +CMN_ASRCS = up_allocateheap.c up_exit.c up_initialize.c up_interruptcontext.c +CMN_ASRCS += up_lowputs.c up_mdelay.c up_modifyreg8.c up_modifyreg16.c +CMN_CSRCS += up_modifyreg32.c up_puts.c up_releasestack.c up_stackframe.c +CMN_CSRCS += up_task_start.c up_udelay.c up_usestack.c up_vfork.c + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_pthread_start.c +endif + +# Source files common to all S32K1xx chip families. + +CHIP_ASRCS = +CHIP_CSRCS = s32k1xx_start.c + +# Source files specific to the ARM CPU family and to the S32K1xx chip family + +ifeq ($(CONFIG_ARCH_CHIP_S32K11X),y) +include s32k1xx$(DELIM)s32k11x$(DELIM)Make.defs +else +include s32k1xx$(DELIM)s32k14x$(DELIM)Make.defs +endif + +# Make sure that the S32K1 common directory in included in the VPATH + +VPATH += chip/common diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h new file mode 100644 index 0000000000..c3d1735a08 --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h @@ -0,0 +1,114 @@ +/************************************************************************************ + * arch/arm/src/s32k1xx/chip/s32k1xx_cmu.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/* CMU Register Offsets *************************************************************/ + +#define S32K1XX_CMU_GCR_OFFSET 0x0000 /* Global Configuration Register */ +#define S32K1XX_CMU_RCCR_OFFSET 0x0004 /* Reference Count Configuration Register */ +#define S32K1XX_CMU_HTCR_OFFSET 0x0008 /* High Threshold Configuration Register */ +#define S32K1XX_CMU_LTCR_OFFSET 0x000c /* Low Threshold Configuration Register */ +#define S32K1XX_CMU_SR_OFFSET 0x0010 /* Status Register */ +#define S32K1XX_CMU_IER_OFFSET 0x0014 /* Interrupt Enable Register */ + +/* CMU Register Addresses ***********************************************************/ + +#define S32K1XX_CMU_GCR (S32K1XX_CMU_BASE + S32K1XX_CMU_GCR_OFFSET) +#define S32K1XX_CMU_RCCR (S32K1XX_CMU_BASE + S32K1XX_CMU_RCCR_OFFSET) +#define S32K1XX_CMU_HTCR (S32K1XX_CMU_BASE + S32K1XX_CMU_HTCR_OFFSET) +#define S32K1XX_CMU_LTCR (S32K1XX_CMU_BASE + S32K1XX_CMU_LTCR_OFFSET) +#define S32K1XX_CMU_SR (S32K1XX_CMU_BASE + S32K1XX_CMU_SR_OFFSET) +#define S32K1XX_CMU_IER (S32K1XX_CMU_BASE + S32K1XX_CMU_IER_OFFSET) + +/* CMU Register Bitfield Definitions ************************************************/ + +/* Global Configuration Register */ + +#define CMU_GCR_FCE (1 << 0) /* Bit 0: Frequency Check Enable */ + +/* Reference Count Configuration Register */ + +#define CMU_RCCR_REFCNT_SHIFT (0) /* Bits 0-15: Reference clock count */ +#define CMU_RCCR_REFCNT_MASK (0xffff << CMU_RCCR_REFCNT_SHIFT) +# define CMU_RCCR_REFCNT(n) ((uint32_t)(n) << CMU_RCCR_REFCNT_SHIFT) + +/* High Threshold Configuration Register */ + +#define CMU_HTCR_HFREF_SHIFT (0) /* Bits 0-23: High frequency reference threshold */ +#define CMU_HTCR_HFREF_MASK (0xffffff << CMU_HTCR_HFREF_SHIFT) +# define CMU_HTCR_HFREF(n) ((uint32_t)(n) << CMU_HTCR_HFREF_SHIFT) + +/* Low Threshold Configuration Register */ + +#define CMU_LTCR_LFREF_SHIFT (0) /* Bits 0-23: Low Frequency Reference Threshold. */ +#define CMU_LTCR_LFREF_MASK (0xffffff << CMU_LTCR_LFREF_SHIFT) +# define CMU_LTCR_LFREF(n) ((uint32_t)(n) << CMU_LTCR_LFREF_SHIFT) + +/* Status Register */ + +#define CMU_SR_FLL (1 << 0) /* Bit 0: Frequency < low frequency reference threshold */ +#define CMU_SR_FHH (1 << 1) /* Bit 1: Frequency > high frequency reference threshold */ +#define CMU_SR_STATE_SHIFT (2) /* Bits 2-3: Module state */ +#define CMU_SR_STATE_MASK (3 << CMU_SR_STATE_SHIFT) +# define CMU_SR_STATE_INIT (1 << CMU_SR_STATE_SHIFT) /* Initialization state */ +# define CMU_SR_STATE_INITWAIT (2 << CMU_SR_STATE_SHIFT) /* Initialization wait state */ +# define CMU_SR_STATE_FREQCHECK (3 << CMU_SR_STATE_SHIFT) /* Frequency check state */ +#define CMU_SR_RS (1 << 4) /* Bit 4: Run Status */ + +/* Interrupt Enable Register */ + +#define CMU_IER_FLLIE (1 << 0) /* Bit 0: Frequency < low frequency reference threshold, + * synchronous */ +#define CMU_IER_FHHIE (1 << 1) /* Bit 1: Frequency > high frequency reference threshold, + * synchronous */ +#define CMU_IER_FLLAIE (1 << 2) /* Bit 2: Frequency < low frequency reference threshold, + * asynchronous */ +#define CMU_IER_FHHAIE (1 << 3) /* Bit 3: Frequency > high frequency reference threshold, + * asynchronous */ + +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h new file mode 100644 index 0000000000..ce2a0bc3c6 --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h @@ -0,0 +1,271 @@ +/************************************************************************************ + * arch/arm/src/s32k1xx/chip/s32k1xx_mcm.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#ifdef CONFIG_ARCH_CHIP_S32K14X + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/* CMU Register Offsets *************************************************************/ + +#define S32K1XX_MCM_PLASC_BASE 0x0008 /* Crossbar Switch (AXBS) Slave Configuration */ +#define S32K1XX_MCM_PLAMC_BASE 0x000a /* Crossbar Switch (AXBS) Master Configuration */ +#define S32K1XX_MCM_CPCR_BASE 0x000c /* Core Platform Control Register */ +#define S32K1XX_MCM_ISCR_BASE 0x0010 /* Interrupt Status and Control Register */ +#define S32K1XX_MCM_PID_BASE 0x0030 /* Process ID Register */ +#define S32K1XX_MCM_CPO_BASE 0x0040 /* Compute Operation Control Register */ +#define S32K1XX_MCM_LMDR0_BASE 0x0400 /* Local Memory Descriptor Register 0 */ +#define S32K1XX_MCM_LMDR1_BASE 0x0404 /* Local Memory Descriptor Register 1 */ +#define S32K1XX_MCM_LMDR2_BASE 0x0408 /* Local Memory Descriptor Register 2 */ +#define S32K1XX_MCM_LMPECR_BASE 0x0480 /* LMEM Parity and ECC Control Register */ +#define S32K1XX_MCM_LMPEIR_BASE 0x0488 /* LMEM Parity and ECC Interrupt Register */ +#define S32K1XX_MCM_LMFAR_BASE 0x0490 /* LMEM Fault Address Register */ +#define S32K1XX_MCM_LMFATR_BASE 0x0494 /* LMEM Fault Attribute Register */ +#define S32K1XX_MCM_LMFDHR_BASE 0x04a0 /* LMEM Fault Data High Register */ +#define S32K1XX_MCM_LMFDLR_BASE 0x04a4 /* LMEM Fault Data Low Register */ + +/* CMU Register Addresses ***********************************************************/ + +#define S32K1XX_MCM_PLASC (S32K1XX_MCM_BASE + S32K1XX_MCM_PLASC_BASE) +#define S32K1XX_MCM_PLAMC (S32K1XX_MCM_BASE + S32K1XX_MCM_PLAMC_BASE) +#define S32K1XX_MCM_CPCR (S32K1XX_MCM_BASE + S32K1XX_MCM_CPCR_BASE) +#define S32K1XX_MCM_ISCR (S32K1XX_MCM_BASE + S32K1XX_MCM_ISCR_BASE) +#define S32K1XX_MCM_PID (S32K1XX_MCM_BASE + S32K1XX_MCM_PID_BASE) +#define S32K1XX_MCM_CPO (S32K1XX_MCM_BASE + S32K1XX_MCM_CPO_BASE) +#define S32K1XX_MCM_LMDR0 (S32K1XX_MCM_BASE + S32K1XX_MCM_LMDR0_BASE) +#define S32K1XX_MCM_LMDR1 (S32K1XX_MCM_BASE + S32K1XX_MCM_LMDR1_BASE) +#define S32K1XX_MCM_LMDR2 (S32K1XX_MCM_BASE + S32K1XX_MCM_LMDR2_BASE) +#define S32K1XX_MCM_LMPECR (S32K1XX_MCM_BASE + S32K1XX_MCM_LMPECR_BASE) +#define S32K1XX_MCM_LMPEIR (S32K1XX_MCM_BASE + S32K1XX_MCM_LMPEIR_BASE) +#define S32K1XX_MCM_LMFAR (S32K1XX_MCM_BASE + S32K1XX_MCM_LMFAR_BASE) +#define S32K1XX_MCM_LMFATR (S32K1XX_MCM_BASE + S32K1XX_MCM_LMFATR_BASE) +#define S32K1XX_MCM_LMFDHR (S32K1XX_MCM_BASE + S32K1XX_MCM_LMFDHR_BASE) +#define S32K1XX_MCM_LMFDLR (S32K1XX_MCM_BASE + S32K1XX_MCM_LMFDLR_BASE) + +/* CMU Register Bitfield Definitions ************************************************/ + +/* Crossbar Switch (AXBS) Slave Configuration (16-bit) */ + +#define MCM_PLASC_ASC(n) (1 << (n)) /* Bus slave connection to AXBS port n present */ + +/* Crossbar Switch (AXBS) Master Configuration */ + +#define MCM_PLAMC_AMC(n) (1 << (n)) /* Bus master connection to AXBS port n present */ + +/* Core Platform Control Register */ + +#define MCM_CPCR_HLT_FSM_ST_SHIFT (0) /* Bits 0-1: AXBS Halt State Machine Status */ +#define MCM_CPCR_HLT_FSM_ST_MASK (3 << MCM_CPCR_HLT_FSM_ST_SHIFT) +# define MCM_CPCR_HLT_FSM_WTREQ (0 << MCM_CPCR_HLT_FSM_ST_SHIFT) /* Waiting for request */ +# define MCM_CPCR_HLT_FSM_WTIDLE (1 << MCM_CPCR_HLT_FSM_ST_SHIFT) /* Waiting for platform idle */ +# define MCM_CPCR_HLT_FSM_STALLED (2 << MCM_CPCR_HLT_FSM_ST_SHIFT) /* Platform stalled */ +#define MCM_CPCR_AXBS_HLT_REQ (1 << 2) /* Bit 2: AXBS Halt Request */ +#define MCM_CPCR_AXBS_HLTD (1 << 3) /* Bit 3: AXBS Halted */ +#define MCM_CPCR_FMC_PF_IDLE (1 << 4) /* Bit 4: Flash Memory Controller Program Flash Idle */ +#define MCM_CPCR_PBRIDGE_IDLE (1 << 6) /* Bit 6: Peripheral Bridge Idle */ +#define MCM_CPCR_CBRR (1 << 9) /* Bit 8: Crossbar Round-robin Arbitration Enable */ +#define MCM_CPCR_SRAMUAP_SHIFT (24) /* Bits 24-25: SRAM_U Arbitration Priority */ +#define MCM_CPCR_SRAMUAP_MASK (3 << MCM_CPCR_SRAMUAP_SHIFT) +# define MCM_CPCR_SRAMUAP_RR (0 << MCM_CPCR_SRAMUAP_SHIFT) /* Round robin */ +# define MCM_CPCR_SRAMUAP_SRR (1 << MCM_CPCR_SRAMUAP_SHIFT) /* Special round robin (favors SRAM backdoor) */# define MCM_CPCR_SRAMUAP_FIXEDP (2 << MCM_CPCR_SRAMUAP_SHIFT) /* Fixed priority. Processor has highest */ +# define MCM_CPCR_SRAMUAP_FIXEDB (3 << MCM_CPCR_SRAMUAP_SHIFT) /* Fixed priority. Backdoor has highest */ +#define MCM_CPCR_SRAMUWP (1 << 26) /* Bit 26: SRAM_U Write Protect */ +#define MCM_CPCR_SRAMLAP_SHIFT (28) /* Bits 28-29: SRAM_L Arbitration Priority */ +#define MCM_CPCR_SRAMLAP_MASK (3 << MCM_CPCR_SRAMLAP_SHIFT) +# define MCM_CPCR_SRAMLAP_RR (0 << MCM_CPCR_SRAMLAP_SHIFT) /* Round robin */ +# define MCM_CPCR_SRAMLAP_SRR (1 << MCM_CPCR_SRAMLAP_SHIFT) /* Special round robin (favors SRAM backdoor) */# define MCM_CPCR_SRAMLAP_FIXEDP (2 << MCM_CPCR_SRAMLAP_SHIFT) /* Fixed priority. Processor has highest */ +# define MCM_CPCR_SRAMLAP_FIXEDB (3 << MCM_CPCR_SRAMLAP_SHIFT) /* Fixed priority. Backdoor has highest */ +#define MCM_CPCR_SRAMLWP (1 << 30) /* Bit 30: SRAM_L Write Protect */ + +/* Interrupt Status and Control Register */ + +#define MCM_ISCR_IOC (1 << 8) /* Bit 8: FPU Invalid Operation Interrupt Status */ +#define MCM_ISCR_FDZC (1 << 9) /* Bit 9: FPU Divide-by-Zero Interrupt Status */ +#define MCM_ISCR_FOFC (1 << 10) /* Bit 10: FPU Overflow Interrupt Status */ +#define MCM_ISCR_FUFC (1 << 11) /* Bit 11: FPU Underflow Interrupt Status */ +#define MCM_ISCR_FIXC (1 << 12) /* Bit 12: FPU Inexact Interrupt Status */ +#define MCM_ISCR_FIDC (1 << 15) /* Bit 15: FPU Input Denormal Interrupt Status */ +#define MCM_ISCR_FIOCE (1 << 24) /* Bit 24: FPU Invalid Operation Interrupt Enable */ +#define MCM_ISCR_FDZCE (1 << 25) /* Bit 25: FPU Divide-by-Zero Interrupt Enable */ +#define MCM_ISCR_FOFCE (1 << 26) /* Bit 26: FPU Overflow Interrupt Enable */ +#define MCM_ISCR_FUFCE (1 << 27) /* Bit 27: FPU Underflow Interrupt Enable */ +#define MCM_ISCR_FIXCE (1 << 28) /* Bit 28: FPU Inexact Interrupt Enable */ +#define MCM_ISCR_FIDCE (1 << 31) /* Bit 31: FPU Input Denormal Interrupt Enable */ + +/* Process ID Register */ + +#define MCM_PID_SHIFT (0) /* Bits 0-7: M0_PID and M1_PID for MPU */ +#define MCM_PID_MASK (0xff << MCM_PID_SHIFT) +# define MCM_PID(n) ((uint32_t)(n) << MCM_PID_SHIFT) + +/* Compute Operation Control Register */ + +#define MCM_CPO_CPOREQ (1 << 0) /* Bit 0: Compute Operation Request */ +#define MCM_CPO_CPOACK (1 << 1) /* Bit 1: Compute Operation Acknowledge */ +#define MCM_CPO_CPOWOI (1 << 2) /* Bit 2: Compute Operation Wakeup On Interrupt */ + +/* Local Memory Descriptor Registers */ + +#define MCM_LMDR_CF0_SHIFT (0) /* Bits 0-3: Control Field 0 (LMDR0 and LMDR1) */ +#define MCM_LMDR_CF0_MASK (15 << MCM_LMDR_CF0_SHIFT) +# define MCM_LMDR_CF0_EEWG (0 << MCM_LMDR_CF0_SHIFT) /* CF0[0]: ECC Enable Write Generation */ +# define MCM_LMDR_CF0_EERC (1 << MCM_LMDR_CF0_SHIFT) /* CF0[1]: ECC Enable Read Check */ +#define MCM_LMDR2_CF1_SHIFT (4) /* Bits 4-7: Control Field 1 (LMDR2) */ +#define MCM_LMDR2_CF1_MASK (15 << MCM_LMDR2_CF1_SHIFT) +# define MCM_LMDR2_CF1_PCPME (2 << MCM_LMDR2_CF1_SHIFT) /* CF1[1]: PC Parity Miss Enable */ +# define MCM_LMDR2_CF1_PCPFE (8 << MCM_LMDR2_CF1_SHIFT) /* CF1[3]: PC Parity Fault Enable */ +#define MCM_LMDR_MT_SHIFT (13) /* Bits 13-15: Memory Type */ +#define MCM_LMDR_MT_MASK (7 << MCM_LMDR_MT_SHIFT) +# define MCM_LMDR_MT_SRAML (0 << MCM_LMDR_MT_SHIFT) /* SRAM_L (LMDR0 and LMDR1) */ +# define MCM_LMDR_MT_SRAMU (1 << MCM_LMDR_MT_SHIFT) /* SRAM_U (LMDR0 and LMDR1) */ +# define MCM_LMDR2_MT_PCCACHE (2 << MCM_LMDR_MT_SHIFT) /* PC Cache (LMDR2) */ +#define MCM_LMDR_LOCK (1 << 16) /* Bit 16: Lock */ +#define MCM_LMDR_DPW_SHIFT (17) /* Bits 17-19: LMEM Data Path Width */ +#define MCM_LMDR_DPW_MASK (7 << MCM_LMDR_DPW_SHIFT) +# define MCM_LMDR_DPW_ 2BITS (2 << MCM_LMDR_DPW_SHIFT) /* LMEMn 32-bits wide */ +# define MCM_LMDR_DPW_64BITS (3 << MCM_LMDR_DPW_SHIFT) /* LMEMn 64-bits wide */ +#define MCM_LMDR_WY_SHIFT (20) /* Bits 20-23: Level 1 Cache Ways */ +#define MCM_LMDR_WY_MASK (15 << MCM_LMDR_WY_SHIFT) +# define MCM_LMDR_WY_NOCACHE (0 << MCM_LMDR_WY_SHIFT) /* No Cache */ +# define MCM_LMDR_WY_2WAY (2 << MCM_LMDR_WY_SHIFT) /* 2-Way Set Associative */ +# define MCM_LMDR_WY_4WAY (4 << MCM_LMDR_WY_SHIFT) /* 4-Way Set Associative */ +#define MCM_LMDR_LMSZ_SHIFT (24) /* Bits 24-27: LMEM Size */ +#define MCM_LMDR_LMSZ_MASK (15 << MCM_LMDR_LMSZ_SHIFT) +# define MCM_LMDR_LMSZ_ MASK (0 << MCM_LMDR_LMSZ_SHIFT) /* No LMEMn (0 KB) */ +# define MCM_LMDR_LMSZ_ MASK (1 << MCM_LMDR_LMSZ_SHIFT) /* 1 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (2 << MCM_LMDR_LMSZ_SHIFT) /* 2 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (3 << MCM_LMDR_LMSZ_SHIFT) /* 4 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (4 << MCM_LMDR_LMSZ_SHIFT) /* 8 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (5 << MCM_LMDR_LMSZ_SHIFT) /* 16 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (6 << MCM_LMDR_LMSZ_SHIFT) /* 32 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (7 << MCM_LMDR_LMSZ_SHIFT) /* 64 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (8 << MCM_LMDR_LMSZ_SHIFT) /* 128 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (9 << MCM_LMDR_LMSZ_SHIFT) /* 256 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (10 << MCM_LMDR_LMSZ_SHIFT) /* 512 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (11 << MCM_LMDR_LMSZ_SHIFT) /* 1024 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (12 << MCM_LMDR_LMSZ_SHIFT) /* 2048 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (13 << MCM_LMDR_LMSZ_SHIFT) /* 4096 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (14 << MCM_LMDR_LMSZ_SHIFT) /* 8192 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR_LMSZ_ MASK (15 << MCM_LMDR_LMSZ_SHIFT) /* 16384 KB LMEMn (LMDR0, LMDR1) */ +# define MCM_LMDR2_LMSZ_ MASK (4 << MCM_LMDR_LMSZ_SHIFT) /* 4 KB LMEMn (LMDR2) */ +#define MCM_LMDR_LMSZH (1 << 28) /* Bit 28: LMEM Size Hole */ +#define MCM_LMDR_V (1 << 31) /* Bit 31: Local Memory Valid */ + +/* LMEM Parity and ECC Control Register */ + +#define MCM_LMPECR_ERNCR (1 << 0) /* Bit 0: Enable RAM ECC Noncorrectable Reporting */ +#define MCM_LMPECR_ER1BR (1 << 8) /* Bit 8: Enable RAM ECC 1 Bit Reporting */ +#define MCM_LMPECR_ECPR (1 << 20) /* Bit 20: Enable Cache Parity Reporting */ + +/* LMEM Parity and ECC Interrupt Register */ + +#define MCM_LMPEIR_ENC_SHIFT (0) /* Bits 0-7: ENCn = ECC Noncorrectable Error n */ +#define MCM_LMPEIR_ENC_MASK (0xff << MCM_LMPEIR_ENC_SHIFT) +# define MCM_LMPEIR_ENC_SRAML (1 << 0) /* PEIR[0]: Noncorrectable SRAM_L Error detected */ +# define MCM_LMPEIR_ENC_SRAMU (2 << 1) /* PEIR[1]: Noncorrectable SRAM_U Error detected */ +#define MCM_LMPEIR_E1B_SHIFT (8) /* Bits 8-15: E1Bn = ECC 1-bit Error n */ +#define MCM_LMPEIR_E1B_MASK (0xff << MCM_LMPEIR_E1B_SHIFT) +# define MCM_LMPEIR_E1B_SRAML (1 << 8) /* PEIR[8]: 1-bit Error detected on SRAM_L */ +# define MCM_LMPEIR_E1B_SRAMU (2 << 9) /* PEIR[9]: 1-bit Error detected on SRAM_U */ +#define MCM_LMPEIR_PE_SHIFT (16) /* Bits 16-23: Cache Parity Error */ +#define MCM_LMPEIR_PE_MASK (0xff << MCM_LMPEIR_PE_SHIFT) +# define MCM_LMPEIR_PE_TAG (1 << 20) /* PE[20]: PC Tag Parity Error */ +# define MCM_LMPEIR_PE_DATA (1 << 21) /* PE[21]: PC Data Parity Error */ +#define MCM_LMPEIR_PEELOC_SHIFT (24) /* Bits 24-28: Parity or ECC Error Location */ +#define MCM_LMPEIR_PEELOC_MASK (0x1f << MCM_LMPEIR_PEELOC_SHIFT) +# define MCM_LMPEIR_PEELOC_NCSRAML (0 << MCM_LMPEIR_PEELOC_SHIFT) /* Non-correctable ECC event from SRAM_L */ +# define MCM_LMPEIR_PEELOC_NCSRAMU (1 << MCM_LMPEIR_PEELOC_SHIFT) /* Non-correctable ECC event from SRAM_U */ +# define MCM_LMPEIR_PEELOC_CSRAML (8 << MCM_LMPEIR_PEELOC_SHIFT) /* 1-bit correctable ECC event from SRAM_L */ +# define MCM_LMPEIR_PEELOC_CSRAMU (9 << MCM_LMPEIR_PEELOC_SHIFT) /* 1-bit correctable ECC event from SRAM_U */ +# define MCM_LMPEIR_PEELOC_PCTAG (14 << MCM_LMPEIR_PEELOC_SHIFT) /* PC tag parity error */ +# define MCM_LMPEIR_PEELOC_PCDATA (15 << MCM_LMPEIR_PEELOC_SHIFT) /* PC data parity error */ +#define MCM_LMPEIR_V (1 << 31) /* Bit 31: Valid Bit */ + +/* LMEM Fault Address Register */ + +#define MCM_LMFAR_PEFPRT_SHIFT (0) /* Bits 0-3: Parity/ECC Fault Protection */ +#define MCM_LMFAR_PEFPRT_MASK (15 << MCM_LMFAR_PEFPRT_SHIFT) +# define MCM_LMFAR_PEFPRT_DATA (1 << MCM_LMFAR_PEFPRT_SHIFT) /* FATR[0]: Type: 0=I-Fetch, 1=Data */ +# define MCM_LMFAR_PEFPRT_SUPERVISOR (2 << MCM_LMFAR_PEFPRT_SHIFT) /* FATR[1]: Mode: 0=User mode, 1=Supervisor mode */ +# define MCM_LMFAR_PEFPRT_BUFFERABLE (4 << MCM_LMFAR_PEFPRT_SHIFT) /* FATR[2]: Bufferable: 0=Non-bufferable, 1=Bufferable */ +# define MCM_LMFAR_PEFPRT_CACHEABLE (8 << MCM_LMFAR_PEFPRT_SHIFT) /* FATR[3]: Cacheable: 0=Non-cacheable, 1=Cacheable */ +#define MCM_LMFAR_PEFSIZE_SHIFT (4) /* Bits 4-6: Parity/ECC Fault Master Size */ +#define MCM_LMFAR_PEFSIZE_MASK (7 << MCM_LMFAR_PEFSIZE_SHIFT) +# define MCM_LMFAR_PEFSIZE_8BIT (0 << MCM_LMFAR_PEFSIZE_SHIFT) /* 8-bit access */ +# define MCM_LMFAR_PEFSIZE_16BIT (1 << MCM_LMFAR_PEFSIZE_SHIFT) /* 16-bit access */ +# define MCM_LMFAR_PEFSIZE_32BIT (2 << MCM_LMFAR_PEFSIZE_SHIFT) /* 32-bit access */ +# define MCM_LMFAR_PEFSIZE_64BIT (3 << MCM_LMFAR_PEFSIZE_SHIFT) /* 64-bit access */ +#define MCM_LMFAR_PEFW (1 << 7) /* Bit 7: Parity/ECC Fault Write */ +#define MCM_LMFAR_PEFMST_SHIFT (8) /* Bits 8-15: Parity/ECC Fault Master Number */ +#define MCM_LMFAR_PEFMST_MASK (0xff << MCM_LMFAR_PEFMST_SHIFT) +# define MCM_LMFAR_PEFMST(n) ((uint32_t)(n) << MCM_LMFAR_PEFMST_SHIFT) +#define MCM_LMFAR_OVR (1 << 31) /* Bit 31: Overrun */ + +/* LMEM Fault Attribute Register */ + +#define MCM_LMFATR_PEFPRT_SHIFT (0) /* Bits 0-3: Parity/ECC Fault Protection */ +#define MCM_LMFATR_PEFPRT_MASK (15 << MCM_LMFATR_PEFPRT_SHIFT) +# define MCM_LMFATR_PEFPRT_DATA (1 << MCM_LMFATR_PEFPRT_SHIFT) /* FATR[0]: Type: 0=I-Fetch, 1=Data */ +# define MCM_LMFATR_PEFPRT_SUPERVISOR (2 << MCM_LMFATR_PEFPRT_SHIFT) /* FATR[1]: Mode: 0=User mode, 1=Supervisor mode */ +# define MCM_LMFATR_PEFPRT_BUFFERABLE (4 << MCM_LMFATR_PEFPRT_SHIFT) /* FATR[2]: Bufferable: 0=Non-bufferable, 1=Bufferable */ +# define MCM_LMFATR_PEFPRT_CACHEABLE (8 << MCM_LMFATR_PEFPRT_SHIFT) /* FATR[3]: Cacheable: 0=Non-cacheable, 1=Cacheable */ +#define MCM_LMFATR_PEFSIZE_SHIFT (4) /* Bits 4-6: Parity/ECC Fault Master Size */ +#define MCM_LMFATR_PEFSIZE_MASK (7 << MCM_LMFATR_PEFSIZE_SHIFT) +# define MCM_LMFATR_PEFSIZE_8BIT (0 << MCM_LMFATR_PEFSIZE_SHIFT) /* 8-bit access */ +# define MCM_LMFATR_PEFSIZE_16BIT (1 << MCM_LMFATR_PEFSIZE_SHIFT) /* 16-bit access */ +# define MCM_LMFATR_PEFSIZE_32BIT (2 << MCM_LMFATR_PEFSIZE_SHIFT) /* 32-bit access */ +# define MCM_LMFATR_PEFSIZE_64BIT (3 << MCM_LMFATR_PEFSIZE_SHIFT) /* 64-bit access */ +#define MCM_LMFATR_PEFW (1 << 7) /* Bit 7: Parity/ECC Fault Write */ +#define MCM_LMFATR_PEFMST_SHIFT (8) /* Bits 8-15: Parity/ECC Fault Master Number */ +#define MCM_LMFATR_PEFMST_MASK (0xff << MCM_LMFATR_PEFMST_SHIFT) +# define MCM_LMFATR_PEFMST(n) ((uint32_t)(n) << MCM_LMFATR_PEFMST_SHIFT) +#define MCM_LMFATR_OVR (1 << 31) /* Bit 31: Overrun */ + +/* LMEM Fault Data High Register (32-bit address data) */ +/* LMEM Fault Data Low Register (32-bit address data) */ + +#endif /* CONFIG_ARCH_CHIP_S32K14X */ +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h new file mode 100644 index 0000000000..408f4d8608 --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h @@ -0,0 +1,125 @@ +/************************************************************************************ + * arch/arm/src/s32k1xx/chip/s32k1xx_memorymap.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MEMORYMAP_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#define S32K1XX_AIPS_LITE_BASE 0x40000000 /* Peripheral bridge (AIPS-Lite) */ +# define S32K1XX_MSCM_BASE 0x40001000 /* MSCM */ +# define S32K1XX_DMAC_BASE 0x40008000 /* DMA controller */ +# define S32K1XX_DMADESC_BASE 0x40008000 /* DMA transfer control descriptors */ +# define S32K1XX_MPU_BASE 0x4000d000 /* MPU */ +# define S32K1XX_GPIOC_BASE 0x4000f000 /* GPIO controller */ +# define S32K1XX_GPIOALIAS_BASE 0x400ff000 /* GPIO controller (alias) */ +# define S32K1XX_ERM_BASE 0x40018000 /* ERM */ +# define S32K1XX_EIM_BASE 0x40019000 /* EIM */ +#define S32K1XX_FTFC_BASE 0x40020000 /* Flash memory */ +#define S32K1XX_DMAMUX_BASE 0x40021000 /* DMA Channel Multiplexer */ +#define S32K1XX_FLEXCAN0_BASE 0x40024000 /* FlexCAN 0 */ +#define S32K1XX_FLEXCAN1_BASE 0x40025000 /* FlexCAN 1 */ +#define S32K1XX_FLEXTIMER_BASE 0x40026000 /* FlexTimer */ +#define S32K1XX_ADC1_BASE 0x40027000 /* Analog-to-digital converter 1 */ +#define S32K1XX_FLEXCAN2_BASE 0x4002b000 /* FlexCAN 2 */ +#define S32K1XX_LPSPI0_BASE 0x4002c000 /* Low Power SPI 0 */ +#define S32K1XX_LPSPI1_BASE 0x4002d000 /* Low Power SPI 1 */ +#define S32K1XX_LPSPI2_BASE 0x4002e000 /* Low Power SPI 2 */ +#define S32K1XX_PDB1_BASE 0x40031000 /* Programmable delay block 1 */ +#define S32K1XX_CRC_BASE 0x40032000 /* CRC */ +#define S32K1XX_LPIT0_BASE 0x40037000 /* Low power periodic interrupt timer */ +#define S32K1XX_FTM0_BASE 0x40038000 /* FlexTimer 0 */ +#define S32K1XX_FTM1_BASE 0x40039000 /* FlexTimer 1 */ +#define S32K1XX_FTM2_BASE 0x4003a000 /* FlexTimer 2 */ +#define S32K1XX_ADC0_BASE 0x4003b000 /* Analog-to-digital converter 0 */ +#define S32K1XX_RTC_BASE 0x4003d000 /* Real-time counter */ +#define S32K1XX_CMU0_BASE 0x4003e000 /* Clock Monitor Unit 0 */ +#define S32K1XX_CMU1_BASE 0x4003f000 /* Clock Monitor Unit 1 */ +#define S32K1XX_LPTMR0_BASE 0x40040000 /* Low-power timer 0 */ +#define S32K1XX_SIM_BASE 0x40048000 /* System integration module */ +#define S32K1XX_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +#define S32K1XX_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +#define S32K1XX_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +#define S32K1XX_PORTE_BASE 0x4004c000 /* Port D multiplexing control */ +#define S32K1XX_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +#define S32K1XX_WDOG_BASE 0x40052000 /* Software watchdog */ +#define S32K1XX_SAI0_BASE 0x40054000 /* Synchronous Audio Interface 0 */ +#define S32K1XX_SAI1_BASE 0x40055000 /* Synchronous Audio Interface 1 */ +#define S32K1XX_FLEXIO_BASE 0x4005a000 /* Flexible IO */ +#define S32K1XX_EWM_BASE 0x40061000 /* External watchdog */ +#define S32K1XX_TRGMUX_BASE 0x40063000 /* Trigger Multiplexing Control */ +#define S32K1XX_SCG_BASE 0x40064000 /* System Clock Generator */ +#define S32K1XX_PCC_BASE 0x40065000 /* Peripheral Clock Control */ +#define S32K1XX_LPI2C0_BASE 0x40066000 /* Low Power I2C 0 */ +#define S32K1XX_LPI2C1_BASE 0x40067000 /* Low Power I2C 1 */ +#define S32K1XX_LPUART0_BASE 0x4006a000 /* Low Power UART 0 */ +#define S32K1XX_LPUART1_BASE 0x4006b000 /* Low Power UART 1 */ +#define S32K1XX_LPUART2_BASE 0x4006c000 /* Low Power UART 2 */ +#define S32K1XX_FTM4_BASE 0x4006e000 /* FlexTimer 4 */ +#define S32K1XX_FTM5_BASE 0x4006f000 /* FlexTimer 5 */ +#define S32K1XX_FTM6_BASE 0x40070000 /* FlexTimer 6 */ +#define S32K1XX_FTM7_BASE 0x40071000 /* FlexTimer 7 */ +#define S32K1XX_CMP0_BASE 0x40073000 /* Analog comparator 0 */ +#define S32K1XX_QUADSPI_BASE 0x40076000 /* QuadSPI */ +#define S32K1XX_ENET_BASE 0x40079000 /* Ethernet */ +#define S32K1XX_PMC_BASE 0x4007d000 /* Power management controller */ +#define S32K1XX_SMC_BASE 0x4007e000 /* System Mode controller */ +#define S32K1XX_RCM_BASE 0x4007f000 /* Reset Control Module */ +#define S32K1XX_GPIO_BASE 0x400ff000 /* GPIO controller */ + +#if defined(CONFIG_ARCH_CHIP_S32K14X) +# define S32K1XX_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell */ +# define S32K1XX_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace */ +# define S32K1XX_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint */ +# define S32K1XX_SCS_BASE 0xe000e000 /* System Control Space */ +# define S32K1XX_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit */ +# define S32K1XX_MCM_BASE 0xe0080000 /* Miscellaneous Control Module */ +# define S32K1XX_LMEM_BASE 0xe0082000 /* Cache Controller */ +# define S32K1XX_ROMTABLE1_BASE 0xe00ff000 /* Arm Core ROM Table */ +#elif defined(CONFIG_ARCH_CHIP_S32K11X) +# define S32K1XX_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace */ +# define S32K1XX_ROMTABLE_BASE 0xe0002000 /* Arm Core ROM Table */ +# define S32K1XX_SCS_BASE 0xe000e000 /* System Control Space */ +#endif + +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MEMORYMAP_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h new file mode 100644 index 0000000000..34ddf701e9 --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h @@ -0,0 +1,172 @@ +/************************************************************************************ + * arch/arm/src/s32k1xx/chip/s32k1xx_pcc.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PCC_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PCC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/* PCC Register Offsets *************************************************************/ + +#define S32K1XX_PCC_FTFC_OFFSET 0x0080 /* PCC FTFC Register */ +#define S32K1XX_PCC_DMAMUX_OFFSET 0x0084 /* PCC DMAMUX Register */ +#define S32K1XX_PCC_FLEXCAN0_OFFSET 0x0090 /* PCC FlexCAN0 Register */ +#define S32K1XX_PCC_FLEXCAN1_OFFSET 0x0094 /* PCC FlexCAN1 Register */ +#define S32K1XX_PCC_FTM3_OFFSET 0x0098 /* PCC FTM3 Register */ +#define S32K1XX_PCC_ADC1_OFFSET 0x009c /* PCC ADC1 Register */ +#define S32K1XX_PCC_FLEXCAN_OFFSET 0x00ac /* PCC FlexCAN2 Register */ +#define S32K1XX_PCC_LPSPI0_OFFSET 0x00b0 /* PCC LPSPI0 Register */ +#define S32K1XX_PCC_LPSPI1_OFFSET 0x00b4 /* PCC LPSPI1 Register */ +#define S32K1XX_PCC_LPSPI2_OFFSET 0x00b8 /* PCC LPSPI2 Register */ +#define S32K1XX_PCC_PDB1_OFFSET 0x00c4 /* PCC PDB1 Register */ +#define S32K1XX_PCC_CRC_OFFSET 0x00c8 /* PCC CRC Register */ +#define S32K1XX_PCC_PDB0_OFFSET 0x00d8 /* PCC PDB0 Register */ +#define S32K1XX_PCC_LPIT_OFFSET 0x00dc /* PCC LPIT Register */ +#define S32K1XX_PCC_FTM0_OFFSET 0x00e0 /* PCC FTM0 Register */ +#define S32K1XX_PCC_FTM1_OFFSET 0x00e4 /* PCC FTM1 Register */ +#define S32K1XX_PCC_FTM2_OFFSET 0x00e8 /* PCC FTM2 Register */ +#define S32K1XX_PCC_ADC0_OFFSET 0x00ec /* PCC ADC0 Register */ +#define S32K1XX_PCC_RTC_OFFSET 0x00f4 /* PCC RTC Register */ +#define S32K1XX_PCC_CMU0_OFFSET 0x00f8 /* PCC CMU0 Register */ +#define S32K1XX_PCC_CMU1_OFFSET 0x00fc /* PCC CMU1 Register */ +#define S32K1XX_PCC_LPTMR0_OFFSET 0x0100 /* PCC LPTMR0 Register */ +#define S32K1XX_PCC_PORTA_OFFSET 0x0124 /* PCC PORTA Register */ +#define S32K1XX_PCC_PORTB_OFFSET 0x0128 /* PCC PORTB Register */ +#define S32K1XX_PCC_PORTC_OFFSET 0x012c /* PCC PORTC Register */ +#define S32K1XX_PCC_PORTD_OFFSET 0x0130 /* PCC PORTD Register */ +#define S32K1XX_PCC_PORTE_OFFSET 0x0134 /* PCC PORTE Register */ +#define S32K1XX_PCC_SAI0_OFFSET 0x0150 /* PCC SAI0 Register */ +#define S32K1XX_PCC_SAI1_OFFSET 0x0154 /* PCC SAI1 Register */ +#define S32K1XX_PCC_FLEXIO_OFFSET 0x0168 /* PCC FlexIO Register */ +#define S32K1XX_PCC_EWM_OFFSET 0x0184 /* PCC EWM Register */ +#define S32K1XX_PCC_LPI2C0_OFFSET 0x0198 /* PCC LPI2C0 Register */ +#define S32K1XX_PCC_LPI2C1_OFFSET 0x019c /* PCC LPI2C1 Register */ +#define S32K1XX_PCC_LPUART0_OFFSET 0x01a8 /* PCC LPUART0 Register */ +#define S32K1XX_PCC_LPUART1_OFFSET 0x01ac /* PCC LPUART1 Register */ +#define S32K1XX_PCC_LPUART2_OFFSET 0x01b0 /* PCC LPUART2 Register */ +#define S32K1XX_PCC_FTM4_OFFSET 0x01b8 /* PCC FTM4 Register */ +#define S32K1XX_PCC_FTM5_OFFSET 0x01bc /* PCC FTM5 Register */ +#define S32K1XX_PCC_FTM6_OFFSET 0x01c0 /* PCC FTM6 Register */ +#define S32K1XX_PCC_FTM7_OFFSET 0x01c4 /* PCC FTM7 Register */ +#define S32K1XX_PCC_CMP0_OFFSET 0x01cc /* PCC CMP0 Register */ +#define S32K1XX_PCC_QSPI_OFFSET 0x01d8 /* PCC QSPI Register */ +#define S32K1XX_PCC_ENET_OFFSET 0x01e4 /* PCC ENET Register */ + +/* PCC Register Addresses ***********************************************************/ + +#define S32K1XX_PCC_FTFC (S32K1XX_PCC_BASE + S32K1XX_PCC_FTFC_OFFSET) +#define S32K1XX_PCC_DMAMUX (S32K1XX_PCC_BASE + S32K1XX_PCC_DMAMUX_OFFSET) +#define S32K1XX_PCC_FLEXCAN0 (S32K1XX_PCC_BASE + S32K1XX_PCC_FLEXCAN0_OFFSET) +#define S32K1XX_PCC_FLEXCAN1 (S32K1XX_PCC_BASE + S32K1XX_PCC_FLEXCAN1_OFFSET) +#define S32K1XX_PCC_FTM3 (S32K1XX_PCC_BASE + S32K1XX_PCC_FTM3_OFFSET) +#define S32K1XX_PCC_ADC1 (S32K1XX_PCC_BASE + S32K1XX_PCC_ADC1_OFFSET) +#define S32K1XX_PCC_FLEXCAN (S32K1XX_PCC_BASE + S32K1XX_PCC_FLEXCAN_OFFSET) +#define S32K1XX_PCC_LPSPI0 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPSPI0_OFFSET) +#define S32K1XX_PCC_LPSPI1 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPSPI1_OFFSET) +#define S32K1XX_PCC_LPSPI2 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPSPI2_OFFSET) +#define S32K1XX_PCC_PDB1 (S32K1XX_PCC_BASE + S32K1XX_PCC_PDB1_OFFSET) +#define S32K1XX_PCC_CRC (S32K1XX_PCC_BASE + S32K1XX_PCC_CRC_OFFSET) +#define S32K1XX_PCC_PDB0 (S32K1XX_PCC_BASE + S32K1XX_PCC_PDB0_OFFSET) +#define S32K1XX_PCC_LPIT (S32K1XX_PCC_BASE + S32K1XX_PCC_LPIT_OFFSET) +#define S32K1XX_PCC_FTM0 (S32K1XX_PCC_BASE + S32K1XX_PCC_FTM0_OFFSET) +#define S32K1XX_PCC_FTM1 (S32K1XX_PCC_BASE + S32K1XX_PCC_FTM1_OFFSET) +#define S32K1XX_PCC_FTM2 (S32K1XX_PCC_BASE + S32K1XX_PCC_FTM2_OFFSET) +#define S32K1XX_PCC_ADC0 (S32K1XX_PCC_BASE + S32K1XX_PCC_ADC0_OFFSET) +#define S32K1XX_PCC_RTC (S32K1XX_PCC_BASE + S32K1XX_PCC_RTC_OFFSET) +#define S32K1XX_PCC_CMU0 (S32K1XX_PCC_BASE + S32K1XX_PCC_CMU0_OFFSET) +#define S32K1XX_PCC_CMU1 (S32K1XX_PCC_BASE + S32K1XX_PCC_CMU1_OFFSET) +#define S32K1XX_PCC_LPTMR0 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPTMR0_OFFSET) +#define S32K1XX_PCC_PORTA (S32K1XX_PCC_BASE + S32K1XX_PCC_PORTA_OFFSET) +#define S32K1XX_PCC_PORTB (S32K1XX_PCC_BASE + S32K1XX_PCC_PORTB_OFFSET) +#define S32K1XX_PCC_PORTC (S32K1XX_PCC_BASE + S32K1XX_PCC_PORTC_OFFSET) +#define S32K1XX_PCC_PORTD (S32K1XX_PCC_BASE + S32K1XX_PCC_PORTD_OFFSET) +#define S32K1XX_PCC_PORTE (S32K1XX_PCC_BASE + S32K1XX_PCC_PORTE_OFFSET) +#define S32K1XX_PCC_SAI0 (S32K1XX_PCC_BASE + S32K1XX_PCC_SAI0_OFFSET) +#define S32K1XX_PCC_SAI1 (S32K1XX_PCC_BASE + S32K1XX_PCC_SAI1_OFFSET) +#define S32K1XX_PCC_FLEXIO (S32K1XX_PCC_BASE + S32K1XX_PCC_FLEXIO_OFFSET) +#define S32K1XX_PCC_EWM (S32K1XX_PCC_BASE + S32K1XX_PCC_EWM_OFFSET) +#define S32K1XX_PCC_LPI2C0 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPI2C0_OFFSET) +#define S32K1XX_PCC_LPI2C1 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPI2C1_OFFSET) +#define S32K1XX_PCC_LPUART0 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPUART0_OFFSET) +#define S32K1XX_PCC_LPUART1 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPUART1_OFFSET) +#define S32K1XX_PCC_LPUART2 (S32K1XX_PCC_BASE + S32K1XX_PCC_LPUART2_OFFSET) +#define S32K1XX_PCC_FTM4 (S32K1XX_PCC_BASE + S32K1XX_PCC_FTM4_OFFSET) +#define S32K1XX_PCC_FTM5 (S32K1XX_PCC_BASE + S32K1XX_PCC_FTM5_OFFSET) +#define S32K1XX_PCC_FTM6 (S32K1XX_PCC_BASE + S32K1XX_PCC_FTM6_OFFSET) +#define S32K1XX_PCC_FTM7 (S32K1XX_PCC_BASE + S32K1XX_PCC_FTM7_OFFSET) +#define S32K1XX_PCC_CMP0 (S32K1XX_PCC_BASE + S32K1XX_PCC_CMP0_OFFSET) +#define S32K1XX_PCC_QSPI (S32K1XX_PCC_BASE + S32K1XX_PCC_QSPI_OFFSET) +#define S32K1XX_PCC_ENET (S32K1XX_PCC_BASE + S32K1XX_PCC_ENET_OFFSET) + +/* PCC Register Bitfield Definitions ************************************************/ + +/* The form of each PCC register is the same as follows. Some register, however, do + * not support all of the files: + * + * PCD - ENET + * FRAC - ENET + * PCS - FTM3, ADC0, ADC1, LPSPI0, LPSPI1, LPSPI2, LPIT, FTM0, FTM2, FTM4, FTM6, + * FTM7, LPTMR0, FLEXIO, LPI2C0, LPCI2C1, UART0, UART1, UART2, ENET + * CGC - All PCC registers + * PR - All PCC registers + */ + +#define PCC_PCD_SHIFT (0) /* Bits 0-2: Peripheral Clock Divider Select */ +#define PCC_PCD_MASK (7 << PCC_PCD_SHIFT) +# define PCC_PCD(n) ((uint32_t)((n) - 1) << PCC_PCD_SHIFT) /* n=1..8 */ +#define PCC_FRAC (1 << 3) /* Bits 3: Peripheral Clock Divider Fraction */ +#define PCC_PCS_SHIFT (24) /* Bits 24-26: Peripheral Clock Source Select */ +#define PCC_PCS_MASK (7 << PCC_PCS_SHIFT) +# define PCC_PCS_OFF (0 << PCC_PCS_SHIFT) /* Clock is off */ +# define PCC_PCS_OPTION1 (1 << PCC_PCS_SHIFT) /* Clock option 1 */ +# define PCC_PCS_OPTION2 (2 << PCC_PCS_SHIFT) /* Clock option 2 */ +# define PCC_PCS_OPTION3 (3 << PCC_PCS_SHIFT) /* Clock option 3 */ +# define PCC_PCS_OPTION4 (4 << PCC_PCS_SHIFT) /* Clock option 4 */ +# define PCC_PCS_OPTION5 (5 << PCC_PCS_SHIFT) /* Clock option 5 */ +# define PCC_PCS_OPTION6 (6 << PCC_PCS_SHIFT) /* Clock option 6 */ +# define PCC_PCS_OPTION7 (7 << PCC_PCS_SHIFT) /* Clock option 7 */ +#define PCC_CGC (1 << 30) /* Clock Gate Control */ +#define PCC_PR (1 << 31) /* Present */ + +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PCC_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h new file mode 100644 index 0000000000..765a73e9bc --- /dev/null +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h @@ -0,0 +1,344 @@ +/************************************************************************************ + * arch/arm/src/s32k1xx/chip/s32k1xx_scg.h + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SCG_H +#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SCG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/* SCG Register Offsets *************************************************************/ + +#define S32K1XX_SCG_VERID_OFFSET 0x0000 /* Version ID Register */ +#define S32K1XX_SCG_PARAM_OFFSET 0x0004 /* Parameter Register */ +#define S32K1XX_SCG_CSR_OFFSET 0x0010 /* Clock Status Register */ +#define S32K1XX_SCG_RCCR_OFFSET 0x0014 /* Run Clock Control Register */ +#define S32K1XX_SCG_VCCR_OFFSET 0x0018 /* VLPR Clock Control Register */ +#define S32K1XX_SCG_HCCR_OFFSET 0x001c /* HSRUN Clock Control Register */ +#define S32K1XX_SCG_CLKOUTCNFG_OFFSET 0x0020 /* SCG CLKOUT Configuration Register */ +#define S32K1XX_SCG_SOSCCSR_OFFSET 0x0100 /* System OSC Control Status Register */ +#define S32K1XX_SCG_SOSCDIV_OFFSET 0x0104 /* System OSC Divide Register */ +#define S32K1XX_SCG_SOSCCFG_OFFSET 0x0108 /* System Oscillator Configuration Register */ +#define S32K1XX_SCG_SIRCCSR_OFFSET 0x0200 /* Slow IRC Control Status Register */ +#define S32K1XX_SCG_SIRCDIV_OFFSET 0x0204 /* Slow IRC Divide Register */ +#define S32K1XX_SCG_SIRCCFG_OFFSET 0x0208 /* Slow IRC Configuration Register */ +#define S32K1XX_SCG_FIRCCSR_OFFSET 0x0300 /* Fast IRC Control Status Register */ +#define S32K1XX_SCG_FIRCDIV_OFFSET 0x0304 /* Fast IRC Divide Register */ +#define S32K1XX_SCG_FIRCCFG_OFFSET 0x0308 /* Fast IRC Configuration Register */ +#define S32K1XX_SCG_SPLLCSR_OFFSET 0x0600 /* System PLL Control Status Register */ +#define S32K1XX_SCG_SPLLDIV_OFFSET 0x0604 /* System PLL Divide Register */ +#define S32K1XX_SCG_SPLLCFG_OFFSET 0x0608 /* System PLL Configuration Register */ + +/* SCG Register Addresses ***********************************************************/ + +#define S32K1XX_SCG_VERID (S32K1XX_SCG_BASE + S32K1XX_SCG_VERID_OFFSET) +#define S32K1XX_SCG_PARAM (S32K1XX_SCG_BASE + S32K1XX_SCG_PARAM_OFFSET) +#define S32K1XX_SCG_CSR (S32K1XX_SCG_BASE + S32K1XX_SCG_CSR_OFFSET) +#define S32K1XX_SCG_RCCR (S32K1XX_SCG_BASE + S32K1XX_SCG_RCCR_OFFSET) +#define S32K1XX_SCG_VCCR (S32K1XX_SCG_BASE + S32K1XX_SCG_VCCR_OFFSET) +#define S32K1XX_SCG_HCCR (S32K1XX_SCG_BASE + S32K1XX_SCG_HCCR_OFFSET) +#define S32K1XX_SCG_CLKOUTCNFG (S32K1XX_SCG_BASE + S32K1XX_SCG_CLKOUTCNFG_OFFSET) +#define S32K1XX_SCG_SOSCCSR (S32K1XX_SCG_BASE + S32K1XX_SCG_SOSCCSR_OFFSET) +#define S32K1XX_SCG_SOSCDIV (S32K1XX_SCG_BASE + S32K1XX_SCG_SOSCDIV_OFFSET) +#define S32K1XX_SCG_SOSCCFG (S32K1XX_SCG_BASE + S32K1XX_SCG_SOSCCFG_OFFSET) +#define S32K1XX_SCG_SIRCCSR (S32K1XX_SCG_BASE + S32K1XX_SCG_SIRCCSR_OFFSET) +#define S32K1XX_SCG_SIRCDIV (S32K1XX_SCG_BASE + S32K1XX_SCG_SIRCDIV_OFFSET) +#define S32K1XX_SCG_SIRCCFG (S32K1XX_SCG_BASE + S32K1XX_SCG_SIRCCFG_OFFSET) +#define S32K1XX_SCG_FIRCCSR (S32K1XX_SCG_BASE + S32K1XX_SCG_FIRCCSR_OFFSET) +#define S32K1XX_SCG_FIRCDIV (S32K1XX_SCG_BASE + S32K1XX_SCG_FIRCDIV_OFFSET) +#define S32K1XX_SCG_FIRCCFG (S32K1XX_SCG_BASE + S32K1XX_SCG_FIRCCFG_OFFSET) +#define S32K1XX_SCG_SPLLCSR (S32K1XX_SCG_BASE + S32K1XX_SCG_SPLLCSR_OFFSET) +#define S32K1XX_SCG_SPLLDIV (S32K1XX_SCG_BASE + S32K1XX_SCG_SPLLDIV_OFFSET) +#define S32K1XX_SCG_SPLLCFG (S32K1XX_SCG_BASE + S32K1XX_SCG_SPLLCFG_OFFSET) + +/* SCG Register Bitfield Definitions ************************************************/ + +/* Version ID Register (32-bit version number) */ + +/* Parameter Register */ + +#define SCG_PARAM_SOSC (1 << 1) /* System OSC (SOSC) clock present */ +#define SCG_PARAM_SIRC (1 << 2) /* Slow IRC (SIRC) clock present */ +#define SCG_PARAM_FIRC (1 << 3) /* Fast IRC (FIRC) clock present */ +#define SCG_PARAM_SPLL (1 << 6) /* System PLL (SPLL) clock present */ +#define SCG_PARAM_DIVSLOW (1 << 27) /* Bit 27: DIVSLOW clock divider present */ +#define SCG_PARAM_DIVBUS (1 << 28) /* Bit 28: DIVBUS clock divider present */ +#define SCG_PARAM_DIVCORE (1 << 31) /* Bit 31: DIVCORE clock divider present */ + +/* Clock Status Register */ + +#define SCG_CSR_DIVSLOW_SHIFT (0) /* Bits 0-3: Slow Clock Divide Ratio */ +#define SCG_CSR_DIVSLOW_MASK (15 << SCG_CSR_DIVSLOW_SHIFT) +# define SCG_CSR_DIVSLOW(n) ((uint32_t)((n) - 1) << SCG_CSR_DIVSLOW_SHIFT) /* n=1-8 */ +#define SCG_CSR_DIVBUS_SHIFT (4) /* Bits 4-7: Bus Clock Divide Ratio */ +#define SCG_CSR_DIVBUS_MASK (15 << SCG_CSR_DIVBUS_SHIFT) +# define SCG_CSR_DIVBUS(n) ((uint32_t)((n) - 1) << SCG_CSR_DIVBUS_SHIFT) /* n=1-16 */ +#define SCG_CSR_DIVCORE_SHIFT (16) /* Bits 16-19: Core Clock Divide Ratio */ +#define SCG_CSR_DIVCORE_MASK (15 << SCG_CSR_DIVCORE_SHIFT) +# define SCG_CSR_DIVCORE(n) ((uint32_t)((n) - 1) << SCG_CSR_DIVCORE_SHIFT) /* n=1-16 */ +#define SCG_CSR_SCS_SHIFT (24) /* Bits 24-27: System clock source */ +#define SCG_CSR_SCS_MASK (15 << SCG_CSR_SCS_SHIFT) +# define SCG_CSR_SCS_SOSC (1 << SCG_CSR_SCS_SHIFT) /* System OSC (SOSC_CLK) */ +# define SCG_CSR_SCS_SIRC (2 << SCG_CSR_SCS_SHIFT) /* Slow IRC (SIRC_CLK) */ +# define SCG_CSR_SCS_FIRC (3 << SCG_CSR_SCS_SHIFT) /* Fast IRC (FIRC_CLK) */ +# define SCG_CSR_SPLL_FIRC (6 << SCG_CSR_SCS_SHIFT) /* System PLL (SPLL_CLK) */ + +/* Run Clock Control Register */ + +#define SCG_RCCR_DIVSLOW_SHIFT (0) /* Bits 0-3: Slow Clock Divide Ratio */ +#define SCG_RCCR_DIVSLOW_MASK (15 << SCG_RCCR_DIVSLOW_SHIFT) +# define SCG_RCCR_DIVSLOW(n) ((uint32_t)((n) - 1) << SCG_RCCR_DIVSLOW_SHIFT) /* n=1-8 */ +#define SCG_RCCR_DIVBUS_SHIFT (4) /* Bits 4-7: Bus Clock Divide Ratio */ +#define SCG_RCCR_DIVBUS_MASK (15 << SCG_RCCR_DIVBUS_SHIFT) +# define SCG_RCCR_DIVBUS(n) ((uint32_t)((n) - 1) << SCG_RCCR_DIVBUS_SHIFT) /* n=1-16 */ +#define SCG_RCCR_DIVCORE_SHIFT (16) /* Bits 16-19: Core Clock Divide Ratio */ +#define SCG_RCCR_DIVCORE_MASK (15 << SCG_RCCR_DIVCORE_SHIFT) +# define SCG_RCCR_DIVCORE(n) ((uint32_t)((n) - 1) << SCG_RCCR_DIVCORE_SHIFT) /* n=1-16 */ +#define SCG_RCCR_SCS_SHIFT (24) /* Bits 24-27: System clock source */ +#define SCG_RCCR_SCS_MASK (15 << SCG_RCCR_SCS_SHIFT) +# define SCG_RCCR_SCS_SOSC (1 << SCG_RCCR_SCS_SHIFT) /* System OSC (SOSC_CLK) */ +# define SCG_RCCR_SCS_SIRC (2 << SCG_RCCR_SCS_SHIFT) /* Slow IRC (SIRC_CLK) */ +# define SCG_RCCR_SCS_FIRC (3 << SCG_RCCR_SCS_SHIFT) /* Fast IRC (FIRC_CLK) */ +# define SCG_RCCR_SPLL_FIRC (6 << SCG_RCCR_SCS_SHIFT) /* System PLL (SPLL_CLK) */ + +/* VLPR Clock Control Register */ + +#define SCG_VCCR_DIVSLOW_SHIFT (0) /* Bits 0-3: Slow Clock Divide Ratio */ +#define SCG_VCCR_DIVSLOW_MASK (15 << SCG_VCCR_DIVSLOW_SHIFT) +# define SCG_VCCR_DIVSLOW(n) ((uint32_t)((n) - 1) << SCG_VCCR_DIVSLOW_SHIFT) /* n=1-8 */ +#define SCG_VCCR_DIVBUS_SHIFT (4) /* Bits 4-7: Bus Clock Divide Ratio */ +#define SCG_VCCR_DIVBUS_MASK (15 << SCG_VCCR_DIVBUS_SHIFT) +# define SCG_VCCR_DIVBUS(n) ((uint32_t)((n) - 1) << SCG_VCCR_DIVBUS_SHIFT) /* n=1-16 */ +#define SCG_VCCR_DIVCORE_SHIFT (16) /* Bits 16-19: Core Clock Divide Ratio */ +#define SCG_VCCR_DIVCORE_MASK (15 << SCG_VCCR_DIVCORE_SHIFT) +# define SCG_VCCR_DIVCORE(n) ((uint32_t)((n) - 1) << SCG_VCCR_DIVCORE_SHIFT) /* n=1-16 */ +#define SCG_VCCR_SCS_SHIFT (24) /* Bits 24-27: System clock source */ +#define SCG_VCCR_SCS_MASK (15 << SCG_VCCR_SCS_SHIFT) +# define SCG_VCCR_SCS_SIRC (2 << SCG_VCCR_SCS_SHIFT) /* Slow IRC (SIRC_CLK) */ + +/* HSRUN Clock Control Register */ + +#define SCG_HCCR_DIVSLOW_SHIFT (0) /* Bits 0-3: Slow Clock Divide Ratio */ +#define SCG_HCCR_DIVSLOW_MASK (15 << SCG_HCCR_DIVSLOW_SHIFT) +# define SCG_HCCR_DIVSLOW(n) ((uint32_t)((n) - 1) << SCG_HCCR_DIVSLOW_SHIFT) /* n=1-8 */ +#define SCG_HCCR_DIVBUS_SHIFT (4) /* Bits 4-7: Bus Clock Divide Ratio */ +#define SCG_HCCR_DIVBUS_MASK (15 << SCG_HCCR_DIVBUS_SHIFT) +# define SCG_HCCR_DIVBUS(n) ((uint32_t)((n) - 1) << SCG_HCCR_DIVBUS_SHIFT) /* n=1-16 */ +#define SCG_HCCR_DIVCORE_SHIFT (16) /* Bits 16-19: Core Clock Divide Ratio */ +#define SCG_HCCR_DIVCORE_MASK (15 << SCG_HCCR_DIVCORE_SHIFT) +# define SCG_HCCR_DIVCORE(n) ((uint32_t)((n) - 1) << SCG_HCCR_DIVCORE_SHIFT) /* n=1-16 */ +#define SCG_HCCR_SCS_SHIFT (24) /* Bits 24-27: System clock source */ +#define SCG_HCCR_SCS_MASK (15 << SCG_HCCR_SCS_SHIFT) +# define SCG_HCCR_SCS_FIRC (3 << SCG_HCCR_SCS_SHIFT) /* Fast IRC (FIRC_CLK) */ +# define SCG_HCCR_SPLL_FIRC (6 << SCG_HCCR_SCS_SHIFT) /* System PLL (SPLL_CLK) */ + +/* SCG CLKOUT Configuration Register */ + +#define SCG_CLKOUTCNFG_SCS_SHIFT (24) /* Bits 24-27: SCG Clkout Select */ +#define SCG_CLKOUTCNFG_SCS_MASK (15 << SCG_CLKOUTCNFG_SCS_SHIFT) +# define SCG_CLKOUTCNFG_SCS_SOSC (1 << SCG_CLKOUTCNFG_SCS_SHIFT) /* System OSC (SOSC_CLK) */ +# define SCG_CLKOUTCNFG_SCS_SIRC (2 << SCG_CLKOUTCNFG_SCS_SHIFT) /* Slow IRC (SIRC_CLK) */ +# define SCG_CLKOUTCNFG_SCS_FIRC (3 << SCG_CLKOUTCNFG_SCS_SHIFT) /* Fast IRC (FIRC_CLK) */ +# define SCG_CLKOUTCNFG_SPLL_FIRC (6 << SCG_CLKOUTCNFG_SCS_SHIFT) /* System PLL (SPLL_CLK) */ + +/* System OSC Control Status Register */ + +#define SCG_SOSCCSR_SOSCEN (1 << 0) /* Bit 0: System OSC Enable */ +#define SCG_SOSCCSR_SOSCCM (1 << 16) /* Bit 16: System OSC Clock Monitor */ +#define SCG_SOSCCSR_SOSCCMRE (1 << 17) /* Bit 17: System OSC Clock Monitor Reset Enable */ +#define SCG_SOSCCSR_LK (1 << 23) /* Bit 23: Lock Register */ +#define SCG_SOSCCSR_SOSCVLD (1 << 24) /* Bit 24: System OSC Valid */ +#define SCG_SOSCCSR_SOSCSEL (1 << 25) /* Bit 25: System OSC Selected */ +#define SCG_SOSCCSR_SOSCERR (1 << 26) /* Bit 26: System OSC Clock Error */ + +/* System OSC Divide Register */ + +#define SCG_SOSCDIV_SOSCDIV1_SHIFT (0) /* Bits 0-2: System OSC Clock Divide 1 */ +#define SCG_SOSCDIV_SOSCDIV1_MASK (7 << SCG_SOSCDIV_SOSCDIV1_SHIFT) +# define SCG_SOSCDIV_SOSCDIV1_DISABLE (0 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Output disabled */ +# define SCG_SOSCDIV_SOSCDIV1_DIV1 (1 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 1 */ +# define SCG_SOSCDIV_SOSCDIV1_DIV2 (2 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 2 */ +# define SCG_SOSCDIV_SOSCDIV1_DIV4 (3 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 4 */ +# define SCG_SOSCDIV_SOSCDIV1_DIV8 (4 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 8 */ +# define SCG_SOSCDIV_SOSCDIV1_DIV16 (5 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 16 */ +# define SCG_SOSCDIV_SOSCDIV1_DIV32 (6 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 32 */ +# define SCG_SOSCDIV_SOSCDIV1_DIV64 (7 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 64 */ +#define SCG_SOSCDIV_SOSCDIV2_SHIFT (8) /* Bits 8-10: System OSC Clock Divide 2 */ +#define SCG_SOSCDIV_SOSCDIV2_MASK (7 << SCG_SOSCDIV_SOSCDIV2_SHIFT) +# define SCG_SOSCDIV_SOSCDIV2_DISABLE (0 << SCG_SOSCDIV_SOSCDIV2_SHIFT) /* Output disabled */ +# define SCG_SOSCDIV_SOSCDIV2_DIV1 (1 << SCG_SOSCDIV_SOSCDIV2_SHIFT) /* Divide by 1 */ +# define SCG_SOSCDIV_SOSCDIV2_DIV2 (2 << SCG_SOSCDIV_SOSCDIV2_SHIFT) /* Divide by 2 */ +# define SCG_SOSCDIV_SOSCDIV2_DIV4 (3 << SCG_SOSCDIV_SOSCDIV2_SHIFT) /* Divide by 4 */ +# define SCG_SOSCDIV_SOSCDIV2_DIV8 (4 << SCG_SOSCDIV_SOSCDIV2_SHIFT) /* Divide by 8 */ +# define SCG_SOSCDIV_SOSCDIV2_DIV16 (5 << SCG_SOSCDIV_SOSCDIV2_SHIFT) /* Divide by 16 */ +# define SCG_SOSCDIV_SOSCDIV2_DIV32 (6 << SCG_SOSCDIV_SOSCDIV2_SHIFT) /* Divide by 32 */ +# define SCG_SOSCDIV_SOSCDIV2_DIV64 (7 << SCG_SOSCDIV_SOSCDIV2_SHIFT) /* Divide by 64 */ + +/* System Oscillator Configuration Register */ + +#define SCG_SOSCCFG_EREFS (1 << 2) /* Bit 2: External Reference Select */ +#define SCG_SOSCCFG_HGO (1 << 3) /* Bit 3: High Gain Oscillator Select */ +#define SCG_SOSCCFG_RANGE_SHIFT (4) /* Bits 4-5: System OSC Range Select */ +#define SCG_SOSCCFG_RANGE_MASK (3 << SCG_SOSCCFG_RANGE_SHIFT) +# define SCG_SOSCCFG_RANGE_LOW (1 << SCG_SOSCCFG_RANGE_SHIFT) /* Low frequency range */ +# define SCG_SOSCCFG_RANGE_MED (2 << SCG_SOSCCFG_RANGE_SHIFT) /* Medium frequency range */ +# define SCG_SOSCCFG_RANGE_HIGH (3 << SCG_SOSCCFG_RANGE_SHIFT) /* High frequency range + +/* Slow IRC Control Status Register */ + +#define SCG_SIRCCSR_SIRCEN (1 << 0) /* Bit 0: Slow IRC Enable */ +#define SCG_SIRCCSR_SIRCSTEN (1 << 1) /* Bit 1: Slow IRC Stop Enable */ +#define SCG_SIRCCSR_SIRCLPEN (1 << 2) /* Bit 2: Slow IRC Low Power Enable */ +#define SCG_SIRCCSR_LK (1 << 23) /* Bit 23: Lock Register */ +#define SCG_SIRCCSR_SIRCVLD (1 << 24) /* Bit 24: Slow IRC Valid */ +#define SCG_SIRCCSR_SIRCSEL (1 << 25) /* Bit 25: Slow IRC Selected */ + +/* Slow IRC Divide Register */ + +#define SCG_SIRCDIV_SIRCDIV1_SHIFT (0) /* Bits 0-2: Slow IRC Clock Divide 1 */ +#define SCG_SIRCDIV_SIRCDIV1_MASK (7 << SCG_SIRCDIV_SIRCDIV1_SHIFT) +# define SCG_SIRCDIV_SIRCDIV1_DISABLE (0 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Output disabled */ +# define SCG_SIRCDIV_SIRCDIV1_DIV1 (1 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 1 */ +# define SCG_SIRCDIV_SIRCDIV1_DIV2 (2 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 2 */ +# define SCG_SIRCDIV_SIRCDIV1_DIV4 (3 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 4 */ +# define SCG_SIRCDIV_SIRCDIV1_DIV8 (4 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 8 */ +# define SCG_SIRCDIV_SIRCDIV1_DIV16 (5 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 16 */ +# define SCG_SIRCDIV_SIRCDIV1_DIV32 (6 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 32 */ +# define SCG_SIRCDIV_SIRCDIV1_DIV64 (7 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 64 */ +#define SCG_SIRCDIV_SIRCDIV2_SHIFT (8) /* Bits 8-10: Slow IRC Clock Divide 2 */ +#define SCG_SIRCDIV_SIRCDIV2_MASK (7 << SCG_SIRCDIV_SIRCDIV2_SHIFT) +# define SCG_SIRCDIV_SIRCDIV2_DISABLE (0 << SCG_SIRCDIV_SIRCDIV2_SHIFT) /* Output disabled */ +# define SCG_SIRCDIV_SIRCDIV2_DIV1 (1 << SCG_SIRCDIV_SIRCDIV2_SHIFT) /* Divide by 1 */ +# define SCG_SIRCDIV_SIRCDIV2_DIV2 (2 << SCG_SIRCDIV_SIRCDIV2_SHIFT) /* Divide by 2 */ +# define SCG_SIRCDIV_SIRCDIV2_DIV4 (3 << SCG_SIRCDIV_SIRCDIV2_SHIFT) /* Divide by 4 */ +# define SCG_SIRCDIV_SIRCDIV2_DIV8 (4 << SCG_SIRCDIV_SIRCDIV2_SHIFT) /* Divide by 8 */ +# define SCG_SIRCDIV_SIRCDIV2_DIV16 (5 << SCG_SIRCDIV_SIRCDIV2_SHIFT) /* Divide by 16 */ +# define SCG_SIRCDIV_SIRCDIV2_DIV32 (6 << SCG_SIRCDIV_SIRCDIV2_SHIFT) /* Divide by 32 */ +# define SCG_SIRCDIV_SIRCDIV2_DIV64 (7 << SCG_SIRCDIV_SIRCDIV2_SHIFT) /* Divide by 64 */ + +/* Slow IRC Configuration Register */ + +#define SCG_SIRCCFG_RANGE (1 << 0) /* Bit 0: Frequency Range */ +# define SCG_SIRCCFG_LOWRANGE (0) /* Slow IRC low range clock (2 MHz) */ +# define SCG_SIRCCFG_HIGHRANGE (1 << 0) /* Slow IRC high range clock (8 MHz ) */ + +/* Fast IRC Control Status Register */ + +#define SCG_FIRCCSR_FIRCEN (1 << 0) /* Bit 0: Fast IRC Enable */ +#define SCG_FIRCCSR_FIRCREGOFF (1 << 3) /* Bit 3: Fast IRC Regulator Enable */ +#define SCG_FIRCCSR_LK (1 << 23) /* Bit 23: Lock Register */ +#define SCG_FIRCCSR_FIRCVLD (1 << 24) /* Bit 24: Fast IRC Valid status */ +#define SCG_FIRCCSR_FIRCSEL (1 << 25) /* Bit 25: Fast IRC Selected status */ +#define SCG_FIRCCSR_FIRCERR (1 << 26) /* Bit 26: Fast IRC Clock Error */ + +/* Fast IRC Divide Register */ + +#define SCG_FIRCDIV_FIRCDIV1_SHIFT (0) /* Bits 0-2: Fast IRC Clock Divide 1 */ +#define SCG_FIRCDIV_FIRCDIV1_MASK (7 << SCG_FIRCDIV_FIRCDIV1_SHIFT) +# define SCG_FIRCDIV_FIRCDIV1_DISABLE (0 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Output disabled */ +# define SCG_FIRCDIV_FIRCDIV1_DIV1 (1 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 1 */ +# define SCG_FIRCDIV_FIRCDIV1_DIV2 (2 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 2 */ +# define SCG_FIRCDIV_FIRCDIV1_DIV4 (3 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 4 */ +# define SCG_FIRCDIV_FIRCDIV1_DIV8 (4 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 8 */ +# define SCG_FIRCDIV_FIRCDIV1_DIV16 (5 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 16 */ +# define SCG_FIRCDIV_FIRCDIV1_DIV32 (6 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 32 */ +# define SCG_FIRCDIV_FIRCDIV1_DIV64 (7 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 64 */ +#define SCG_FIRCDIV_FIRCDIV2_SHIFT (8) /* Bits 8-10: Fast IRC Clock Divide 2 */ +#define SCG_FIRCDIV_FIRCDIV2_MASK (7 << SCG_FIRCDIV_FIRCDIV2_SHIFT) +# define SCG_FIRCDIV_FIRCDIV2_DISABLE (0 << SCG_FIRCDIV_FIRCDIV2_SHIFT) /* Output disabled */ +# define SCG_FIRCDIV_FIRCDIV2_DIV1 (1 << SCG_FIRCDIV_FIRCDIV2_SHIFT) /* Divide by 1 */ +# define SCG_FIRCDIV_FIRCDIV2_DIV2 (2 << SCG_FIRCDIV_FIRCDIV2_SHIFT) /* Divide by 2 */ +# define SCG_FIRCDIV_FIRCDIV2_DIV4 (3 << SCG_FIRCDIV_FIRCDIV2_SHIFT) /* Divide by 4 */ +# define SCG_FIRCDIV_FIRCDIV2_DIV8 (4 << SCG_FIRCDIV_FIRCDIV2_SHIFT) /* Divide by 8 */ +# define SCG_FIRCDIV_FIRCDIV2_DIV16 (5 << SCG_FIRCDIV_FIRCDIV2_SHIFT) /* Divide by 16 */ +# define SCG_FIRCDIV_FIRCDIV2_DIV32 (6 << SCG_FIRCDIV_FIRCDIV2_SHIFT) /* Divide by 32 */ +# define SCG_FIRCDIV_FIRCDIV2_DIV64 (7 << SCG_FIRCDIV_FIRCDIV2_SHIFT) /* Divide by 64 */ + +/* Fast IRC Configuration Register */ + +#define SCG_FIRCCFG_RANGE (1 << 0) /* Bit 0: Frequency Range */ +# define SCG_FIRCCFG_48MHZ (0) /* Fast IRC is trimmed to 48 MHz */ + +/* System PLL Control Status Register */ + +#define SCG_SPLLCSR_SPLLEN (1 << 0) /* Bit 0: System PLL Enable */ +#define SCG_SPLLCSR_SPLLCM (1 << 16) /* Bit 16: System PLL Clock Monitor */ +#define SCG_SPLLCSR_SPLLCMRE (1 << 17) /* Bit 17: System PLL Clock Monitor Reset Enable */ +#define SCG_SPLLCSR_LK (1 << 23) /* Bit 23: Lock Register */ +#define SCG_SPLLCSR_SPLLVLD (1 << 24) /* Bit 24: System PLL Valid */ +#define SCG_SPLLCSR_SPLLSEL (1 << 25) /* Bit 25: System PLL Selected */ +#define SCG_SPLLCSR_SPLLERR (1 << 26) /* Bit 65: System PLL Clock Error */ + +/* System PLL Divide Register */ + +#define SCG_SPLLDIV_SPLLDIV1_SHIFT (0) /* Bits 0-2: System PLL Clock Divide 1 */ +#define SCG_SPLLDIV_SPLLDIV1_MASK (7 << SCG_SPLLDIV_SPLLDIV1_SHIFT) +# define SCG_SPLLDIV_SPLLDIV1_DISABLE (0 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Output disabled */ +# define SCG_SPLLDIV_SPLLDIV1_DIV1 (1 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 1 */ +# define SCG_SPLLDIV_SPLLDIV1_DIV2 (2 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 2 */ +# define SCG_SPLLDIV_SPLLDIV1_DIV4 (3 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 4 */ +# define SCG_SPLLDIV_SPLLDIV1_DIV8 (4 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 8 */ +# define SCG_SPLLDIV_SPLLDIV1_DIV16 (5 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 16 */ +# define SCG_SPLLDIV_SPLLDIV1_DIV32 (6 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 32 */ +# define SCG_SPLLDIV_SPLLDIV1_DIV64 (7 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 64 */ +#define SCG_SPLLDIV_SPLLDIV2_SHIFT (8) /* Bits 8-10: System PLL Clock Divide 2 */ +#define SCG_SPLLDIV_SPLLDIV2_MASK (7 << SCG_SPLLDIV_SPLLDIV2_SHIFT) +# define SCG_SPLLDIV_SPLLDIV2_DISABLE (0 << SCG_SPLLDIV_SPLLDIV2_SHIFT) /* Output disabled */ +# define SCG_SPLLDIV_SPLLDIV2_DIV1 (1 << SCG_SPLLDIV_SPLLDIV2_SHIFT) /* Divide by 1 */ +# define SCG_SPLLDIV_SPLLDIV2_DIV2 (2 << SCG_SPLLDIV_SPLLDIV2_SHIFT) /* Divide by 2 */ +# define SCG_SPLLDIV_SPLLDIV2_DIV4 (3 << SCG_SPLLDIV_SPLLDIV2_SHIFT) /* Divide by 4 */ +# define SCG_SPLLDIV_SPLLDIV2_DIV8 (4 << SCG_SPLLDIV_SPLLDIV2_SHIFT) /* Divide by 8 */ +# define SCG_SPLLDIV_SPLLDIV2_DIV16 (5 << SCG_SPLLDIV_SPLLDIV2_SHIFT) /* Divide by 16 */ +# define SCG_SPLLDIV_SPLLDIV2_DIV32 (6 << SCG_SPLLDIV_SPLLDIV2_SHIFT) /* Divide by 32 */ +# define SCG_SPLLDIV_SPLLDIV2_DIV64 (7 << SCG_SPLLDIV_SPLLDIV2_SHIFT) /* Divide by 64 */ + +/* System PLL Configuration Register */ + +#define SCG_SPLLCFG_PREDIV_SHIFT (8) /* Bits 8-10: PLL Reference Clock Divider */ +#define SCG_SPLLCFG_PREDIV_MASK (7 << SCG_SPLLCFG_PREDIV_SHIFT) +# define SCG_SPLLCFG_PREDIV(n) ((uint32_t)((n) - 1) << SCG_SPLLCFG_PREDIV_SHIFT) /* n=1..8 */ +#define SCG_SPLLCFG_MULT_SHIFT (16) /* Bits 16-20: System PLL Multiplier */ +#define SCG_SPLLCFG_MULT_MASK (31 << SCG_SPLLCFG_MULT_SHIFT) +# define SCG_SPLLCFG_MULT(n) ((uint32_t)((n) - 16) << SCG_SPLLCFG_MULT_SHIFT) /* n=16..47 */ + +#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SCG_H */ diff --git a/arch/arm/src/s32k1xx/s32K11x/Make.defs b/arch/arm/src/s32k1xx/s32K11x/Make.defs new file mode 100644 index 0000000000..49b2457d71 --- /dev/null +++ b/arch/arm/src/s32k1xx/s32K11x/Make.defs @@ -0,0 +1,72 @@ +############################################################################ +# arch/arm/src/s32k1xx/x32k11x/Make.defs +# +# Copyright (C) 2019 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Source files specific to the Cortex-M0+ + +HEAD_ASRC = + +CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S +CMN_ASRCS += up_switchcontext.S vfork.S + +CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c +CMN_CSRCS += up_initialstate.c up_releasepending.c up_reprioritizertr.c +CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_systemreset.c +CMN_CSRCS += up_unblocktask.c up_doirq.c up_hardfault.c up_svcall.c +CMN_CSRCS += up_vectors.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_signal_dispatch.c +CMN_UASRCS += up_signal_handler.S +endif + +ifeq ($(CONFIG_DEBUG_FEATURES),y) +CMN_CSRCS += up_dumpnvic.c +endif + +# Source file specific to the S32k11x family + +CHIP_ASRCS = +CHIP_CSRCS = s32k11x_irq.c s32k11x_lowputc.c s32k11x_port.c s32k11x_serial.c +CHIP_CSRCS += s32k11x_lpuart.c + +# Configuration-dependent S32k11x files + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += s32k11x_timerisr.c +endif + +# Make sure that this directory in included in the VPATH + +VPATH += chip/s32k11x diff --git a/arch/arm/src/s32k1xx/s32K14x/Make.defs b/arch/arm/src/s32k1xx/s32K14x/Make.defs new file mode 100644 index 0000000000..ad8716f783 --- /dev/null +++ b/arch/arm/src/s32k1xx/s32K14x/Make.defs @@ -0,0 +1,90 @@ +############################################################################ +# arch/arm/src/s32k14x/Make.defs +# +# Copyright (C) 2019 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Source files specific to the Cortex-M4F + +HEAD_ASRC = + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S + +ifeq ($(CONFIG_ARCH_SETJMP_H),y) +ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y) +CMN_ASRCS += up_setjmp.S +endif +endif + +CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c +CMN_CSRCS += up_doirq.c up_hardfault.c up_initialstate.c up_memfault.c +CMN_CSRCS += up_releasepending.c up_reprioritizertr.c up_schedulesigaction.c +CMN_CSRCS += up_sigdeliver.c up_svcall.c up_trigger_irq.c up_unblocktask.c + +ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_ASRCS += up_lazyexception.S +else +CMN_ASRCS += up_exception.S +endif +CMN_CSRCS += up_vectors.c + +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_mpu.c up_signal_dispatch.c +CMN_UASRCS += up_signal_handler.S +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CMN_ASRCS += up_fpu.S +CMN_CSRCS += up_copyarmstate.c +endif + +# Source file specific to the S32k11x family + +CHIP_ASRCS = +CHIP_CSRCS = s32k14x_irq.c s32k14x_clrpend.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += s32k14x_userspace.c s32k14x_mpuinit.c +endif + +ifeq ($(CONFIG_S32K1XX_ETHERNET),y) +CHIP_CSRCS += s32k14x_ethernet.c +endif + +# Make sure that this directory in included in the VPATH + +VPATH += chip/s32k14x