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SAML21. With these changes, the board now builds without error

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This commit is contained in:
Gregory Nutt 2015-05-22 10:36:37 -06:00
parent de6eb5c02b
commit bd23c4ad4e
7 changed files with 75 additions and 28 deletions
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7
arch/arm/src/samdl/sam_lowputc.c
View File

@ -295,13 +295,18 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
{
int ret;
/* Enable clocking to the SERCOM module in PM */
/* Enable clocking to the SERCOM module */
sercom_enable(config->sercom);
/* Configure the GCLKs for the SERCOM module */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
sercom_coreclk_configure(config->sercom, config->gclkgen, false);
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
sam_gclk_chan_enable(config->sercom + GCLK_CHAN_SERCOM0_CORE,
config->gclkgen);
#endif
sercom_slowclk_configure(BOARD_SERCOM_SLOW_GCLKGEN);
/* Set USART configuration according to the board configuration */

41
arch/arm/src/samdl/sam_sercom.c
View File

@ -87,6 +87,7 @@
*
****************************************************************************/
#ifdef CONFIG_ARCH_FAMILY_SAMD20
void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock)
{
uint16_t regval;
@ -126,6 +127,7 @@ void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock)
putreg16(regval, SAM_GCLK_CLKCTRL);
}
#endif
/****************************************************************************
* Name: sercom_slowclk_configure
@ -143,10 +145,46 @@ void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock)
void sercom_slowclk_configure(int gclkgen)
{
#if defined(CONFIG_ARCH_FAMILY_SAMDL21)
static bool configured = false;
#ifdef CONFIG_DEBUG
static uint8_t slowgen = 0xff;
#endif
/* Setup the SERCOMn_GCLK channel. This is common to all SERCOM modules
* and should be done only once.
*/
if (!configured)
{
/* Configure the common slow clock channel */
sam_gclk_chan_enable(BOARD_SERCOM_SLOW_GCLKCHAN, gclkgen);
/* The slow clock is now configured and should not be configured again. */
configured = true;
#ifdef CONFIG_DEBUG
slowgen = (uint8_t)clkgen;
#endif
}
#ifdef CONFIG_DEBUG
/* Already configured. This is okay provided that the same GCLK generator
* is being used. Otherwise, there is a problem.
*/
else
{
DEBUGASSERT((int)slowgen == clkgen);
}
#endif
#elif defined(CONFIG_ARCH_FAMILY_SAMD20)
static bool configured = false;
uint16_t regval;
/* Since GCLK_SERCOM_SLOW is shard amongst all SERCOM modules, it should
/* Since GCLK_SERCOM_SLOW is shared amongst all SERCOM modules, it should
* only be configured one time.
*/
@ -189,4 +227,5 @@ void sercom_slowclk_configure(int gclkgen)
configured = true;
}
#endif
}

2
arch/arm/src/samdl/sam_sercom.h
View File

@ -130,7 +130,9 @@ static inline void sercom_enable(int sercom)
*
****************************************************************************/
#ifdef CONFIG_ARCH_FAMILY_SAMD20
void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock);
#endif
/****************************************************************************
* Name: sercom_slowclk_configure

12
arch/arm/src/samdl/sam_spi.c
View File

@ -268,7 +268,7 @@ static struct sam_spidev_s g_spi0dev =
#if 0 /* Not used */
.irq = SAM_IRQ_SERCOM0,
#endif
.gclkgen = (BOARD_SERCOM0_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM0_GCLKGEN,
.pad0 = BOARD_SERCOM0_PINMAP_PAD0,
.pad1 = BOARD_SERCOM0_PINMAP_PAD1,
.pad2 = BOARD_SERCOM0_PINMAP_PAD2,
@ -320,7 +320,7 @@ static struct sam_spidev_s g_spi1dev =
#if 0 /* Not used */
.irq = SAM_IRQ_SERCOM1,
#endif
.gclkgen = (BOARD_SERCOM1_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM1_GCLKGEN,
.pad0 = BOARD_SERCOM1_PINMAP_PAD0,
.pad1 = BOARD_SERCOM1_PINMAP_PAD1,
.pad2 = BOARD_SERCOM1_PINMAP_PAD2,
@ -372,7 +372,7 @@ static struct sam_spidev_s g_spi2dev =
#if 0 /* Not used */
.irq = SAM_IRQ_SERCOM2,
#endif
.gclkgen = (BOARD_SERCOM2_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM2_GCLKGEN,
.pad0 = BOARD_SERCOM2_PINMAP_PAD0,
.pad1 = BOARD_SERCOM2_PINMAP_PAD1,
.pad2 = BOARD_SERCOM2_PINMAP_PAD2,
@ -424,7 +424,7 @@ static struct sam_spidev_s g_spi3dev =
#if 0 /* Not used */
.irq = SAM_IRQ_SERCOM3,
#endif
.gclkgen = (BOARD_SERCOM3_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM3_GCLKGEN,
.pad0 = BOARD_SERCOM3_PINMAP_PAD0,
.pad1 = BOARD_SERCOM3_PINMAP_PAD1,
.pad2 = BOARD_SERCOM3_PINMAP_PAD2,
@ -476,7 +476,7 @@ static struct sam_spidev_s g_spi4dev =
#if 0 /* Not used */
.irq = SAM_IRQ_SERCOM4,
#endif
.gclkgen = (BOARD_SERCOM4_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM4_GCLKGEN,
.pad0 = BOARD_SERCOM4_PINMAP_PAD0,
.pad1 = BOARD_SERCOM4_PINMAP_PAD1,
.pad2 = BOARD_SERCOM4_PINMAP_PAD2,
@ -528,7 +528,7 @@ static struct sam_spidev_s g_spi5dev =
#if 0 /* Not used */
.irq = SAM_IRQ_SERCOM5,
#endif
.gclkgen = (BOARD_SERCOM5_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM5_GCLKGEN,
.pad0 = BOARD_SERCOM5_PINMAP_PAD0,
.pad1 = BOARD_SERCOM5_PINMAP_PAD1,
.pad2 = BOARD_SERCOM5_PINMAP_PAD2,

12
arch/arm/src/samdl/sam_usart.c
View File

@ -63,7 +63,7 @@ const struct sam_usart_config_s g_usart0config =
.parity = CONFIG_USART0_PARITY,
.bits = CONFIG_USART0_BITS,
.irq = SAM_IRQ_SERCOM0,
.gclkgen = (BOARD_SERCOM0_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM0_GCLKGEN ,
.stopbits2 = CONFIG_USART0_2STOP,
.baud = CONFIG_USART0_BAUD,
.pad0 = BOARD_SERCOM0_PINMAP_PAD0,
@ -83,7 +83,7 @@ const struct sam_usart_config_s g_usart1config =
.parity = CONFIG_USART1_PARITY,
.bits = CONFIG_USART1_BITS,
.irq = SAM_IRQ_SERCOM1,
.gclkgen = (BOARD_SERCOM1_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM1_GCLKGEN,
.stopbits2 = CONFIG_USART1_2STOP,
.baud = CONFIG_USART1_BAUD,
.pad0 = BOARD_SERCOM1_PINMAP_PAD0,
@ -103,7 +103,7 @@ const struct sam_usart_config_s g_usart2config =
.parity = CONFIG_USART2_PARITY,
.bits = CONFIG_USART2_BITS,
.irq = SAM_IRQ_SERCOM2,
.gclkgen = (BOARD_SERCOM2_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM2_GCLKGEN,
.stopbits2 = CONFIG_USART2_2STOP,
.baud = CONFIG_USART2_BAUD,
.pad0 = BOARD_SERCOM2_PINMAP_PAD0,
@ -123,7 +123,7 @@ const struct sam_usart_config_s g_usart3config =
.parity = CONFIG_USART3_PARITY,
.bits = CONFIG_USART3_BITS,
.irq = SAM_IRQ_SERCOM3,
.gclkgen = (BOARD_SERCOM3_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM3_GCLKGEN,
.stopbits2 = CONFIG_USART3_2STOP,
.baud = CONFIG_USART3_BAUD,
.pad0 = BOARD_SERCOM3_PINMAP_PAD0,
@ -143,7 +143,7 @@ const struct sam_usart_config_s g_usart4config =
.parity = CONFIG_USART4_PARITY,
.bits = CONFIG_USART4_BITS,
.irq = SAM_IRQ_SERCOM4,
.gclkgen = (BOARD_SERCOM4_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM4_GCLKGEN,
.stopbits2 = CONFIG_USART4_2STOP,
.baud = CONFIG_USART4_BAUD,
.pad0 = BOARD_SERCOM4_PINMAP_PAD0,
@ -163,7 +163,7 @@ const struct sam_usart_config_s g_usart5config =
.parity = CONFIG_USART5_PARITY,
.bits = CONFIG_USART5_BITS,
.irq = SAM_IRQ_SERCOM5,
.gclkgen = (BOARD_SERCOM5_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
.gclkgen = BOARD_SERCOM5_GCLKGEN,
.stopbits2 = CONFIG_USART5_2STOP,
.baud = CONFIG_USART5_BAUD,
.pad0 = BOARD_SERCOM5_PINMAP_PAD0,

16
configs/samd20-xplained/include/board.h
View File

@ -179,7 +179,7 @@
* BOARD_DFLL_FINEVALUE - Value
*
* Closed loop mode only:
* BOARD_DFLL_GCLKGEN - See GCLK_CLKCTRL_GEN* definitions
* BOARD_DFLL_GCLKGEN - GCLK index
* BOARD_DFLL_MULTIPLIER - Value
* BOARD_DFLL_MAXCOARSESTEP - Value
* BOARD_DFLL_MAXFINESTEP - Value
@ -199,7 +199,7 @@
/* DFLL closed loop mode configuration */
#define BOARD_DFLL_SRCGCLKGEN GCLK_CLKCTRL_GEN1
#define BOARD_DFLL_SRCGCLKGEN 1
#define BOARD_DFLL_MULTIPLIER 6
#define BOARD_DFLL_QUICKLOCK 1
#define BOARD_DFLL_TRACKAFTERFINELOCK 1
@ -359,7 +359,7 @@
* to all SERCOM modules.
*/
#define BOARD_SERCOM_SLOW_GCLKGEN (GCLK_CLKCTRL_GEN0 >> GCLK_CLKCTRL_GEN_SHIFT)
#define BOARD_SERCOM_SLOW_GCLKGEN 0
/* SERCOM0 SPI is available on EXT1
*
@ -371,7 +371,7 @@
* 18 PA7 SERCOM0 PAD3 SPI SCK
*/
#define BOARD_SERCOM0_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM0_GCLKGEN 0
#define BOARD_SERCOM0_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
#define BOARD_SERCOM0_PINMAP_PAD0 PORT_SERCOM0_PAD0_2 /* SPI_MISO */
#define BOARD_SERCOM0_PINMAP_PAD1 0 /* microSD_SS */
@ -390,7 +390,7 @@
* 18 PA19 SERCOM1 PAD3 SPI SCK
*/
#define BOARD_SERCOM1_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM1_GCLKGEN 0
#define BOARD_SERCOM1_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
#define BOARD_SERCOM1_PINMAP_PAD0 PORT_SERCOM1_PAD0_1 /* SPI_MISO */
#define BOARD_SERCOM1_PINMAP_PAD1 0 /* microSD_SS */
@ -408,7 +408,7 @@
* PA25 SERCOM3 / USART RXD
*/
#define BOARD_SERCOM3_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM3_GCLKGEN 0
#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_RXPAD3 | USART_CTRLA_TXPAD2)
#define BOARD_SERCOM3_PINMAP_PAD0 0
#define BOARD_SERCOM3_PINMAP_PAD1 0
@ -432,7 +432,7 @@
* configurations.
*/
#define BOARD_SERCOM4_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM4_GCLKGEN 0
#if defined(CONFIG_SAMD20_XPLAINED_USART4_EXT1)
# define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0)
@ -466,7 +466,7 @@
* 18 PB23 SERCOM5 PAD3 SPI SCK
*/
#define BOARD_SERCOM5_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM5_GCLKGEN 0
#define BOARD_SERCOM5_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
#define BOARD_SERCOM5_PINMAP_PAD0 PORT_SERCOM5_PAD0_1 /* SPI_MISO */
#define BOARD_SERCOM5_PINMAP_PAD1 0 /* microSD_SS */

13
configs/saml21-xplained/include/board.h
View File

@ -413,7 +413,8 @@
* to all SERCOM modules.
*/
#define BOARD_SERCOM_SLOW_GCLKGEN (GCLK_CLKCTRL_GEN0 >> GCLK_CLKCTRL_GEN_SHIFT)
#define BOARD_SERCOM_SLOW_GCLKGEN 0
#define BOARD_SERCOM_SLOW_GCLKCHAN GCLK_CHAN_SERCOM0_SLOW
/* SERCOM0 SPI is available on EXT1
*
@ -425,7 +426,7 @@
* 18 PA7 SERCOM0 PAD3 SPI SCK
*/
#define BOARD_SERCOM0_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM0_GCLKGEN 0
#define BOARD_SERCOM0_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
#define BOARD_SERCOM0_PINMAP_PAD0 PORT_SERCOM0_PAD0_2 /* SPI_MISO */
#define BOARD_SERCOM0_PINMAP_PAD1 0 /* SPI_SS (not used) */
@ -444,7 +445,7 @@
* 20 VCC VCC VCC N/A
*/
#define BOARD_SERCOM1_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM1_GCLKGEN 0
#define BOARD_SERCOM1_MUXCONFIG (USART_CTRLA_TXPAD2 | USART_CTRLA_RXPAD3)
#define BOARD_SERCOM1_PINMAP_PAD0 0 /* (not used) */
#define BOARD_SERCOM1_PINMAP_PAD1 0 /* (not used) */
@ -462,7 +463,7 @@
* PA23 SERCOM3 PAD[1] / USART RXD
*/
#define BOARD_SERCOM3_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM3_GCLKGEN 0
#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0_2)
#define BOARD_SERCOM3_PINMAP_PAD0 PORT_SERCOM3_PAD0_1 /* USART TX */
#define BOARD_SERCOM3_PINMAP_PAD1 PORT_SERCOM3_PAD1_1 /* USART RX */
@ -481,7 +482,7 @@
* 20 VCC VCC VCC N/A
*/
#define BOARD_SERCOM4_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM4_GCLKGEN 0
#define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0_2)
#define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3 /* USART TX */
@ -501,7 +502,7 @@
* 18 PB23 SERCOM5 PAD3 SPI SCK
*/
#define BOARD_SERCOM5_GCLKGEN GCLK_CLKCTRL_GEN0
#define BOARD_SERCOM5_GCLKGEN 0
#define BOARD_SERCOM5_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
#define BOARD_SERCOM5_PINMAP_PAD0 PORT_SERCOM5_PAD0_1 /* SPI_MISO */
#define BOARD_SERCOM5_PINMAP_PAD1 0 /* SPI_SS (not used) */