arch/mips: Add cache operations. Cache is initialized at startup (head.S) and the different operations are implemented in up_cache.S.

arch/mips/include/mips32/cp0.h

@@ -73,6 +73,7 @@
 #  define MIPS32_CP0_DEBUG3         $23,0  /* Debug control and exception status */
 #  define MIPS32_CP0_DEPC3          $24,0  /* Program counter at last debug exception */
 #  define MIPS32_CP0_ERRCTL         $26,0  /* Controls access data CACHE instruction */
+#  define MIPS32_CP0_CACHEERR       $27,0  /* Cache error-detection logic */
 #  define MIPS32_CP0_TAGLO          $28,0  /* LS portion of cache tag interface */
 #  define MIPS32_CP0_DATALO         $28,1  /* LS portion of cache tag interface */
 #  define MIPS32_CP0_TAGHI          $29,0  /* MS portion of cache tag interface */
@@ -333,7 +334,9 @@
 #define CP0_CONFIG_BE               (1 << 15) /* Bit 15: Processor is running in big-endian mode */
 #define CP0_CONFIG_IMPL_SHIFT       (16)      /* Bits 16-30: Implementation dependent */
 #define CP0_CONFIG_IMPL_MASK        (0x7fff << CP0_CONFIG_IMPL_SHIFT)
-#define CP0_CONFIG_M                (1 << 31) /* Bit 31: Config1 register is implemented at select=1 */
+#define CP0_CONFIG_M_SHIFT         (31)
+#define CP0_CONFIG_M_MASK          (1 << CP0_CONFIG_M_SHIFT)
+#  define CP0_CONFIG_M             (1 << CP0_CONFIG_M_SHIFT) /* Bit 31: Indicates the presence of a Config1 register */
 
 /* Register Number: 16 Sel: 1 Name: Config1
  * Function: Configuration register 1

arch/mips/src/mips32/Kconfig

@@ -83,4 +83,75 @@ config MIPS32_FRAMEPOINTER
 		Register r30 may be a frame pointer in some ABIs.  Or may just be
 		saved register s8.  It makes a difference for vfork handling.
 
+config MIPS32_HAVE_ICACHE
+	bool
+	default n
+
+config MIPS32_HAVE_DCACHE
+	bool
+	default n
+
+config MIPS32_ICACHE
+	bool "Use I-Cache"
+	default n
+	depends on MIPS32_HAVE_ICACHE
+	select ARCH_ICACHE
+	---help---
+		Enable K0 I-Cache
+
+config MIPS32_ICACHE_SIZE
+	int "I-Cache Size"
+	default 16384
+	depends on MIPS32_ICACHE && !MIPS32_CACHE_AUTOINFO
+	---help---
+		Instruction cache size in bytes.
+
+config MIPS32_ILINE_SIZE
+	int "I-Cache Line Size"
+	default 16
+	depends on MIPS32_ICACHE && !MIPS32_CACHE_AUTOINFO
+	---help---
+		Instruction cache line size.
+
+config MIPS32_KSEG0_IBASE
+	hex "Instruction base address"
+	default 0x9d000000
+	depends on MIPS32_ICACHE
+	---help---
+		Instruction base address in KSEG0
+
+config MIPS32_DCACHE
+	bool "Use D-Cache"
+	default n
+	depends on MIPS32_HAVE_DCACHE
+	select ARCH_DCACHE
+	---help---
+		Enable K0 D-Cache
+
+config MIPS32_DCACHE_SIZE
+	int "D-Cache Size"
+	default 4096
+	depends on MIPS32_DCACHE && !MIPS32_CACHE_AUTOINFO
+	---help---
+		Data cache size in bytes.
+
+config MIPS32_DLINE_SIZE
+	int "D-Cache Line Size"
+	default 16
+	depends on MIPS32_DCACHE && !MIPS32_CACHE_AUTOINFO
+	---help---
+		Data cache line size.
+
+config MIPS32_KSEG0_DBASE
+	hex "Data base address"
+	default 0x80000000
+	depends on MIPS32_DCACHE
+	---help---
+		Data base address in KSEG0
+
+config MIPS32_CACHE_AUTOINFO
+	bool "Auto detect cache size"
+	depends on MIPS32_ICACHE || MIPS32_DCACHE
+	default n
+
 endif

arch/mips/src/pic32mz/Make.defs

@@ -39,7 +39,7 @@ HEAD_ASRC = pic32mz-head.S
 
 # Common MIPS files
 
-CMN_ASRCS  = up_syscall0.S vfork.S
+CMN_ASRCS  = up_syscall0.S vfork.S up_cache.S
 CMN_CSRCS  = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
 CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_initialize.c
 CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c

arch/mips/src/pic32mz/pic32mz-config.h

@@ -48,6 +48,12 @@
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
+
+/* Cache line sizes (in bytes) for the PIC32MZ */
+
+#define PIC32MZ_DCACHE_LINESIZE 16  /* 16 bytes (4 words) */
+#define PIC32MZ_ICACHE_LINESIZE 16  /* 16 bytes (4 words) */
+
 /* GPIO IRQs ************************************************************************/
 
 #ifndef CONFIG_PIC32MZ_GPIOIRQ

arch/mips/src/pic32mz/pic32mz-head.S

@@ -105,6 +105,46 @@
 #  define PIC32MZ_HEAP_BASE     PIC32MZ_STACK_TOP
 #endif
 
+#if defined (CONFIG_MIPS32_ICACHE) || defined (CONFIG_MIPS32_DCACHE)
+#  define K0_CACHE_ALGORITHM CP0_CONFIG_K0_CACHEABLE
+#else
+#  define K0_CACHE_ALGORITHM CP0_CONFIG_K0_UNCACHED
+#endif
+
+#ifdef CONFIG_MIPS32_ICACHE
+#  ifdef CONFIG_MIPS32_ICACHE_SIZE
+#    define PIC32MZ_ICACHE_SIZE CONFIG_MIPS32_ICACHE_SIZE
+#  else
+#    define PIC32MZ_ICACHE_SIZE 16384
+#  endif
+
+#  ifdef CONFIG_MIPS32_ILINE_SIZE
+#    define PIC32MZ_ILINE_SIZE CONFIG_MIPS32_ILINE_SIZE
+#  else
+#    define PIC32MZ_ILINE_SIZE 16
+#  endif
+
+#  define PIC32MZ_KSEG0_IBASE CONFIG_MIPS32_KSEG0_IBASE
+#  define PIC32MZ_INDEXSTORETAG_I 8
+#endif
+
+#ifdef CONFIG_MIPS32_DCACHE
+#  ifdef CONFIG_MIPS32_DCACHE_SIZE
+#    define PIC32MZ_DCACHE_SIZE CONFIG_MIPS32_DCACHE_SIZE
+#  else
+#    define PIC32MZ_DCACHE_SIZE 4096
+#  endif
+
+#  ifdef CONFIG_MIPS32_DLINE_SIZE
+#    define PIC32MZ_DLINE_SIZE CONFIG_MIPS32_DLINE_SIZE
+#  else
+#    define PIC32MZ_DLINE_SIZE 16
+#  endif
+
+#  define PIC32MZ_KSEG0_DBASE CONFIG_MIPS32_KSEG0_DBASE
+#  define PIC32MZ_INDEXSTORETAG_D 9
+#endif
+
 /****************************************************************************
  * Public Symbols
  ****************************************************************************/
@@ -401,6 +441,61 @@ __start:
 	mtc0	t3, PIC32MZ_CP0_SRSCTL	/* Restore SRSCtl */
 	ehb
 
+#if defined (CONFIG_MIPS32_ICACHE) || defined (CONFIG_MIPS32_DCACHE)
+  /* Initialize K0 Cache. The cache resets in an indeterminate state.
+   * We need to clear the tags and invalidate any data.
+   * It's done as follows:
+   *  1 - Clear the ErrCtl register to use the TagLo(1) register.
+   *  2 - Clear the TagLo register.
+   *  3 - Perform an IndexStoreTag for each line to copy the content of TagLo.
+   */
+
+  /* Clear ErrCtl and TagLo */
+
+  mtc0 zero, PIC32MZ_CP0_ERRCTL
+  mtc0 zero, PIC32MZ_CP0_TAGLO
+  ehb
+
+#ifdef CONFIG_MIPS32_ICACHE
+  /* Init I-Cache (Copy content of TagLo) */
+
+  li t0, PIC32MZ_KSEG0_IBASE
+  addu t1, t0, PIC32MZ_ICACHE_SIZE
+.icacheloop:
+  addu t0, t0, PIC32MZ_ILINE_SIZE
+  bne t0, t1, .icacheloop
+  cache PIC32MZ_INDEXSTORETAG_I, -4(t0)
+#endif
+
+#ifdef CONFIG_MIPS32_DCACHE
+  /* Init D-Cache (Copy content of TagLo) */
+
+  li t0, PIC32MZ_KSEG0_DBASE
+  addu t1, t0, PIC32MZ_DCACHE_SIZE
+.dcacheloop:
+  addu t0, t0, PIC32MZ_DLINE_SIZE
+  bne t0, t1, .dcacheloop
+  cache PIC32MZ_INDEXSTORETAG_D, -4(t0)
+#endif
+
+  /* Force memory synchronization */
+
+  sync
+
+#endif /* CONFIG_MIPS32_ICACHE || CONFIG_MIPS32_DCACHE */
+
+  /* Set the cache algorithm.
+   * If the cache was enable, then it has already been initiliazed and
+   * the cache algorithm will be set to write-back with write allocation.
+   * if not, just set the algorithm to uncached.
+   */
+
+  mfc0 t0, PIC32MZ_CP0_CONFIG
+  ori  t0, CP0_CONFIG_K0_MASK
+  xori t0, CP0_CONFIG_K0_MASK
+  ori  t0, K0_CACHE_ALGORITHM
+  mtc0 t0, PIC32MZ_CP0_CONFIG
+
 	/* Clear uninitialized data sections */
 
 	la		t0, _sbss