arch/risc-v: Remove dupped irq code from bl602
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
Xiang Xiao
parent
8532feda78
commit
bd57229f3c
@ -37,165 +37,141 @@
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/* Map RISC-V exception code to NuttX IRQ */
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/* IRQ 0-15 : (exception:interrupt=0) */
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#define BL602_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
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#define BL602_IRQ_IAFAULT (1) /* Instruction Address Fault */
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#define BL602_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
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#define BL602_IRQ_BPOINT (3) /* Break Point */
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#define BL602_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
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#define BL602_IRQ_LAFAULT (5) /* Load Access Fault */
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#define BL602_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
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#define BL602_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
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#define BL602_IRQ_ECALLU (8) /* Environment Call from U-mode */
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/* 9-10: Reserved */
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#define BL602_IRQ_ECALLM (11) /* Environment Call from M-mode */
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/* 12-15: Reserved */
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/* IRQ 16- : (async event:interrupt=1) */
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#define BL602_IRQ_NUM_BASE (16)
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#define BL602_IRQ_ASYNC (16)
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#define BL602_IRQ_MSOFT (BL602_IRQ_ASYNC + 3) /* Machine Software Int */
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#define BL602_IRQ_MTIMER (BL602_IRQ_ASYNC + 7) /* Machine Timer Int */
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#define BL602_IRQ_MEXT (BL602_IRQ_ASYNC + 11) /* Machine External Int */
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/* Machine Global External Interrupt */
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#define BL602_IRQ_BMX_ERR \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 0) /* BMX Error Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 0) /* BMX Error Interrupt */
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#define BL602_IRQ_BMX_TO \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 1) /* BMX Timeout Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 1) /* BMX Timeout Interrupt */
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#define BL602_IRQ_L1C_BMX_ERR \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 2) /* L1C BMX Error Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 2) /* L1C BMX Error Interrupt */
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#define BL602_IRQ_L1C_BMX_TO \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 3) /* L1C BMX Timeout Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 3) /* L1C BMX Timeout Interrupt */
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#define BL602_IRQ_SEC_BMX_ERR \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 4) /* SEC BMX Error Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 4) /* SEC BMX Error Interrupt */
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#define BL602_IRQ_RF_TOP_INT0 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 5) /* RF_TOP_INT0 Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 5) /* RF_TOP_INT0 Interrupt */
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#define BL602_IRQ_RF_TOP_INT1 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 6) /* RF_TOP_INT1 Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 6) /* RF_TOP_INT1 Interrupt */
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#define BL602_IRQ_SDIO \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 7) /* SDIO Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 7) /* SDIO Interrupt */
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#define BL602_IRQ_DMA_BMX_ERR \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 8) /* DMA BMX Error Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 8) /* DMA BMX Error Interrupt */
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#define BL602_IRQ_SEC_GMAC \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 9) /* SEC_ENG_GMAC_INT Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 9) /* SEC_ENG_GMAC_INT Interrupt */
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#define BL602_IRQ_SEC_CDET \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 10) /* SEC_ENG_CDET_INT Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 10) /* SEC_ENG_CDET_INT Interrupt */
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#define BL602_IRQ_SEC_PKA \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 11) /* SEC_ENG_PKA_INT Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 11) /* SEC_ENG_PKA_INT Interrupt */
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#define BL602_IRQ_SEC_TRNG \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 12) /* SEC_ENG_TRNG_INT Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 12) /* SEC_ENG_TRNG_INT Interrupt */
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#define BL602_IRQ_SEC_AES \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 13) /* SEC_ENG_AES_INT Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 13) /* SEC_ENG_AES_INT Interrupt */
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#define BL602_IRQ_SEC_SHA \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 14) /* SEC_ENG_SHA_INT Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 14) /* SEC_ENG_SHA_INT Interrupt */
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#define BL602_IRQ_DMA_ALL \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 15) /* DMA ALL Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 15) /* DMA ALL Interrupt */
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#define BL602_IRQ_RESERVED0 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 16) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 16) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED1 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 17) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 17) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED2 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 18) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 18) /* RESERVED Interrupt */
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#define BL602_IRQ_IRTX_IRQn \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 19) /* IR TX Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 19) /* IR TX Interrupt */
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#define BL602_IRQ_IRRX_IRQn \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 20) /* IR RX Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 20) /* IR RX Interrupt */
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#define BL602_IRQ_RESERVED3 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 21) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 21) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED4 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 22) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 22) /* RESERVED Interrupt */
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#define BL602_IRQ_SF_CTRL \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 23) /* SF_CTRL Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 23) /* SF_CTRL Interrupt */
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#define BL602_IRQ_RESERVED5 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 24) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 24) /* RESERVED Interrupt */
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#define BL602_IRQ_GPADC_DMA \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 25) /* GPADC_DMA Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 25) /* GPADC_DMA Interrupt */
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#define BL602_IRQ_EFUSE \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 26) /* Efuse Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 26) /* Efuse Interrupt */
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#define BL602_IRQ_SPI \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 27) /* SPI Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 27) /* SPI Interrupt */
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#define BL602_IRQ_RESERVED6 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 28) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 28) /* RESERVED Interrupt */
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#define BL602_IRQ_UART0 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 29) /* UART Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 29) /* UART Interrupt */
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#define BL602_IRQ_UART1 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 30) /* UART1 Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 30) /* UART1 Interrupt */
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#define BL602_IRQ_RESERVED7 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 31) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 31) /* RESERVED Interrupt */
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#define BL602_IRQ_I2C \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 32) /* I2C Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 32) /* I2C Interrupt */
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#define BL602_IRQ_RESERVED8 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 33) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 33) /* RESERVED Interrupt */
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#define BL602_IRQ_PWM \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 34) /* PWM Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 34) /* PWM Interrupt */
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#define BL602_IRQ_RESERVED9 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 35) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 35) /* RESERVED Interrupt */
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#define BL602_IRQ_TIMER_CH0 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 36) /* Timer Channel 0 Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 36) /* Timer Channel 0 Interrupt */
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#define BL602_IRQ_TIMER_CH1 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 37) /* Timer Channel 1 Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 37) /* Timer Channel 1 Interrupt */
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#define BL602_IRQ_TIMER_WDT \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 38) /* Timer Watch Dog Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 38) /* Timer Watch Dog Interrupt */
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#define BL602_IRQ_RESERVED10 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 39) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 39) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED11 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 40) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 40) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED12 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 41) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 41) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED13 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 42) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 42) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED14 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 43) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 43) /* RESERVED Interrupt */
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#define BL602_IRQ_GPIO_INT0 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 44) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 44) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED16 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 45) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 45) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED17 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 46) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 46) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED18 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 47) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 47) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED19 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 48) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 48) /* RESERVED Interrupt */
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#define BL602_IRQ_RESERVED20 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 49) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 49) /* RESERVED Interrupt */
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#define BL602_IRQ_PDS_WAKEUP \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 50) /* PDS Wakeup Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 50) /* PDS Wakeup Interrupt */
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#define BL602_IRQ_HBN_OUT0 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 51) /* Hibernate out 0 Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 51) /* Hibernate out 0 Interrupt */
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#define BL602_IRQ_HBN_OUT1 \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 52) /* Hibernate out 1 Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 52) /* Hibernate out 1 Interrupt */
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#define BL602_IRQ_BOR \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 53) /* BOR Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 53) /* BOR Interrupt */
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#define BL602_IRQ_WIFI \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 54) /* WIFI To CPU Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 54) /* WIFI To CPU Interrupt */
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#define BL602_IRQ_BZ_PHY \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 55) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 55) /* RESERVED Interrupt */
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#define BL602_IRQ_BLE \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 56) /* RESERVED Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 56) /* RESERVED Interrupt */
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#define BL602_IRQ_MAC_TXRX_TIMER \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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57) /* mac_int_tx_rx_timer Interrupt */
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#define BL602_IRQ_MAC_TXRX_MISC \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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58) /* mac_int_tx_rx_misc Interrupt */
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#define BL602_IRQ_MAC_RX_TRG \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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59) /* mac_int_rx_trigger Interrupt */
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#define BL602_IRQ_MAC_TX_TRG \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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60) /* mac_int_tx_trigger Interrupt */
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#define BL602_IRQ_MAC_GEN \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 61) /* mac_int_gen Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 61) /* mac_int_gen Interrupt */
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#define BL602_IRQ_MAC_PORT_TRG \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
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62) /* mac_int_port_trigger Interrupt */
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#define BL602_IRQ_WIFI_IPC_PUBLIC \
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(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 63) /* wifi IPC public Interrupt */
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(RISCV_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 63) /* wifi IPC public Interrupt */
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/* Total number of IRQs */
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@ -92,7 +92,7 @@ void up_irqinitialize(void)
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/* Attach the ecall interrupt handler */
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irq_attach(BL602_IRQ_ECALLM, riscv_swint, NULL);
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irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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@ -114,13 +114,13 @@ void up_disable_irq(int irq)
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{
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uint32_t oldstat;
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if (irq == BL602_IRQ_MSOFT)
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if (irq == RISCV_IRQ_MSOFT)
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{
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/* Read mstatus & clear machine software interrupt enable in mie */
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asm volatile("csrrc %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE));
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}
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else if (irq == BL602_IRQ_MTIMER)
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else if (irq == RISCV_IRQ_MTIMER)
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{
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putreg8(0, CLIC_TIMER_ENABLE_ADDRESS);
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@ -130,8 +130,8 @@ void up_disable_irq(int irq)
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}
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else
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{
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ASSERT(irq < 64 + 16 + BL602_IRQ_ASYNC);
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bl_irq_disable(irq - BL602_IRQ_ASYNC);
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ASSERT(irq < 64 + 16 + RISCV_IRQ_ASYNC);
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bl_irq_disable(irq - RISCV_IRQ_ASYNC);
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}
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}
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@ -147,13 +147,13 @@ void up_enable_irq(int irq)
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{
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uint32_t oldstat;
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if (irq == BL602_IRQ_MSOFT)
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if (irq == RISCV_IRQ_MSOFT)
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{
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/* Read mstatus & set machine software interrupt enable in mie */
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asm volatile("csrrs %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE));
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}
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else if (irq == BL602_IRQ_MTIMER)
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else if (irq == RISCV_IRQ_MTIMER)
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{
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putreg8(1, CLIC_TIMER_ENABLE_ADDRESS);
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@ -165,8 +165,8 @@ void up_enable_irq(int irq)
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}
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else
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{
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ASSERT(irq < 64 + 16 + BL602_IRQ_ASYNC);
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bl_irq_enable(irq - BL602_IRQ_ASYNC);
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ASSERT(irq < 64 + 16 + RISCV_IRQ_ASYNC);
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bl_irq_enable(irq - RISCV_IRQ_ASYNC);
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}
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}
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@ -60,12 +60,12 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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if (vector & 0x80000000u)
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{
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irq += BL602_IRQ_ASYNC;
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irq += RISCV_IRQ_ASYNC;
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}
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/* NOTE: In case of ecall, we need to adjust mepc in the context */
|
||||
|
||||
if (BL602_IRQ_ECALLM == irq)
|
||||
if (RISCV_IRQ_ECALLM == irq)
|
||||
{
|
||||
*mepc += 4;
|
||||
}
|
||||
|
||||
@ -138,7 +138,7 @@ void up_timer_initialize(void)
|
||||
{
|
||||
/* Attach timer interrupt handler */
|
||||
|
||||
irq_attach(BL602_IRQ_MTIMER, bl602_timerisr, NULL);
|
||||
irq_attach(RISCV_IRQ_MTIMER, bl602_timerisr, NULL);
|
||||
|
||||
/* Reload CLINT mtimecmp */
|
||||
|
||||
@ -146,5 +146,5 @@ void up_timer_initialize(void)
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(BL602_IRQ_MTIMER);
|
||||
up_enable_irq(RISCV_IRQ_MTIMER);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user